1 /* 2 * MFD driver for twl6040 3 * 4 * Authors: Jorge Eduardo Candelaria <[email protected]> 5 * Misael Lopez Cruz <[email protected]> 6 * 7 * Copyright: (C) 2011 Texas Instruments, Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 */ 24 25 #ifndef __TWL6040_CODEC_H__ 26 #define __TWL6040_CODEC_H__ 27 28 #include <linux/interrupt.h> 29 #include <linux/mfd/core.h> 30 #include <linux/regulator/consumer.h> 31 32 #define TWL6040_REG_ASICID 0x01 33 #define TWL6040_REG_ASICREV 0x02 34 #define TWL6040_REG_INTID 0x03 35 #define TWL6040_REG_INTMR 0x04 36 #define TWL6040_REG_NCPCTL 0x05 37 #define TWL6040_REG_LDOCTL 0x06 38 #define TWL6040_REG_HPPLLCTL 0x07 39 #define TWL6040_REG_LPPLLCTL 0x08 40 #define TWL6040_REG_LPPLLDIV 0x09 41 #define TWL6040_REG_AMICBCTL 0x0A 42 #define TWL6040_REG_DMICBCTL 0x0B 43 #define TWL6040_REG_MICLCTL 0x0C 44 #define TWL6040_REG_MICRCTL 0x0D 45 #define TWL6040_REG_MICGAIN 0x0E 46 #define TWL6040_REG_LINEGAIN 0x0F 47 #define TWL6040_REG_HSLCTL 0x10 48 #define TWL6040_REG_HSRCTL 0x11 49 #define TWL6040_REG_HSGAIN 0x12 50 #define TWL6040_REG_EARCTL 0x13 51 #define TWL6040_REG_HFLCTL 0x14 52 #define TWL6040_REG_HFLGAIN 0x15 53 #define TWL6040_REG_HFRCTL 0x16 54 #define TWL6040_REG_HFRGAIN 0x17 55 #define TWL6040_REG_VIBCTLL 0x18 56 #define TWL6040_REG_VIBDATL 0x19 57 #define TWL6040_REG_VIBCTLR 0x1A 58 #define TWL6040_REG_VIBDATR 0x1B 59 #define TWL6040_REG_HKCTL1 0x1C 60 #define TWL6040_REG_HKCTL2 0x1D 61 #define TWL6040_REG_GPOCTL 0x1E 62 #define TWL6040_REG_ALB 0x1F 63 #define TWL6040_REG_DLB 0x20 64 #define TWL6040_REG_TRIM1 0x28 65 #define TWL6040_REG_TRIM2 0x29 66 #define TWL6040_REG_TRIM3 0x2A 67 #define TWL6040_REG_HSOTRIM 0x2B 68 #define TWL6040_REG_HFOTRIM 0x2C 69 #define TWL6040_REG_ACCCTL 0x2D 70 #define TWL6040_REG_STATUS 0x2E 71 72 /* INTID (0x03) fields */ 73 74 #define TWL6040_THINT 0x01 75 #define TWL6040_PLUGINT 0x02 76 #define TWL6040_UNPLUGINT 0x04 77 #define TWL6040_HOOKINT 0x08 78 #define TWL6040_HFINT 0x10 79 #define TWL6040_VIBINT 0x20 80 #define TWL6040_READYINT 0x40 81 82 /* INTMR (0x04) fields */ 83 84 #define TWL6040_THMSK 0x01 85 #define TWL6040_PLUGMSK 0x02 86 #define TWL6040_HOOKMSK 0x08 87 #define TWL6040_HFMSK 0x10 88 #define TWL6040_VIBMSK 0x20 89 #define TWL6040_READYMSK 0x40 90 #define TWL6040_ALLINT_MSK 0x7B 91 92 /* NCPCTL (0x05) fields */ 93 94 #define TWL6040_NCPENA 0x01 95 #define TWL6040_NCPOPEN 0x40 96 97 /* LDOCTL (0x06) fields */ 98 99 #define TWL6040_LSLDOENA 0x01 100 #define TWL6040_HSLDOENA 0x04 101 #define TWL6040_REFENA 0x40 102 #define TWL6040_OSCENA 0x80 103 104 /* HPPLLCTL (0x07) fields */ 105 106 #define TWL6040_HPLLENA 0x01 107 #define TWL6040_HPLLRST 0x02 108 #define TWL6040_HPLLBP 0x04 109 #define TWL6040_HPLLSQRENA 0x08 110 #define TWL6040_MCLK_12000KHZ (0 << 5) 111 #define TWL6040_MCLK_19200KHZ (1 << 5) 112 #define TWL6040_MCLK_26000KHZ (2 << 5) 113 #define TWL6040_MCLK_38400KHZ (3 << 5) 114 #define TWL6040_MCLK_MSK 0x60 115 116 /* LPPLLCTL (0x08) fields */ 117 118 #define TWL6040_LPLLENA 0x01 119 #define TWL6040_LPLLRST 0x02 120 #define TWL6040_LPLLSEL 0x04 121 #define TWL6040_LPLLFIN 0x08 122 #define TWL6040_HPLLSEL 0x10 123 124 /* HSLCTL/R (0x10/0x11) fields */ 125 126 #define TWL6040_HSDACENA (1 << 0) 127 #define TWL6040_HSDACMODE (1 << 1) 128 #define TWL6040_HSDRVMODE (1 << 3) 129 130 /* VIBCTLL/R (0x18/0x1A) fields */ 131 132 #define TWL6040_VIBENA (1 << 0) 133 #define TWL6040_VIBSEL (1 << 1) 134 #define TWL6040_VIBCTRL (1 << 2) 135 #define TWL6040_VIBCTRL_P (1 << 3) 136 #define TWL6040_VIBCTRL_N (1 << 4) 137 138 /* VIBDATL/R (0x19/0x1B) fields */ 139 140 #define TWL6040_VIBDAT_MAX 0x64 141 142 /* GPOCTL (0x1E) fields */ 143 144 #define TWL6040_GPO1 0x01 145 #define TWL6040_GPO2 0x02 146 #define TWL6040_GPO3 0x03 147 148 /* ACCCTL (0x2D) fields */ 149 150 #define TWL6040_I2CSEL 0x01 151 #define TWL6040_RESETSPLIT 0x04 152 #define TWL6040_INTCLRMODE 0x08 153 154 /* STATUS (0x2E) fields */ 155 156 #define TWL6040_PLUGCOMP 0x02 157 #define TWL6040_VIBLOCDET 0x10 158 #define TWL6040_VIBROCDET 0x20 159 #define TWL6040_TSHUTDET 0x40 160 161 #define TWL6040_CELLS 2 162 163 #define TWL6040_REV_ES1_0 0x00 164 #define TWL6040_REV_ES1_1 0x01 /* Rev ES1.1 and ES1.2 */ 165 #define TWL6040_REV_ES1_3 0x02 166 167 #define TWL6040_IRQ_TH 0 168 #define TWL6040_IRQ_PLUG 1 169 #define TWL6040_IRQ_HOOK 2 170 #define TWL6040_IRQ_HF 3 171 #define TWL6040_IRQ_VIB 4 172 #define TWL6040_IRQ_READY 5 173 174 /* PLL selection */ 175 #define TWL6040_SYSCLK_SEL_LPPLL 0 176 #define TWL6040_SYSCLK_SEL_HPPLL 1 177 178 struct twl6040_codec_data { 179 u16 hs_left_step; 180 u16 hs_right_step; 181 u16 hf_left_step; 182 u16 hf_right_step; 183 }; 184 185 struct twl6040_vibra_data { 186 unsigned int vibldrv_res; /* left driver resistance */ 187 unsigned int vibrdrv_res; /* right driver resistance */ 188 unsigned int viblmotor_res; /* left motor resistance */ 189 unsigned int vibrmotor_res; /* right motor resistance */ 190 int vddvibl_uV; /* VDDVIBL volt, set 0 for fixed reg */ 191 int vddvibr_uV; /* VDDVIBR volt, set 0 for fixed reg */ 192 }; 193 194 struct twl6040_platform_data { 195 int audpwron_gpio; /* audio power-on gpio */ 196 unsigned int irq_base; 197 198 struct twl6040_codec_data *codec; 199 struct twl6040_vibra_data *vibra; 200 }; 201 202 struct regmap; 203 204 struct twl6040 { 205 struct device *dev; 206 struct regmap *regmap; 207 struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */ 208 struct mutex mutex; 209 struct mutex irq_mutex; 210 struct mfd_cell cells[TWL6040_CELLS]; 211 struct completion ready; 212 213 int audpwron; 214 int power_count; 215 int rev; 216 u8 vibra_ctrl_cache[2]; 217 218 /* PLL configuration */ 219 int pll; 220 unsigned int sysclk; 221 unsigned int mclk; 222 223 unsigned int irq; 224 unsigned int irq_base; 225 u8 irq_masks_cur; 226 u8 irq_masks_cache; 227 }; 228 229 int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg); 230 int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg, 231 u8 val); 232 int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg, 233 u8 mask); 234 int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg, 235 u8 mask); 236 int twl6040_power(struct twl6040 *twl6040, int on); 237 int twl6040_set_pll(struct twl6040 *twl6040, int pll_id, 238 unsigned int freq_in, unsigned int freq_out); 239 int twl6040_get_pll(struct twl6040 *twl6040); 240 unsigned int twl6040_get_sysclk(struct twl6040 *twl6040); 241 int twl6040_irq_init(struct twl6040 *twl6040); 242 void twl6040_irq_exit(struct twl6040 *twl6040); 243 /* Get the combined status of the vibra control register */ 244 int twl6040_get_vibralr_status(struct twl6040 *twl6040); 245 246 static inline int twl6040_get_revid(struct twl6040 *twl6040) 247 { 248 return twl6040->rev; 249 } 250 251 252 #endif /* End of __TWL6040_CODEC_H__ */ 253