1 /* 2 * tps65910.h -- TI TPS6591x 3 * 4 * Copyright 2010-2011 Texas Instruments Inc. 5 * 6 * Author: Graeme Gregory <[email protected]> 7 * Author: Jorge Eduardo Candelaria <[email protected]> 8 * Author: Arnaud Deconinck <[email protected]> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 17 #ifndef __LINUX_MFD_TPS65910_H 18 #define __LINUX_MFD_TPS65910_H 19 20 /* TPS chip id list */ 21 #define TPS65910 0 22 #define TPS65911 1 23 24 /* TPS regulator type list */ 25 #define REGULATOR_LDO 0 26 #define REGULATOR_DCDC 1 27 28 /* 29 * List of registers for component TPS65910 30 * 31 */ 32 33 #define TPS65910_SECONDS 0x0 34 #define TPS65910_MINUTES 0x1 35 #define TPS65910_HOURS 0x2 36 #define TPS65910_DAYS 0x3 37 #define TPS65910_MONTHS 0x4 38 #define TPS65910_YEARS 0x5 39 #define TPS65910_WEEKS 0x6 40 #define TPS65910_ALARM_SECONDS 0x8 41 #define TPS65910_ALARM_MINUTES 0x9 42 #define TPS65910_ALARM_HOURS 0xA 43 #define TPS65910_ALARM_DAYS 0xB 44 #define TPS65910_ALARM_MONTHS 0xC 45 #define TPS65910_ALARM_YEARS 0xD 46 #define TPS65910_RTC_CTRL 0x10 47 #define TPS65910_RTC_STATUS 0x11 48 #define TPS65910_RTC_INTERRUPTS 0x12 49 #define TPS65910_RTC_COMP_LSB 0x13 50 #define TPS65910_RTC_COMP_MSB 0x14 51 #define TPS65910_RTC_RES_PROG 0x15 52 #define TPS65910_RTC_RESET_STATUS 0x16 53 #define TPS65910_BCK1 0x17 54 #define TPS65910_BCK2 0x18 55 #define TPS65910_BCK3 0x19 56 #define TPS65910_BCK4 0x1A 57 #define TPS65910_BCK5 0x1B 58 #define TPS65910_PUADEN 0x1C 59 #define TPS65910_REF 0x1D 60 #define TPS65910_VRTC 0x1E 61 #define TPS65910_VIO 0x20 62 #define TPS65910_VDD1 0x21 63 #define TPS65910_VDD1_OP 0x22 64 #define TPS65910_VDD1_SR 0x23 65 #define TPS65910_VDD2 0x24 66 #define TPS65910_VDD2_OP 0x25 67 #define TPS65910_VDD2_SR 0x26 68 #define TPS65910_VDD3 0x27 69 #define TPS65910_VDIG1 0x30 70 #define TPS65910_VDIG2 0x31 71 #define TPS65910_VAUX1 0x32 72 #define TPS65910_VAUX2 0x33 73 #define TPS65910_VAUX33 0x34 74 #define TPS65910_VMMC 0x35 75 #define TPS65910_VPLL 0x36 76 #define TPS65910_VDAC 0x37 77 #define TPS65910_THERM 0x38 78 #define TPS65910_BBCH 0x39 79 #define TPS65910_DCDCCTRL 0x3E 80 #define TPS65910_DEVCTRL 0x3F 81 #define TPS65910_DEVCTRL2 0x40 82 #define TPS65910_SLEEP_KEEP_LDO_ON 0x41 83 #define TPS65910_SLEEP_KEEP_RES_ON 0x42 84 #define TPS65910_SLEEP_SET_LDO_OFF 0x43 85 #define TPS65910_SLEEP_SET_RES_OFF 0x44 86 #define TPS65910_EN1_LDO_ASS 0x45 87 #define TPS65910_EN1_SMPS_ASS 0x46 88 #define TPS65910_EN2_LDO_ASS 0x47 89 #define TPS65910_EN2_SMPS_ASS 0x48 90 #define TPS65910_EN3_LDO_ASS 0x49 91 #define TPS65910_SPARE 0x4A 92 #define TPS65910_INT_STS 0x50 93 #define TPS65910_INT_MSK 0x51 94 #define TPS65910_INT_STS2 0x52 95 #define TPS65910_INT_MSK2 0x53 96 #define TPS65910_INT_STS3 0x54 97 #define TPS65910_INT_MSK3 0x55 98 #define TPS65910_GPIO0 0x60 99 #define TPS65910_GPIO1 0x61 100 #define TPS65910_GPIO2 0x62 101 #define TPS65910_GPIO3 0x63 102 #define TPS65910_GPIO4 0x64 103 #define TPS65910_GPIO5 0x65 104 #define TPS65910_GPIO6 0x66 105 #define TPS65910_GPIO7 0x67 106 #define TPS65910_GPIO8 0x68 107 #define TPS65910_JTAGVERNUM 0x80 108 #define TPS65910_MAX_REGISTER 0x80 109 110 /* 111 * List of registers specific to TPS65911 112 */ 113 #define TPS65911_VDDCTRL 0x27 114 #define TPS65911_VDDCTRL_OP 0x28 115 #define TPS65911_VDDCTRL_SR 0x29 116 #define TPS65911_LDO1 0x30 117 #define TPS65911_LDO2 0x31 118 #define TPS65911_LDO5 0x32 119 #define TPS65911_LDO8 0x33 120 #define TPS65911_LDO7 0x34 121 #define TPS65911_LDO6 0x35 122 #define TPS65911_LDO4 0x36 123 #define TPS65911_LDO3 0x37 124 #define TPS65911_VMBCH 0x6A 125 #define TPS65911_VMBCH2 0x6B 126 127 /* 128 * List of register bitfields for component TPS65910 129 * 130 */ 131 132 133 /*Register BCK1 (0x80) register.RegisterDescription */ 134 #define BCK1_BCKUP_MASK 0xFF 135 #define BCK1_BCKUP_SHIFT 0 136 137 138 /*Register BCK2 (0x80) register.RegisterDescription */ 139 #define BCK2_BCKUP_MASK 0xFF 140 #define BCK2_BCKUP_SHIFT 0 141 142 143 /*Register BCK3 (0x80) register.RegisterDescription */ 144 #define BCK3_BCKUP_MASK 0xFF 145 #define BCK3_BCKUP_SHIFT 0 146 147 148 /*Register BCK4 (0x80) register.RegisterDescription */ 149 #define BCK4_BCKUP_MASK 0xFF 150 #define BCK4_BCKUP_SHIFT 0 151 152 153 /*Register BCK5 (0x80) register.RegisterDescription */ 154 #define BCK5_BCKUP_MASK 0xFF 155 #define BCK5_BCKUP_SHIFT 0 156 157 158 /*Register PUADEN (0x80) register.RegisterDescription */ 159 #define PUADEN_EN3P_MASK 0x80 160 #define PUADEN_EN3P_SHIFT 7 161 #define PUADEN_I2CCTLP_MASK 0x40 162 #define PUADEN_I2CCTLP_SHIFT 6 163 #define PUADEN_I2CSRP_MASK 0x20 164 #define PUADEN_I2CSRP_SHIFT 5 165 #define PUADEN_PWRONP_MASK 0x10 166 #define PUADEN_PWRONP_SHIFT 4 167 #define PUADEN_SLEEPP_MASK 0x08 168 #define PUADEN_SLEEPP_SHIFT 3 169 #define PUADEN_PWRHOLDP_MASK 0x04 170 #define PUADEN_PWRHOLDP_SHIFT 2 171 #define PUADEN_BOOT1P_MASK 0x02 172 #define PUADEN_BOOT1P_SHIFT 1 173 #define PUADEN_BOOT0P_MASK 0x01 174 #define PUADEN_BOOT0P_SHIFT 0 175 176 177 /*Register REF (0x80) register.RegisterDescription */ 178 #define REF_VMBCH_SEL_MASK 0x0C 179 #define REF_VMBCH_SEL_SHIFT 2 180 #define REF_ST_MASK 0x03 181 #define REF_ST_SHIFT 0 182 183 184 /*Register VRTC (0x80) register.RegisterDescription */ 185 #define VRTC_VRTC_OFFMASK_MASK 0x08 186 #define VRTC_VRTC_OFFMASK_SHIFT 3 187 #define VRTC_ST_MASK 0x03 188 #define VRTC_ST_SHIFT 0 189 190 191 /*Register VIO (0x80) register.RegisterDescription */ 192 #define VIO_ILMAX_MASK 0xC0 193 #define VIO_ILMAX_SHIFT 6 194 #define VIO_SEL_MASK 0x0C 195 #define VIO_SEL_SHIFT 2 196 #define VIO_ST_MASK 0x03 197 #define VIO_ST_SHIFT 0 198 199 200 /*Register VDD1 (0x80) register.RegisterDescription */ 201 #define VDD1_VGAIN_SEL_MASK 0xC0 202 #define VDD1_VGAIN_SEL_SHIFT 6 203 #define VDD1_ILMAX_MASK 0x20 204 #define VDD1_ILMAX_SHIFT 5 205 #define VDD1_TSTEP_MASK 0x1C 206 #define VDD1_TSTEP_SHIFT 2 207 #define VDD1_ST_MASK 0x03 208 #define VDD1_ST_SHIFT 0 209 210 211 /*Register VDD1_OP (0x80) register.RegisterDescription */ 212 #define VDD1_OP_CMD_MASK 0x80 213 #define VDD1_OP_CMD_SHIFT 7 214 #define VDD1_OP_SEL_MASK 0x7F 215 #define VDD1_OP_SEL_SHIFT 0 216 217 218 /*Register VDD1_SR (0x80) register.RegisterDescription */ 219 #define VDD1_SR_SEL_MASK 0x7F 220 #define VDD1_SR_SEL_SHIFT 0 221 222 223 /*Register VDD2 (0x80) register.RegisterDescription */ 224 #define VDD2_VGAIN_SEL_MASK 0xC0 225 #define VDD2_VGAIN_SEL_SHIFT 6 226 #define VDD2_ILMAX_MASK 0x20 227 #define VDD2_ILMAX_SHIFT 5 228 #define VDD2_TSTEP_MASK 0x1C 229 #define VDD2_TSTEP_SHIFT 2 230 #define VDD2_ST_MASK 0x03 231 #define VDD2_ST_SHIFT 0 232 233 234 /*Register VDD2_OP (0x80) register.RegisterDescription */ 235 #define VDD2_OP_CMD_MASK 0x80 236 #define VDD2_OP_CMD_SHIFT 7 237 #define VDD2_OP_SEL_MASK 0x7F 238 #define VDD2_OP_SEL_SHIFT 0 239 240 /*Register VDD2_SR (0x80) register.RegisterDescription */ 241 #define VDD2_SR_SEL_MASK 0x7F 242 #define VDD2_SR_SEL_SHIFT 0 243 244 245 /*Registers VDD1, VDD2 voltage values definitions */ 246 #define VDD1_2_NUM_VOLTS 73 247 #define VDD1_2_MIN_VOLT 6000 248 #define VDD1_2_OFFSET 125 249 250 251 /*Register VDD3 (0x80) register.RegisterDescription */ 252 #define VDD3_CKINEN_MASK 0x04 253 #define VDD3_CKINEN_SHIFT 2 254 #define VDD3_ST_MASK 0x03 255 #define VDD3_ST_SHIFT 0 256 #define VDDCTRL_MIN_VOLT 6000 257 #define VDDCTRL_OFFSET 125 258 259 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */ 260 #define LDO_SEL_MASK 0x0C 261 #define LDO_SEL_SHIFT 2 262 #define LDO_ST_MASK 0x03 263 #define LDO_ST_SHIFT 0 264 #define LDO_ST_ON_BIT 0x01 265 #define LDO_ST_MODE_BIT 0x02 266 267 268 /* Registers LDO1 to LDO8 in tps65910 */ 269 #define LDO1_SEL_MASK 0xFC 270 #define LDO3_SEL_MASK 0x7C 271 #define LDO_MIN_VOLT 1000 272 #define LDO_MAX_VOLT 3300 273 274 275 /*Register VDIG1 (0x80) register.RegisterDescription */ 276 #define VDIG1_SEL_MASK 0x0C 277 #define VDIG1_SEL_SHIFT 2 278 #define VDIG1_ST_MASK 0x03 279 #define VDIG1_ST_SHIFT 0 280 281 282 /*Register VDIG2 (0x80) register.RegisterDescription */ 283 #define VDIG2_SEL_MASK 0x0C 284 #define VDIG2_SEL_SHIFT 2 285 #define VDIG2_ST_MASK 0x03 286 #define VDIG2_ST_SHIFT 0 287 288 289 /*Register VAUX1 (0x80) register.RegisterDescription */ 290 #define VAUX1_SEL_MASK 0x0C 291 #define VAUX1_SEL_SHIFT 2 292 #define VAUX1_ST_MASK 0x03 293 #define VAUX1_ST_SHIFT 0 294 295 296 /*Register VAUX2 (0x80) register.RegisterDescription */ 297 #define VAUX2_SEL_MASK 0x0C 298 #define VAUX2_SEL_SHIFT 2 299 #define VAUX2_ST_MASK 0x03 300 #define VAUX2_ST_SHIFT 0 301 302 303 /*Register VAUX33 (0x80) register.RegisterDescription */ 304 #define VAUX33_SEL_MASK 0x0C 305 #define VAUX33_SEL_SHIFT 2 306 #define VAUX33_ST_MASK 0x03 307 #define VAUX33_ST_SHIFT 0 308 309 310 /*Register VMMC (0x80) register.RegisterDescription */ 311 #define VMMC_SEL_MASK 0x0C 312 #define VMMC_SEL_SHIFT 2 313 #define VMMC_ST_MASK 0x03 314 #define VMMC_ST_SHIFT 0 315 316 317 /*Register VPLL (0x80) register.RegisterDescription */ 318 #define VPLL_SEL_MASK 0x0C 319 #define VPLL_SEL_SHIFT 2 320 #define VPLL_ST_MASK 0x03 321 #define VPLL_ST_SHIFT 0 322 323 324 /*Register VDAC (0x80) register.RegisterDescription */ 325 #define VDAC_SEL_MASK 0x0C 326 #define VDAC_SEL_SHIFT 2 327 #define VDAC_ST_MASK 0x03 328 #define VDAC_ST_SHIFT 0 329 330 331 /*Register THERM (0x80) register.RegisterDescription */ 332 #define THERM_THERM_HD_MASK 0x20 333 #define THERM_THERM_HD_SHIFT 5 334 #define THERM_THERM_TS_MASK 0x10 335 #define THERM_THERM_TS_SHIFT 4 336 #define THERM_THERM_HDSEL_MASK 0x0C 337 #define THERM_THERM_HDSEL_SHIFT 2 338 #define THERM_RSVD1_MASK 0x02 339 #define THERM_RSVD1_SHIFT 1 340 #define THERM_THERM_STATE_MASK 0x01 341 #define THERM_THERM_STATE_SHIFT 0 342 343 344 /*Register BBCH (0x80) register.RegisterDescription */ 345 #define BBCH_BBSEL_MASK 0x06 346 #define BBCH_BBSEL_SHIFT 1 347 #define BBCH_BBCHEN_MASK 0x01 348 #define BBCH_BBCHEN_SHIFT 0 349 350 351 /*Register DCDCCTRL (0x80) register.RegisterDescription */ 352 #define DCDCCTRL_VDD2_PSKIP_MASK 0x20 353 #define DCDCCTRL_VDD2_PSKIP_SHIFT 5 354 #define DCDCCTRL_VDD1_PSKIP_MASK 0x10 355 #define DCDCCTRL_VDD1_PSKIP_SHIFT 4 356 #define DCDCCTRL_VIO_PSKIP_MASK 0x08 357 #define DCDCCTRL_VIO_PSKIP_SHIFT 3 358 #define DCDCCTRL_DCDCCKEXT_MASK 0x04 359 #define DCDCCTRL_DCDCCKEXT_SHIFT 2 360 #define DCDCCTRL_DCDCCKSYNC_MASK 0x03 361 #define DCDCCTRL_DCDCCKSYNC_SHIFT 0 362 363 364 /*Register DEVCTRL (0x80) register.RegisterDescription */ 365 #define DEVCTRL_RTC_PWDN_MASK 0x40 366 #define DEVCTRL_RTC_PWDN_SHIFT 6 367 #define DEVCTRL_CK32K_CTRL_MASK 0x20 368 #define DEVCTRL_CK32K_CTRL_SHIFT 5 369 #define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10 370 #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4 371 #define DEVCTRL_DEV_OFF_RST_MASK 0x08 372 #define DEVCTRL_DEV_OFF_RST_SHIFT 3 373 #define DEVCTRL_DEV_ON_MASK 0x04 374 #define DEVCTRL_DEV_ON_SHIFT 2 375 #define DEVCTRL_DEV_SLP_MASK 0x02 376 #define DEVCTRL_DEV_SLP_SHIFT 1 377 #define DEVCTRL_DEV_OFF_MASK 0x01 378 #define DEVCTRL_DEV_OFF_SHIFT 0 379 380 381 /*Register DEVCTRL2 (0x80) register.RegisterDescription */ 382 #define DEVCTRL2_TSLOT_LENGTH_MASK 0x30 383 #define DEVCTRL2_TSLOT_LENGTH_SHIFT 4 384 #define DEVCTRL2_SLEEPSIG_POL_MASK 0x08 385 #define DEVCTRL2_SLEEPSIG_POL_SHIFT 3 386 #define DEVCTRL2_PWON_LP_OFF_MASK 0x04 387 #define DEVCTRL2_PWON_LP_OFF_SHIFT 2 388 #define DEVCTRL2_PWON_LP_RST_MASK 0x02 389 #define DEVCTRL2_PWON_LP_RST_SHIFT 1 390 #define DEVCTRL2_IT_POL_MASK 0x01 391 #define DEVCTRL2_IT_POL_SHIFT 0 392 393 394 /*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */ 395 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80 396 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7 397 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40 398 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6 399 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20 400 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5 401 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10 402 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4 403 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08 404 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3 405 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04 406 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2 407 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02 408 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1 409 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01 410 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0 411 412 413 /*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */ 414 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80 415 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7 416 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40 417 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6 418 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20 419 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5 420 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10 421 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4 422 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08 423 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3 424 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04 425 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2 426 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02 427 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1 428 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01 429 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0 430 431 432 /*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */ 433 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80 434 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7 435 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40 436 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6 437 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20 438 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5 439 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10 440 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4 441 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08 442 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3 443 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04 444 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2 445 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02 446 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1 447 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01 448 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0 449 450 451 /*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */ 452 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80 453 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7 454 #define SLEEP_SET_RES_OFF_RSVD_MASK 0x60 455 #define SLEEP_SET_RES_OFF_RSVD_SHIFT 5 456 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10 457 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4 458 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08 459 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3 460 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04 461 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2 462 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02 463 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1 464 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01 465 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0 466 467 468 /*Register EN1_LDO_ASS (0x80) register.RegisterDescription */ 469 #define EN1_LDO_ASS_VDAC_EN1_MASK 0x80 470 #define EN1_LDO_ASS_VDAC_EN1_SHIFT 7 471 #define EN1_LDO_ASS_VPLL_EN1_MASK 0x40 472 #define EN1_LDO_ASS_VPLL_EN1_SHIFT 6 473 #define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20 474 #define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5 475 #define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10 476 #define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4 477 #define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08 478 #define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3 479 #define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04 480 #define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2 481 #define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02 482 #define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1 483 #define EN1_LDO_ASS_VMMC_EN1_MASK 0x01 484 #define EN1_LDO_ASS_VMMC_EN1_SHIFT 0 485 486 487 /*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */ 488 #define EN1_SMPS_ASS_RSVD_MASK 0xE0 489 #define EN1_SMPS_ASS_RSVD_SHIFT 5 490 #define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10 491 #define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4 492 #define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08 493 #define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3 494 #define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04 495 #define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2 496 #define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02 497 #define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1 498 #define EN1_SMPS_ASS_VIO_EN1_MASK 0x01 499 #define EN1_SMPS_ASS_VIO_EN1_SHIFT 0 500 501 502 /*Register EN2_LDO_ASS (0x80) register.RegisterDescription */ 503 #define EN2_LDO_ASS_VDAC_EN2_MASK 0x80 504 #define EN2_LDO_ASS_VDAC_EN2_SHIFT 7 505 #define EN2_LDO_ASS_VPLL_EN2_MASK 0x40 506 #define EN2_LDO_ASS_VPLL_EN2_SHIFT 6 507 #define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20 508 #define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5 509 #define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10 510 #define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4 511 #define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08 512 #define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3 513 #define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04 514 #define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2 515 #define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02 516 #define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1 517 #define EN2_LDO_ASS_VMMC_EN2_MASK 0x01 518 #define EN2_LDO_ASS_VMMC_EN2_SHIFT 0 519 520 521 /*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */ 522 #define EN2_SMPS_ASS_RSVD_MASK 0xE0 523 #define EN2_SMPS_ASS_RSVD_SHIFT 5 524 #define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10 525 #define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4 526 #define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08 527 #define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3 528 #define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04 529 #define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2 530 #define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02 531 #define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1 532 #define EN2_SMPS_ASS_VIO_EN2_MASK 0x01 533 #define EN2_SMPS_ASS_VIO_EN2_SHIFT 0 534 535 536 /*Register EN3_LDO_ASS (0x80) register.RegisterDescription */ 537 #define EN3_LDO_ASS_VDAC_EN3_MASK 0x80 538 #define EN3_LDO_ASS_VDAC_EN3_SHIFT 7 539 #define EN3_LDO_ASS_VPLL_EN3_MASK 0x40 540 #define EN3_LDO_ASS_VPLL_EN3_SHIFT 6 541 #define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20 542 #define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5 543 #define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10 544 #define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4 545 #define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08 546 #define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3 547 #define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04 548 #define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2 549 #define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02 550 #define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1 551 #define EN3_LDO_ASS_VMMC_EN3_MASK 0x01 552 #define EN3_LDO_ASS_VMMC_EN3_SHIFT 0 553 554 555 /*Register SPARE (0x80) register.RegisterDescription */ 556 #define SPARE_SPARE_MASK 0xFF 557 #define SPARE_SPARE_SHIFT 0 558 559 560 /*Register INT_STS (0x80) register.RegisterDescription */ 561 #define INT_STS_RTC_PERIOD_IT_MASK 0x80 562 #define INT_STS_RTC_PERIOD_IT_SHIFT 7 563 #define INT_STS_RTC_ALARM_IT_MASK 0x40 564 #define INT_STS_RTC_ALARM_IT_SHIFT 6 565 #define INT_STS_HOTDIE_IT_MASK 0x20 566 #define INT_STS_HOTDIE_IT_SHIFT 5 567 #define INT_STS_PWRHOLD_IT_MASK 0x10 568 #define INT_STS_PWRHOLD_IT_SHIFT 4 569 #define INT_STS_PWRON_LP_IT_MASK 0x08 570 #define INT_STS_PWRON_LP_IT_SHIFT 3 571 #define INT_STS_PWRON_IT_MASK 0x04 572 #define INT_STS_PWRON_IT_SHIFT 2 573 #define INT_STS_VMBHI_IT_MASK 0x02 574 #define INT_STS_VMBHI_IT_SHIFT 1 575 #define INT_STS_VMBDCH_IT_MASK 0x01 576 #define INT_STS_VMBDCH_IT_SHIFT 0 577 578 579 /*Register INT_MSK (0x80) register.RegisterDescription */ 580 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80 581 #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7 582 #define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40 583 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6 584 #define INT_MSK_HOTDIE_IT_MSK_MASK 0x20 585 #define INT_MSK_HOTDIE_IT_MSK_SHIFT 5 586 #define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10 587 #define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4 588 #define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08 589 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3 590 #define INT_MSK_PWRON_IT_MSK_MASK 0x04 591 #define INT_MSK_PWRON_IT_MSK_SHIFT 2 592 #define INT_MSK_VMBHI_IT_MSK_MASK 0x02 593 #define INT_MSK_VMBHI_IT_MSK_SHIFT 1 594 #define INT_MSK_VMBDCH_IT_MSK_MASK 0x01 595 #define INT_MSK_VMBDCH_IT_MSK_SHIFT 0 596 597 598 /*Register INT_STS2 (0x80) register.RegisterDescription */ 599 #define INT_STS2_GPIO3_F_IT_MASK 0x80 600 #define INT_STS2_GPIO3_F_IT_SHIFT 7 601 #define INT_STS2_GPIO3_R_IT_MASK 0x40 602 #define INT_STS2_GPIO3_R_IT_SHIFT 6 603 #define INT_STS2_GPIO2_F_IT_MASK 0x20 604 #define INT_STS2_GPIO2_F_IT_SHIFT 5 605 #define INT_STS2_GPIO2_R_IT_MASK 0x10 606 #define INT_STS2_GPIO2_R_IT_SHIFT 4 607 #define INT_STS2_GPIO1_F_IT_MASK 0x08 608 #define INT_STS2_GPIO1_F_IT_SHIFT 3 609 #define INT_STS2_GPIO1_R_IT_MASK 0x04 610 #define INT_STS2_GPIO1_R_IT_SHIFT 2 611 #define INT_STS2_GPIO0_F_IT_MASK 0x02 612 #define INT_STS2_GPIO0_F_IT_SHIFT 1 613 #define INT_STS2_GPIO0_R_IT_MASK 0x01 614 #define INT_STS2_GPIO0_R_IT_SHIFT 0 615 616 617 /*Register INT_MSK2 (0x80) register.RegisterDescription */ 618 #define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80 619 #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7 620 #define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40 621 #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6 622 #define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20 623 #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5 624 #define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10 625 #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4 626 #define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08 627 #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3 628 #define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04 629 #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2 630 #define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02 631 #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1 632 #define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01 633 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0 634 635 636 /*Register INT_STS3 (0x80) register.RegisterDescription */ 637 #define INT_STS3_GPIO5_F_IT_MASK 0x08 638 #define INT_STS3_GPIO5_F_IT_SHIFT 3 639 #define INT_STS3_GPIO5_R_IT_MASK 0x04 640 #define INT_STS3_GPIO5_R_IT_SHIFT 2 641 #define INT_STS3_GPIO4_F_IT_MASK 0x02 642 #define INT_STS3_GPIO4_F_IT_SHIFT 1 643 #define INT_STS3_GPIO4_R_IT_MASK 0x01 644 #define INT_STS3_GPIO4_R_IT_SHIFT 0 645 646 647 /*Register INT_MSK3 (0x80) register.RegisterDescription */ 648 #define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08 649 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3 650 #define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04 651 #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2 652 #define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02 653 #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1 654 #define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01 655 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0 656 657 658 /*Register GPIO (0x80) register.RegisterDescription */ 659 #define GPIO_DEB_MASK 0x10 660 #define GPIO_DEB_SHIFT 4 661 #define GPIO_PUEN_MASK 0x08 662 #define GPIO_PUEN_SHIFT 3 663 #define GPIO_CFG_MASK 0x04 664 #define GPIO_CFG_SHIFT 2 665 #define GPIO_STS_MASK 0x02 666 #define GPIO_STS_SHIFT 1 667 #define GPIO_SET_MASK 0x01 668 #define GPIO_SET_SHIFT 0 669 670 671 /*Register JTAGVERNUM (0x80) register.RegisterDescription */ 672 #define JTAGVERNUM_VERNUM_MASK 0x0F 673 #define JTAGVERNUM_VERNUM_SHIFT 0 674 675 676 /* Register VDDCTRL (0x27) bit definitions */ 677 #define VDDCTRL_ST_MASK 0x03 678 #define VDDCTRL_ST_SHIFT 0 679 680 681 /*Register VDDCTRL_OP (0x28) bit definitios */ 682 #define VDDCTRL_OP_CMD_MASK 0x80 683 #define VDDCTRL_OP_CMD_SHIFT 7 684 #define VDDCTRL_OP_SEL_MASK 0x7F 685 #define VDDCTRL_OP_SEL_SHIFT 0 686 687 688 /*Register VDDCTRL_SR (0x29) bit definitions */ 689 #define VDDCTRL_SR_SEL_MASK 0x7F 690 #define VDDCTRL_SR_SEL_SHIFT 0 691 692 693 /* IRQ Definitions */ 694 #define TPS65910_IRQ_VBAT_VMBDCH 0 695 #define TPS65910_IRQ_VBAT_VMHI 1 696 #define TPS65910_IRQ_PWRON 2 697 #define TPS65910_IRQ_PWRON_LP 3 698 #define TPS65910_IRQ_PWRHOLD 4 699 #define TPS65910_IRQ_HOTDIE 5 700 #define TPS65910_IRQ_RTC_ALARM 6 701 #define TPS65910_IRQ_RTC_PERIOD 7 702 #define TPS65910_IRQ_GPIO_R 8 703 #define TPS65910_IRQ_GPIO_F 9 704 #define TPS65910_NUM_IRQ 10 705 706 #define TPS65911_IRQ_VBAT_VMBDCH 0 707 #define TPS65911_IRQ_VBAT_VMBDCH2L 1 708 #define TPS65911_IRQ_VBAT_VMBDCH2H 2 709 #define TPS65911_IRQ_VBAT_VMHI 3 710 #define TPS65911_IRQ_PWRON 4 711 #define TPS65911_IRQ_PWRON_LP 5 712 #define TPS65911_IRQ_PWRHOLD_F 6 713 #define TPS65911_IRQ_PWRHOLD_R 7 714 #define TPS65911_IRQ_HOTDIE 8 715 #define TPS65911_IRQ_RTC_ALARM 9 716 #define TPS65911_IRQ_RTC_PERIOD 10 717 #define TPS65911_IRQ_GPIO0_R 11 718 #define TPS65911_IRQ_GPIO0_F 12 719 #define TPS65911_IRQ_GPIO1_R 13 720 #define TPS65911_IRQ_GPIO1_F 14 721 #define TPS65911_IRQ_GPIO2_R 15 722 #define TPS65911_IRQ_GPIO2_F 16 723 #define TPS65911_IRQ_GPIO3_R 17 724 #define TPS65911_IRQ_GPIO3_F 18 725 #define TPS65911_IRQ_GPIO4_R 19 726 #define TPS65911_IRQ_GPIO4_F 20 727 #define TPS65911_IRQ_GPIO5_R 21 728 #define TPS65911_IRQ_GPIO5_F 22 729 #define TPS65911_IRQ_WTCHDG 23 730 #define TPS65911_IRQ_PWRDN 24 731 732 #define TPS65911_NUM_IRQ 25 733 734 735 /* GPIO Register Definitions */ 736 #define TPS65910_GPIO_DEB BIT(2) 737 #define TPS65910_GPIO_PUEN BIT(3) 738 #define TPS65910_GPIO_CFG BIT(2) 739 #define TPS65910_GPIO_STS BIT(1) 740 #define TPS65910_GPIO_SET BIT(0) 741 742 /** 743 * struct tps65910_board 744 * Board platform data may be used to initialize regulators. 745 */ 746 747 struct tps65910_board { 748 int gpio_base; 749 int irq; 750 int irq_base; 751 int vmbch_threshold; 752 int vmbch2_threshold; 753 struct regulator_init_data *tps65910_pmic_init_data; 754 }; 755 756 /** 757 * struct tps65910 - tps65910 sub-driver chip access routines 758 */ 759 760 struct tps65910 { 761 struct device *dev; 762 struct i2c_client *i2c_client; 763 struct mutex io_mutex; 764 unsigned int id; 765 int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest); 766 int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src); 767 768 /* Client devices */ 769 struct tps65910_pmic *pmic; 770 struct tps65910_rtc *rtc; 771 struct tps65910_power *power; 772 773 /* GPIO Handling */ 774 struct gpio_chip gpio; 775 776 /* IRQ Handling */ 777 struct mutex irq_lock; 778 int chip_irq; 779 int irq_base; 780 int irq_num; 781 u32 irq_mask; 782 }; 783 784 struct tps65910_platform_data { 785 int irq; 786 int irq_base; 787 }; 788 789 int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask); 790 int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask); 791 void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base); 792 int tps65910_irq_init(struct tps65910 *tps65910, int irq, 793 struct tps65910_platform_data *pdata); 794 int tps65910_irq_exit(struct tps65910 *tps65910); 795 796 static inline int tps65910_chip_id(struct tps65910 *tps65910) 797 { 798 return tps65910->id; 799 } 800 801 #endif /* __LINUX_MFD_TPS65910_H */ 802