1 /* 2 * tps65910.h -- TI TPS6591x 3 * 4 * Copyright 2010-2011 Texas Instruments Inc. 5 * 6 * Author: Graeme Gregory <[email protected]> 7 * Author: Jorge Eduardo Candelaria <[email protected]> 8 * Author: Arnaud Deconinck <[email protected]> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 17 #ifndef __LINUX_MFD_TPS65910_H 18 #define __LINUX_MFD_TPS65910_H 19 20 #include <linux/gpio.h> 21 #include <linux/regmap.h> 22 23 /* TPS chip id list */ 24 #define TPS65910 0 25 #define TPS65911 1 26 27 /* TPS regulator type list */ 28 #define REGULATOR_LDO 0 29 #define REGULATOR_DCDC 1 30 31 /* 32 * List of registers for component TPS65910 33 * 34 */ 35 36 #define TPS65910_SECONDS 0x0 37 #define TPS65910_MINUTES 0x1 38 #define TPS65910_HOURS 0x2 39 #define TPS65910_DAYS 0x3 40 #define TPS65910_MONTHS 0x4 41 #define TPS65910_YEARS 0x5 42 #define TPS65910_WEEKS 0x6 43 #define TPS65910_ALARM_SECONDS 0x8 44 #define TPS65910_ALARM_MINUTES 0x9 45 #define TPS65910_ALARM_HOURS 0xA 46 #define TPS65910_ALARM_DAYS 0xB 47 #define TPS65910_ALARM_MONTHS 0xC 48 #define TPS65910_ALARM_YEARS 0xD 49 #define TPS65910_RTC_CTRL 0x10 50 #define TPS65910_RTC_STATUS 0x11 51 #define TPS65910_RTC_INTERRUPTS 0x12 52 #define TPS65910_RTC_COMP_LSB 0x13 53 #define TPS65910_RTC_COMP_MSB 0x14 54 #define TPS65910_RTC_RES_PROG 0x15 55 #define TPS65910_RTC_RESET_STATUS 0x16 56 #define TPS65910_BCK1 0x17 57 #define TPS65910_BCK2 0x18 58 #define TPS65910_BCK3 0x19 59 #define TPS65910_BCK4 0x1A 60 #define TPS65910_BCK5 0x1B 61 #define TPS65910_PUADEN 0x1C 62 #define TPS65910_REF 0x1D 63 #define TPS65910_VRTC 0x1E 64 #define TPS65910_VIO 0x20 65 #define TPS65910_VDD1 0x21 66 #define TPS65910_VDD1_OP 0x22 67 #define TPS65910_VDD1_SR 0x23 68 #define TPS65910_VDD2 0x24 69 #define TPS65910_VDD2_OP 0x25 70 #define TPS65910_VDD2_SR 0x26 71 #define TPS65910_VDD3 0x27 72 #define TPS65910_VDIG1 0x30 73 #define TPS65910_VDIG2 0x31 74 #define TPS65910_VAUX1 0x32 75 #define TPS65910_VAUX2 0x33 76 #define TPS65910_VAUX33 0x34 77 #define TPS65910_VMMC 0x35 78 #define TPS65910_VPLL 0x36 79 #define TPS65910_VDAC 0x37 80 #define TPS65910_THERM 0x38 81 #define TPS65910_BBCH 0x39 82 #define TPS65910_DCDCCTRL 0x3E 83 #define TPS65910_DEVCTRL 0x3F 84 #define TPS65910_DEVCTRL2 0x40 85 #define TPS65910_SLEEP_KEEP_LDO_ON 0x41 86 #define TPS65910_SLEEP_KEEP_RES_ON 0x42 87 #define TPS65910_SLEEP_SET_LDO_OFF 0x43 88 #define TPS65910_SLEEP_SET_RES_OFF 0x44 89 #define TPS65910_EN1_LDO_ASS 0x45 90 #define TPS65910_EN1_SMPS_ASS 0x46 91 #define TPS65910_EN2_LDO_ASS 0x47 92 #define TPS65910_EN2_SMPS_ASS 0x48 93 #define TPS65910_EN3_LDO_ASS 0x49 94 #define TPS65910_SPARE 0x4A 95 #define TPS65910_INT_STS 0x50 96 #define TPS65910_INT_MSK 0x51 97 #define TPS65910_INT_STS2 0x52 98 #define TPS65910_INT_MSK2 0x53 99 #define TPS65910_INT_STS3 0x54 100 #define TPS65910_INT_MSK3 0x55 101 #define TPS65910_GPIO0 0x60 102 #define TPS65910_GPIO1 0x61 103 #define TPS65910_GPIO2 0x62 104 #define TPS65910_GPIO3 0x63 105 #define TPS65910_GPIO4 0x64 106 #define TPS65910_GPIO5 0x65 107 #define TPS65910_GPIO6 0x66 108 #define TPS65910_GPIO7 0x67 109 #define TPS65910_GPIO8 0x68 110 #define TPS65910_JTAGVERNUM 0x80 111 #define TPS65910_MAX_REGISTER 0x80 112 113 /* 114 * List of registers specific to TPS65911 115 */ 116 #define TPS65911_VDDCTRL 0x27 117 #define TPS65911_VDDCTRL_OP 0x28 118 #define TPS65911_VDDCTRL_SR 0x29 119 #define TPS65911_LDO1 0x30 120 #define TPS65911_LDO2 0x31 121 #define TPS65911_LDO5 0x32 122 #define TPS65911_LDO8 0x33 123 #define TPS65911_LDO7 0x34 124 #define TPS65911_LDO6 0x35 125 #define TPS65911_LDO4 0x36 126 #define TPS65911_LDO3 0x37 127 #define TPS65911_VMBCH 0x6A 128 #define TPS65911_VMBCH2 0x6B 129 130 /* 131 * List of register bitfields for component TPS65910 132 * 133 */ 134 135 136 /*Register BCK1 (0x80) register.RegisterDescription */ 137 #define BCK1_BCKUP_MASK 0xFF 138 #define BCK1_BCKUP_SHIFT 0 139 140 141 /*Register BCK2 (0x80) register.RegisterDescription */ 142 #define BCK2_BCKUP_MASK 0xFF 143 #define BCK2_BCKUP_SHIFT 0 144 145 146 /*Register BCK3 (0x80) register.RegisterDescription */ 147 #define BCK3_BCKUP_MASK 0xFF 148 #define BCK3_BCKUP_SHIFT 0 149 150 151 /*Register BCK4 (0x80) register.RegisterDescription */ 152 #define BCK4_BCKUP_MASK 0xFF 153 #define BCK4_BCKUP_SHIFT 0 154 155 156 /*Register BCK5 (0x80) register.RegisterDescription */ 157 #define BCK5_BCKUP_MASK 0xFF 158 #define BCK5_BCKUP_SHIFT 0 159 160 161 /*Register PUADEN (0x80) register.RegisterDescription */ 162 #define PUADEN_EN3P_MASK 0x80 163 #define PUADEN_EN3P_SHIFT 7 164 #define PUADEN_I2CCTLP_MASK 0x40 165 #define PUADEN_I2CCTLP_SHIFT 6 166 #define PUADEN_I2CSRP_MASK 0x20 167 #define PUADEN_I2CSRP_SHIFT 5 168 #define PUADEN_PWRONP_MASK 0x10 169 #define PUADEN_PWRONP_SHIFT 4 170 #define PUADEN_SLEEPP_MASK 0x08 171 #define PUADEN_SLEEPP_SHIFT 3 172 #define PUADEN_PWRHOLDP_MASK 0x04 173 #define PUADEN_PWRHOLDP_SHIFT 2 174 #define PUADEN_BOOT1P_MASK 0x02 175 #define PUADEN_BOOT1P_SHIFT 1 176 #define PUADEN_BOOT0P_MASK 0x01 177 #define PUADEN_BOOT0P_SHIFT 0 178 179 180 /*Register REF (0x80) register.RegisterDescription */ 181 #define REF_VMBCH_SEL_MASK 0x0C 182 #define REF_VMBCH_SEL_SHIFT 2 183 #define REF_ST_MASK 0x03 184 #define REF_ST_SHIFT 0 185 186 187 /*Register VRTC (0x80) register.RegisterDescription */ 188 #define VRTC_VRTC_OFFMASK_MASK 0x08 189 #define VRTC_VRTC_OFFMASK_SHIFT 3 190 #define VRTC_ST_MASK 0x03 191 #define VRTC_ST_SHIFT 0 192 193 194 /*Register VIO (0x80) register.RegisterDescription */ 195 #define VIO_ILMAX_MASK 0xC0 196 #define VIO_ILMAX_SHIFT 6 197 #define VIO_SEL_MASK 0x0C 198 #define VIO_SEL_SHIFT 2 199 #define VIO_ST_MASK 0x03 200 #define VIO_ST_SHIFT 0 201 202 203 /*Register VDD1 (0x80) register.RegisterDescription */ 204 #define VDD1_VGAIN_SEL_MASK 0xC0 205 #define VDD1_VGAIN_SEL_SHIFT 6 206 #define VDD1_ILMAX_MASK 0x20 207 #define VDD1_ILMAX_SHIFT 5 208 #define VDD1_TSTEP_MASK 0x1C 209 #define VDD1_TSTEP_SHIFT 2 210 #define VDD1_ST_MASK 0x03 211 #define VDD1_ST_SHIFT 0 212 213 214 /*Register VDD1_OP (0x80) register.RegisterDescription */ 215 #define VDD1_OP_CMD_MASK 0x80 216 #define VDD1_OP_CMD_SHIFT 7 217 #define VDD1_OP_SEL_MASK 0x7F 218 #define VDD1_OP_SEL_SHIFT 0 219 220 221 /*Register VDD1_SR (0x80) register.RegisterDescription */ 222 #define VDD1_SR_SEL_MASK 0x7F 223 #define VDD1_SR_SEL_SHIFT 0 224 225 226 /*Register VDD2 (0x80) register.RegisterDescription */ 227 #define VDD2_VGAIN_SEL_MASK 0xC0 228 #define VDD2_VGAIN_SEL_SHIFT 6 229 #define VDD2_ILMAX_MASK 0x20 230 #define VDD2_ILMAX_SHIFT 5 231 #define VDD2_TSTEP_MASK 0x1C 232 #define VDD2_TSTEP_SHIFT 2 233 #define VDD2_ST_MASK 0x03 234 #define VDD2_ST_SHIFT 0 235 236 237 /*Register VDD2_OP (0x80) register.RegisterDescription */ 238 #define VDD2_OP_CMD_MASK 0x80 239 #define VDD2_OP_CMD_SHIFT 7 240 #define VDD2_OP_SEL_MASK 0x7F 241 #define VDD2_OP_SEL_SHIFT 0 242 243 /*Register VDD2_SR (0x80) register.RegisterDescription */ 244 #define VDD2_SR_SEL_MASK 0x7F 245 #define VDD2_SR_SEL_SHIFT 0 246 247 248 /*Registers VDD1, VDD2 voltage values definitions */ 249 #define VDD1_2_NUM_VOLT_FINE 73 250 #define VDD1_2_NUM_VOLT_COARSE 3 251 #define VDD1_2_MIN_VOLT 6000 252 #define VDD1_2_OFFSET 125 253 254 255 /*Register VDD3 (0x80) register.RegisterDescription */ 256 #define VDD3_CKINEN_MASK 0x04 257 #define VDD3_CKINEN_SHIFT 2 258 #define VDD3_ST_MASK 0x03 259 #define VDD3_ST_SHIFT 0 260 #define VDDCTRL_MIN_VOLT 6000 261 #define VDDCTRL_OFFSET 125 262 263 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */ 264 #define LDO_SEL_MASK 0x0C 265 #define LDO_SEL_SHIFT 2 266 #define LDO_ST_MASK 0x03 267 #define LDO_ST_SHIFT 0 268 #define LDO_ST_ON_BIT 0x01 269 #define LDO_ST_MODE_BIT 0x02 270 271 272 /* Registers LDO1 to LDO8 in tps65910 */ 273 #define LDO1_SEL_MASK 0xFC 274 #define LDO3_SEL_MASK 0x7C 275 #define LDO_MIN_VOLT 1000 276 #define LDO_MAX_VOLT 3300 277 278 279 /*Register VDIG1 (0x80) register.RegisterDescription */ 280 #define VDIG1_SEL_MASK 0x0C 281 #define VDIG1_SEL_SHIFT 2 282 #define VDIG1_ST_MASK 0x03 283 #define VDIG1_ST_SHIFT 0 284 285 286 /*Register VDIG2 (0x80) register.RegisterDescription */ 287 #define VDIG2_SEL_MASK 0x0C 288 #define VDIG2_SEL_SHIFT 2 289 #define VDIG2_ST_MASK 0x03 290 #define VDIG2_ST_SHIFT 0 291 292 293 /*Register VAUX1 (0x80) register.RegisterDescription */ 294 #define VAUX1_SEL_MASK 0x0C 295 #define VAUX1_SEL_SHIFT 2 296 #define VAUX1_ST_MASK 0x03 297 #define VAUX1_ST_SHIFT 0 298 299 300 /*Register VAUX2 (0x80) register.RegisterDescription */ 301 #define VAUX2_SEL_MASK 0x0C 302 #define VAUX2_SEL_SHIFT 2 303 #define VAUX2_ST_MASK 0x03 304 #define VAUX2_ST_SHIFT 0 305 306 307 /*Register VAUX33 (0x80) register.RegisterDescription */ 308 #define VAUX33_SEL_MASK 0x0C 309 #define VAUX33_SEL_SHIFT 2 310 #define VAUX33_ST_MASK 0x03 311 #define VAUX33_ST_SHIFT 0 312 313 314 /*Register VMMC (0x80) register.RegisterDescription */ 315 #define VMMC_SEL_MASK 0x0C 316 #define VMMC_SEL_SHIFT 2 317 #define VMMC_ST_MASK 0x03 318 #define VMMC_ST_SHIFT 0 319 320 321 /*Register VPLL (0x80) register.RegisterDescription */ 322 #define VPLL_SEL_MASK 0x0C 323 #define VPLL_SEL_SHIFT 2 324 #define VPLL_ST_MASK 0x03 325 #define VPLL_ST_SHIFT 0 326 327 328 /*Register VDAC (0x80) register.RegisterDescription */ 329 #define VDAC_SEL_MASK 0x0C 330 #define VDAC_SEL_SHIFT 2 331 #define VDAC_ST_MASK 0x03 332 #define VDAC_ST_SHIFT 0 333 334 335 /*Register THERM (0x80) register.RegisterDescription */ 336 #define THERM_THERM_HD_MASK 0x20 337 #define THERM_THERM_HD_SHIFT 5 338 #define THERM_THERM_TS_MASK 0x10 339 #define THERM_THERM_TS_SHIFT 4 340 #define THERM_THERM_HDSEL_MASK 0x0C 341 #define THERM_THERM_HDSEL_SHIFT 2 342 #define THERM_RSVD1_MASK 0x02 343 #define THERM_RSVD1_SHIFT 1 344 #define THERM_THERM_STATE_MASK 0x01 345 #define THERM_THERM_STATE_SHIFT 0 346 347 348 /*Register BBCH (0x80) register.RegisterDescription */ 349 #define BBCH_BBSEL_MASK 0x06 350 #define BBCH_BBSEL_SHIFT 1 351 #define BBCH_BBCHEN_MASK 0x01 352 #define BBCH_BBCHEN_SHIFT 0 353 354 355 /*Register DCDCCTRL (0x80) register.RegisterDescription */ 356 #define DCDCCTRL_VDD2_PSKIP_MASK 0x20 357 #define DCDCCTRL_VDD2_PSKIP_SHIFT 5 358 #define DCDCCTRL_VDD1_PSKIP_MASK 0x10 359 #define DCDCCTRL_VDD1_PSKIP_SHIFT 4 360 #define DCDCCTRL_VIO_PSKIP_MASK 0x08 361 #define DCDCCTRL_VIO_PSKIP_SHIFT 3 362 #define DCDCCTRL_DCDCCKEXT_MASK 0x04 363 #define DCDCCTRL_DCDCCKEXT_SHIFT 2 364 #define DCDCCTRL_DCDCCKSYNC_MASK 0x03 365 #define DCDCCTRL_DCDCCKSYNC_SHIFT 0 366 367 368 /*Register DEVCTRL (0x80) register.RegisterDescription */ 369 #define DEVCTRL_PWR_OFF_MASK 0x80 370 #define DEVCTRL_PWR_OFF_SHIFT 7 371 #define DEVCTRL_RTC_PWDN_MASK 0x40 372 #define DEVCTRL_RTC_PWDN_SHIFT 6 373 #define DEVCTRL_CK32K_CTRL_MASK 0x20 374 #define DEVCTRL_CK32K_CTRL_SHIFT 5 375 #define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10 376 #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4 377 #define DEVCTRL_DEV_OFF_RST_MASK 0x08 378 #define DEVCTRL_DEV_OFF_RST_SHIFT 3 379 #define DEVCTRL_DEV_ON_MASK 0x04 380 #define DEVCTRL_DEV_ON_SHIFT 2 381 #define DEVCTRL_DEV_SLP_MASK 0x02 382 #define DEVCTRL_DEV_SLP_SHIFT 1 383 #define DEVCTRL_DEV_OFF_MASK 0x01 384 #define DEVCTRL_DEV_OFF_SHIFT 0 385 386 387 /*Register DEVCTRL2 (0x80) register.RegisterDescription */ 388 #define DEVCTRL2_TSLOT_LENGTH_MASK 0x30 389 #define DEVCTRL2_TSLOT_LENGTH_SHIFT 4 390 #define DEVCTRL2_SLEEPSIG_POL_MASK 0x08 391 #define DEVCTRL2_SLEEPSIG_POL_SHIFT 3 392 #define DEVCTRL2_PWON_LP_OFF_MASK 0x04 393 #define DEVCTRL2_PWON_LP_OFF_SHIFT 2 394 #define DEVCTRL2_PWON_LP_RST_MASK 0x02 395 #define DEVCTRL2_PWON_LP_RST_SHIFT 1 396 #define DEVCTRL2_IT_POL_MASK 0x01 397 #define DEVCTRL2_IT_POL_SHIFT 0 398 399 400 /*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */ 401 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80 402 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7 403 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40 404 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6 405 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20 406 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5 407 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10 408 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4 409 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08 410 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3 411 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04 412 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2 413 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02 414 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1 415 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01 416 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0 417 418 419 /*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */ 420 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80 421 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7 422 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40 423 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6 424 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20 425 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5 426 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10 427 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4 428 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08 429 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3 430 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04 431 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2 432 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02 433 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1 434 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01 435 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0 436 437 438 /*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */ 439 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80 440 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7 441 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40 442 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6 443 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20 444 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5 445 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10 446 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4 447 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08 448 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3 449 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04 450 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2 451 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02 452 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1 453 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01 454 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0 455 456 457 /*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */ 458 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80 459 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7 460 #define SLEEP_SET_RES_OFF_RSVD_MASK 0x60 461 #define SLEEP_SET_RES_OFF_RSVD_SHIFT 5 462 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10 463 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4 464 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08 465 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3 466 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04 467 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2 468 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02 469 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1 470 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01 471 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0 472 473 474 /*Register EN1_LDO_ASS (0x80) register.RegisterDescription */ 475 #define EN1_LDO_ASS_VDAC_EN1_MASK 0x80 476 #define EN1_LDO_ASS_VDAC_EN1_SHIFT 7 477 #define EN1_LDO_ASS_VPLL_EN1_MASK 0x40 478 #define EN1_LDO_ASS_VPLL_EN1_SHIFT 6 479 #define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20 480 #define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5 481 #define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10 482 #define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4 483 #define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08 484 #define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3 485 #define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04 486 #define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2 487 #define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02 488 #define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1 489 #define EN1_LDO_ASS_VMMC_EN1_MASK 0x01 490 #define EN1_LDO_ASS_VMMC_EN1_SHIFT 0 491 492 493 /*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */ 494 #define EN1_SMPS_ASS_RSVD_MASK 0xE0 495 #define EN1_SMPS_ASS_RSVD_SHIFT 5 496 #define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10 497 #define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4 498 #define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08 499 #define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3 500 #define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04 501 #define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2 502 #define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02 503 #define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1 504 #define EN1_SMPS_ASS_VIO_EN1_MASK 0x01 505 #define EN1_SMPS_ASS_VIO_EN1_SHIFT 0 506 507 508 /*Register EN2_LDO_ASS (0x80) register.RegisterDescription */ 509 #define EN2_LDO_ASS_VDAC_EN2_MASK 0x80 510 #define EN2_LDO_ASS_VDAC_EN2_SHIFT 7 511 #define EN2_LDO_ASS_VPLL_EN2_MASK 0x40 512 #define EN2_LDO_ASS_VPLL_EN2_SHIFT 6 513 #define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20 514 #define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5 515 #define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10 516 #define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4 517 #define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08 518 #define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3 519 #define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04 520 #define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2 521 #define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02 522 #define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1 523 #define EN2_LDO_ASS_VMMC_EN2_MASK 0x01 524 #define EN2_LDO_ASS_VMMC_EN2_SHIFT 0 525 526 527 /*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */ 528 #define EN2_SMPS_ASS_RSVD_MASK 0xE0 529 #define EN2_SMPS_ASS_RSVD_SHIFT 5 530 #define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10 531 #define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4 532 #define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08 533 #define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3 534 #define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04 535 #define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2 536 #define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02 537 #define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1 538 #define EN2_SMPS_ASS_VIO_EN2_MASK 0x01 539 #define EN2_SMPS_ASS_VIO_EN2_SHIFT 0 540 541 542 /*Register EN3_LDO_ASS (0x80) register.RegisterDescription */ 543 #define EN3_LDO_ASS_VDAC_EN3_MASK 0x80 544 #define EN3_LDO_ASS_VDAC_EN3_SHIFT 7 545 #define EN3_LDO_ASS_VPLL_EN3_MASK 0x40 546 #define EN3_LDO_ASS_VPLL_EN3_SHIFT 6 547 #define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20 548 #define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5 549 #define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10 550 #define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4 551 #define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08 552 #define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3 553 #define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04 554 #define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2 555 #define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02 556 #define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1 557 #define EN3_LDO_ASS_VMMC_EN3_MASK 0x01 558 #define EN3_LDO_ASS_VMMC_EN3_SHIFT 0 559 560 561 /*Register SPARE (0x80) register.RegisterDescription */ 562 #define SPARE_SPARE_MASK 0xFF 563 #define SPARE_SPARE_SHIFT 0 564 565 566 /*Register INT_STS (0x80) register.RegisterDescription */ 567 #define INT_STS_RTC_PERIOD_IT_MASK 0x80 568 #define INT_STS_RTC_PERIOD_IT_SHIFT 7 569 #define INT_STS_RTC_ALARM_IT_MASK 0x40 570 #define INT_STS_RTC_ALARM_IT_SHIFT 6 571 #define INT_STS_HOTDIE_IT_MASK 0x20 572 #define INT_STS_HOTDIE_IT_SHIFT 5 573 #define INT_STS_PWRHOLD_IT_MASK 0x10 574 #define INT_STS_PWRHOLD_IT_SHIFT 4 575 #define INT_STS_PWRON_LP_IT_MASK 0x08 576 #define INT_STS_PWRON_LP_IT_SHIFT 3 577 #define INT_STS_PWRON_IT_MASK 0x04 578 #define INT_STS_PWRON_IT_SHIFT 2 579 #define INT_STS_VMBHI_IT_MASK 0x02 580 #define INT_STS_VMBHI_IT_SHIFT 1 581 #define INT_STS_VMBDCH_IT_MASK 0x01 582 #define INT_STS_VMBDCH_IT_SHIFT 0 583 584 585 /*Register INT_MSK (0x80) register.RegisterDescription */ 586 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80 587 #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7 588 #define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40 589 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6 590 #define INT_MSK_HOTDIE_IT_MSK_MASK 0x20 591 #define INT_MSK_HOTDIE_IT_MSK_SHIFT 5 592 #define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10 593 #define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4 594 #define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08 595 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3 596 #define INT_MSK_PWRON_IT_MSK_MASK 0x04 597 #define INT_MSK_PWRON_IT_MSK_SHIFT 2 598 #define INT_MSK_VMBHI_IT_MSK_MASK 0x02 599 #define INT_MSK_VMBHI_IT_MSK_SHIFT 1 600 #define INT_MSK_VMBDCH_IT_MSK_MASK 0x01 601 #define INT_MSK_VMBDCH_IT_MSK_SHIFT 0 602 603 604 /*Register INT_STS2 (0x80) register.RegisterDescription */ 605 #define INT_STS2_GPIO3_F_IT_MASK 0x80 606 #define INT_STS2_GPIO3_F_IT_SHIFT 7 607 #define INT_STS2_GPIO3_R_IT_MASK 0x40 608 #define INT_STS2_GPIO3_R_IT_SHIFT 6 609 #define INT_STS2_GPIO2_F_IT_MASK 0x20 610 #define INT_STS2_GPIO2_F_IT_SHIFT 5 611 #define INT_STS2_GPIO2_R_IT_MASK 0x10 612 #define INT_STS2_GPIO2_R_IT_SHIFT 4 613 #define INT_STS2_GPIO1_F_IT_MASK 0x08 614 #define INT_STS2_GPIO1_F_IT_SHIFT 3 615 #define INT_STS2_GPIO1_R_IT_MASK 0x04 616 #define INT_STS2_GPIO1_R_IT_SHIFT 2 617 #define INT_STS2_GPIO0_F_IT_MASK 0x02 618 #define INT_STS2_GPIO0_F_IT_SHIFT 1 619 #define INT_STS2_GPIO0_R_IT_MASK 0x01 620 #define INT_STS2_GPIO0_R_IT_SHIFT 0 621 622 623 /*Register INT_MSK2 (0x80) register.RegisterDescription */ 624 #define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80 625 #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7 626 #define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40 627 #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6 628 #define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20 629 #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5 630 #define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10 631 #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4 632 #define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08 633 #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3 634 #define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04 635 #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2 636 #define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02 637 #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1 638 #define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01 639 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0 640 641 642 /*Register INT_STS3 (0x80) register.RegisterDescription */ 643 #define INT_STS3_GPIO5_F_IT_MASK 0x08 644 #define INT_STS3_GPIO5_F_IT_SHIFT 3 645 #define INT_STS3_GPIO5_R_IT_MASK 0x04 646 #define INT_STS3_GPIO5_R_IT_SHIFT 2 647 #define INT_STS3_GPIO4_F_IT_MASK 0x02 648 #define INT_STS3_GPIO4_F_IT_SHIFT 1 649 #define INT_STS3_GPIO4_R_IT_MASK 0x01 650 #define INT_STS3_GPIO4_R_IT_SHIFT 0 651 652 653 /*Register INT_MSK3 (0x80) register.RegisterDescription */ 654 #define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08 655 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3 656 #define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04 657 #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2 658 #define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02 659 #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1 660 #define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01 661 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0 662 663 664 /*Register GPIO (0x80) register.RegisterDescription */ 665 #define GPIO_SLEEP_MASK 0x80 666 #define GPIO_SLEEP_SHIFT 7 667 #define GPIO_DEB_MASK 0x10 668 #define GPIO_DEB_SHIFT 4 669 #define GPIO_PUEN_MASK 0x08 670 #define GPIO_PUEN_SHIFT 3 671 #define GPIO_CFG_MASK 0x04 672 #define GPIO_CFG_SHIFT 2 673 #define GPIO_STS_MASK 0x02 674 #define GPIO_STS_SHIFT 1 675 #define GPIO_SET_MASK 0x01 676 #define GPIO_SET_SHIFT 0 677 678 679 /*Register JTAGVERNUM (0x80) register.RegisterDescription */ 680 #define JTAGVERNUM_VERNUM_MASK 0x0F 681 #define JTAGVERNUM_VERNUM_SHIFT 0 682 683 684 /* Register VDDCTRL (0x27) bit definitions */ 685 #define VDDCTRL_ST_MASK 0x03 686 #define VDDCTRL_ST_SHIFT 0 687 688 689 /*Register VDDCTRL_OP (0x28) bit definitios */ 690 #define VDDCTRL_OP_CMD_MASK 0x80 691 #define VDDCTRL_OP_CMD_SHIFT 7 692 #define VDDCTRL_OP_SEL_MASK 0x7F 693 #define VDDCTRL_OP_SEL_SHIFT 0 694 695 696 /*Register VDDCTRL_SR (0x29) bit definitions */ 697 #define VDDCTRL_SR_SEL_MASK 0x7F 698 #define VDDCTRL_SR_SEL_SHIFT 0 699 700 701 /* IRQ Definitions */ 702 #define TPS65910_IRQ_VBAT_VMBDCH 0 703 #define TPS65910_IRQ_VBAT_VMHI 1 704 #define TPS65910_IRQ_PWRON 2 705 #define TPS65910_IRQ_PWRON_LP 3 706 #define TPS65910_IRQ_PWRHOLD 4 707 #define TPS65910_IRQ_HOTDIE 5 708 #define TPS65910_IRQ_RTC_ALARM 6 709 #define TPS65910_IRQ_RTC_PERIOD 7 710 #define TPS65910_IRQ_GPIO_R 8 711 #define TPS65910_IRQ_GPIO_F 9 712 #define TPS65910_NUM_IRQ 10 713 714 #define TPS65911_IRQ_VBAT_VMBDCH 0 715 #define TPS65911_IRQ_VBAT_VMBDCH2L 1 716 #define TPS65911_IRQ_VBAT_VMBDCH2H 2 717 #define TPS65911_IRQ_VBAT_VMHI 3 718 #define TPS65911_IRQ_PWRON 4 719 #define TPS65911_IRQ_PWRON_LP 5 720 #define TPS65911_IRQ_PWRHOLD_F 6 721 #define TPS65911_IRQ_PWRHOLD_R 7 722 #define TPS65911_IRQ_HOTDIE 8 723 #define TPS65911_IRQ_RTC_ALARM 9 724 #define TPS65911_IRQ_RTC_PERIOD 10 725 #define TPS65911_IRQ_GPIO0_R 11 726 #define TPS65911_IRQ_GPIO0_F 12 727 #define TPS65911_IRQ_GPIO1_R 13 728 #define TPS65911_IRQ_GPIO1_F 14 729 #define TPS65911_IRQ_GPIO2_R 15 730 #define TPS65911_IRQ_GPIO2_F 16 731 #define TPS65911_IRQ_GPIO3_R 17 732 #define TPS65911_IRQ_GPIO3_F 18 733 #define TPS65911_IRQ_GPIO4_R 19 734 #define TPS65911_IRQ_GPIO4_F 20 735 #define TPS65911_IRQ_GPIO5_R 21 736 #define TPS65911_IRQ_GPIO5_F 22 737 #define TPS65911_IRQ_WTCHDG 23 738 #define TPS65911_IRQ_PWRDN 24 739 740 #define TPS65911_NUM_IRQ 25 741 742 743 /* GPIO Register Definitions */ 744 #define TPS65910_GPIO_DEB BIT(2) 745 #define TPS65910_GPIO_PUEN BIT(3) 746 #define TPS65910_GPIO_CFG BIT(2) 747 #define TPS65910_GPIO_STS BIT(1) 748 #define TPS65910_GPIO_SET BIT(0) 749 750 /* Max number of TPS65910/11 GPIOs */ 751 #define TPS65910_NUM_GPIO 6 752 #define TPS65911_NUM_GPIO 9 753 #define TPS6591X_MAX_NUM_GPIO 9 754 755 /* Regulator Index Definitions */ 756 #define TPS65910_REG_VRTC 0 757 #define TPS65910_REG_VIO 1 758 #define TPS65910_REG_VDD1 2 759 #define TPS65910_REG_VDD2 3 760 #define TPS65910_REG_VDD3 4 761 #define TPS65910_REG_VDIG1 5 762 #define TPS65910_REG_VDIG2 6 763 #define TPS65910_REG_VPLL 7 764 #define TPS65910_REG_VDAC 8 765 #define TPS65910_REG_VAUX1 9 766 #define TPS65910_REG_VAUX2 10 767 #define TPS65910_REG_VAUX33 11 768 #define TPS65910_REG_VMMC 12 769 770 #define TPS65911_REG_VDDCTRL 4 771 #define TPS65911_REG_LDO1 5 772 #define TPS65911_REG_LDO2 6 773 #define TPS65911_REG_LDO3 7 774 #define TPS65911_REG_LDO4 8 775 #define TPS65911_REG_LDO5 9 776 #define TPS65911_REG_LDO6 10 777 #define TPS65911_REG_LDO7 11 778 #define TPS65911_REG_LDO8 12 779 780 /* Max number of TPS65910/11 regulators */ 781 #define TPS65910_NUM_REGS 13 782 783 /* External sleep controls through EN1/EN2/EN3/SLEEP inputs */ 784 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 0x1 785 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 0x2 786 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 0x4 787 #define TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP 0x8 788 789 /* 790 * Sleep keepon data: Maintains the state in sleep mode 791 * @therm_keepon: Keep on the thermal monitoring in sleep state. 792 * @clkout32k_keepon: Keep on the 32KHz clock output in sleep state. 793 * @i2chs_keepon: Keep on high speed internal clock in sleep state. 794 */ 795 struct tps65910_sleep_keepon_data { 796 unsigned therm_keepon:1; 797 unsigned clkout32k_keepon:1; 798 unsigned i2chs_keepon:1; 799 }; 800 801 /** 802 * struct tps65910_board 803 * Board platform data may be used to initialize regulators. 804 */ 805 806 struct tps65910_board { 807 int gpio_base; 808 int irq; 809 int irq_base; 810 int vmbch_threshold; 811 int vmbch2_threshold; 812 bool en_ck32k_xtal; 813 bool en_dev_slp; 814 bool pm_off; 815 struct tps65910_sleep_keepon_data *slp_keepon; 816 bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO]; 817 unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS]; 818 struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS]; 819 }; 820 821 /** 822 * struct tps65910 - tps65910 sub-driver chip access routines 823 */ 824 825 struct tps65910 { 826 struct device *dev; 827 struct i2c_client *i2c_client; 828 struct regmap *regmap; 829 struct mutex io_mutex; 830 unsigned int id; 831 832 /* Client devices */ 833 struct tps65910_pmic *pmic; 834 struct tps65910_rtc *rtc; 835 struct tps65910_power *power; 836 837 /* Device node parsed board data */ 838 struct tps65910_board *of_plat_data; 839 840 /* IRQ Handling */ 841 struct mutex irq_lock; 842 int chip_irq; 843 int irq_base; 844 int irq_num; 845 u32 irq_mask; 846 struct irq_domain *domain; 847 }; 848 849 struct tps65910_platform_data { 850 int irq; 851 int irq_base; 852 }; 853 854 int tps65910_irq_init(struct tps65910 *tps65910, int irq, 855 struct tps65910_platform_data *pdata); 856 int tps65910_irq_exit(struct tps65910 *tps65910); 857 858 static inline int tps65910_chip_id(struct tps65910 *tps65910) 859 { 860 return tps65910->id; 861 } 862 863 static inline int tps65910_reg_read(struct tps65910 *tps65910, u8 reg, 864 unsigned int *val) 865 { 866 return regmap_read(tps65910->regmap, reg, val); 867 } 868 869 static inline int tps65910_reg_write(struct tps65910 *tps65910, u8 reg, 870 unsigned int val) 871 { 872 return regmap_write(tps65910->regmap, reg, val); 873 } 874 875 static inline int tps65910_reg_set_bits(struct tps65910 *tps65910, u8 reg, 876 u8 mask) 877 { 878 return regmap_update_bits(tps65910->regmap, reg, mask, mask); 879 } 880 881 static inline int tps65910_reg_clear_bits(struct tps65910 *tps65910, u8 reg, 882 u8 mask) 883 { 884 return regmap_update_bits(tps65910->regmap, reg, mask, 0); 885 } 886 887 static inline int tps65910_reg_update_bits(struct tps65910 *tps65910, u8 reg, 888 u8 mask, u8 val) 889 { 890 return regmap_update_bits(tps65910->regmap, reg, mask, val); 891 } 892 893 #endif /* __LINUX_MFD_TPS65910_H */ 894