1 /* 2 * tps65910.h -- TI TPS6591x 3 * 4 * Copyright 2010-2011 Texas Instruments Inc. 5 * 6 * Author: Graeme Gregory <[email protected]> 7 * Author: Jorge Eduardo Candelaria <[email protected]> 8 * Author: Arnaud Deconinck <[email protected]> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 17 #ifndef __LINUX_MFD_TPS65910_H 18 #define __LINUX_MFD_TPS65910_H 19 20 #include <linux/gpio.h> 21 #include <linux/regmap.h> 22 23 /* TPS chip id list */ 24 #define TPS65910 0 25 #define TPS65911 1 26 27 /* TPS regulator type list */ 28 #define REGULATOR_LDO 0 29 #define REGULATOR_DCDC 1 30 31 /* 32 * List of registers for component TPS65910 33 * 34 */ 35 36 #define TPS65910_SECONDS 0x0 37 #define TPS65910_MINUTES 0x1 38 #define TPS65910_HOURS 0x2 39 #define TPS65910_DAYS 0x3 40 #define TPS65910_MONTHS 0x4 41 #define TPS65910_YEARS 0x5 42 #define TPS65910_WEEKS 0x6 43 #define TPS65910_ALARM_SECONDS 0x8 44 #define TPS65910_ALARM_MINUTES 0x9 45 #define TPS65910_ALARM_HOURS 0xA 46 #define TPS65910_ALARM_DAYS 0xB 47 #define TPS65910_ALARM_MONTHS 0xC 48 #define TPS65910_ALARM_YEARS 0xD 49 #define TPS65910_RTC_CTRL 0x10 50 #define TPS65910_RTC_STATUS 0x11 51 #define TPS65910_RTC_INTERRUPTS 0x12 52 #define TPS65910_RTC_COMP_LSB 0x13 53 #define TPS65910_RTC_COMP_MSB 0x14 54 #define TPS65910_RTC_RES_PROG 0x15 55 #define TPS65910_RTC_RESET_STATUS 0x16 56 #define TPS65910_BCK1 0x17 57 #define TPS65910_BCK2 0x18 58 #define TPS65910_BCK3 0x19 59 #define TPS65910_BCK4 0x1A 60 #define TPS65910_BCK5 0x1B 61 #define TPS65910_PUADEN 0x1C 62 #define TPS65910_REF 0x1D 63 #define TPS65910_VRTC 0x1E 64 #define TPS65910_VIO 0x20 65 #define TPS65910_VDD1 0x21 66 #define TPS65910_VDD1_OP 0x22 67 #define TPS65910_VDD1_SR 0x23 68 #define TPS65910_VDD2 0x24 69 #define TPS65910_VDD2_OP 0x25 70 #define TPS65910_VDD2_SR 0x26 71 #define TPS65910_VDD3 0x27 72 #define TPS65910_VDIG1 0x30 73 #define TPS65910_VDIG2 0x31 74 #define TPS65910_VAUX1 0x32 75 #define TPS65910_VAUX2 0x33 76 #define TPS65910_VAUX33 0x34 77 #define TPS65910_VMMC 0x35 78 #define TPS65910_VPLL 0x36 79 #define TPS65910_VDAC 0x37 80 #define TPS65910_THERM 0x38 81 #define TPS65910_BBCH 0x39 82 #define TPS65910_DCDCCTRL 0x3E 83 #define TPS65910_DEVCTRL 0x3F 84 #define TPS65910_DEVCTRL2 0x40 85 #define TPS65910_SLEEP_KEEP_LDO_ON 0x41 86 #define TPS65910_SLEEP_KEEP_RES_ON 0x42 87 #define TPS65910_SLEEP_SET_LDO_OFF 0x43 88 #define TPS65910_SLEEP_SET_RES_OFF 0x44 89 #define TPS65910_EN1_LDO_ASS 0x45 90 #define TPS65910_EN1_SMPS_ASS 0x46 91 #define TPS65910_EN2_LDO_ASS 0x47 92 #define TPS65910_EN2_SMPS_ASS 0x48 93 #define TPS65910_EN3_LDO_ASS 0x49 94 #define TPS65910_SPARE 0x4A 95 #define TPS65910_INT_STS 0x50 96 #define TPS65910_INT_MSK 0x51 97 #define TPS65910_INT_STS2 0x52 98 #define TPS65910_INT_MSK2 0x53 99 #define TPS65910_INT_STS3 0x54 100 #define TPS65910_INT_MSK3 0x55 101 #define TPS65910_GPIO0 0x60 102 #define TPS65910_GPIO1 0x61 103 #define TPS65910_GPIO2 0x62 104 #define TPS65910_GPIO3 0x63 105 #define TPS65910_GPIO4 0x64 106 #define TPS65910_GPIO5 0x65 107 #define TPS65910_GPIO6 0x66 108 #define TPS65910_GPIO7 0x67 109 #define TPS65910_GPIO8 0x68 110 #define TPS65910_JTAGVERNUM 0x80 111 #define TPS65910_MAX_REGISTER 0x80 112 113 /* 114 * List of registers specific to TPS65911 115 */ 116 #define TPS65911_VDDCTRL 0x27 117 #define TPS65911_VDDCTRL_OP 0x28 118 #define TPS65911_VDDCTRL_SR 0x29 119 #define TPS65911_LDO1 0x30 120 #define TPS65911_LDO2 0x31 121 #define TPS65911_LDO5 0x32 122 #define TPS65911_LDO8 0x33 123 #define TPS65911_LDO7 0x34 124 #define TPS65911_LDO6 0x35 125 #define TPS65911_LDO4 0x36 126 #define TPS65911_LDO3 0x37 127 #define TPS65911_VMBCH 0x6A 128 #define TPS65911_VMBCH2 0x6B 129 130 /* 131 * List of register bitfields for component TPS65910 132 * 133 */ 134 135 /* RTC_CTRL_REG bitfields */ 136 #define TPS65910_RTC_CTRL_STOP_RTC 0x01 /*0=stop, 1=run */ 137 #define TPS65910_RTC_CTRL_GET_TIME 0x40 138 139 /* RTC_STATUS_REG bitfields */ 140 #define TPS65910_RTC_STATUS_ALARM 0x40 141 142 /* RTC_INTERRUPTS_REG bitfields */ 143 #define TPS65910_RTC_INTERRUPTS_EVERY 0x03 144 #define TPS65910_RTC_INTERRUPTS_IT_ALARM 0x08 145 146 /*Register BCK1 (0x80) register.RegisterDescription */ 147 #define BCK1_BCKUP_MASK 0xFF 148 #define BCK1_BCKUP_SHIFT 0 149 150 151 /*Register BCK2 (0x80) register.RegisterDescription */ 152 #define BCK2_BCKUP_MASK 0xFF 153 #define BCK2_BCKUP_SHIFT 0 154 155 156 /*Register BCK3 (0x80) register.RegisterDescription */ 157 #define BCK3_BCKUP_MASK 0xFF 158 #define BCK3_BCKUP_SHIFT 0 159 160 161 /*Register BCK4 (0x80) register.RegisterDescription */ 162 #define BCK4_BCKUP_MASK 0xFF 163 #define BCK4_BCKUP_SHIFT 0 164 165 166 /*Register BCK5 (0x80) register.RegisterDescription */ 167 #define BCK5_BCKUP_MASK 0xFF 168 #define BCK5_BCKUP_SHIFT 0 169 170 171 /*Register PUADEN (0x80) register.RegisterDescription */ 172 #define PUADEN_EN3P_MASK 0x80 173 #define PUADEN_EN3P_SHIFT 7 174 #define PUADEN_I2CCTLP_MASK 0x40 175 #define PUADEN_I2CCTLP_SHIFT 6 176 #define PUADEN_I2CSRP_MASK 0x20 177 #define PUADEN_I2CSRP_SHIFT 5 178 #define PUADEN_PWRONP_MASK 0x10 179 #define PUADEN_PWRONP_SHIFT 4 180 #define PUADEN_SLEEPP_MASK 0x08 181 #define PUADEN_SLEEPP_SHIFT 3 182 #define PUADEN_PWRHOLDP_MASK 0x04 183 #define PUADEN_PWRHOLDP_SHIFT 2 184 #define PUADEN_BOOT1P_MASK 0x02 185 #define PUADEN_BOOT1P_SHIFT 1 186 #define PUADEN_BOOT0P_MASK 0x01 187 #define PUADEN_BOOT0P_SHIFT 0 188 189 190 /*Register REF (0x80) register.RegisterDescription */ 191 #define REF_VMBCH_SEL_MASK 0x0C 192 #define REF_VMBCH_SEL_SHIFT 2 193 #define REF_ST_MASK 0x03 194 #define REF_ST_SHIFT 0 195 196 197 /*Register VRTC (0x80) register.RegisterDescription */ 198 #define VRTC_VRTC_OFFMASK_MASK 0x08 199 #define VRTC_VRTC_OFFMASK_SHIFT 3 200 #define VRTC_ST_MASK 0x03 201 #define VRTC_ST_SHIFT 0 202 203 204 /*Register VIO (0x80) register.RegisterDescription */ 205 #define VIO_ILMAX_MASK 0xC0 206 #define VIO_ILMAX_SHIFT 6 207 #define VIO_SEL_MASK 0x0C 208 #define VIO_SEL_SHIFT 2 209 #define VIO_ST_MASK 0x03 210 #define VIO_ST_SHIFT 0 211 212 213 /*Register VDD1 (0x80) register.RegisterDescription */ 214 #define VDD1_VGAIN_SEL_MASK 0xC0 215 #define VDD1_VGAIN_SEL_SHIFT 6 216 #define VDD1_ILMAX_MASK 0x20 217 #define VDD1_ILMAX_SHIFT 5 218 #define VDD1_TSTEP_MASK 0x1C 219 #define VDD1_TSTEP_SHIFT 2 220 #define VDD1_ST_MASK 0x03 221 #define VDD1_ST_SHIFT 0 222 223 224 /*Register VDD1_OP (0x80) register.RegisterDescription */ 225 #define VDD1_OP_CMD_MASK 0x80 226 #define VDD1_OP_CMD_SHIFT 7 227 #define VDD1_OP_SEL_MASK 0x7F 228 #define VDD1_OP_SEL_SHIFT 0 229 230 231 /*Register VDD1_SR (0x80) register.RegisterDescription */ 232 #define VDD1_SR_SEL_MASK 0x7F 233 #define VDD1_SR_SEL_SHIFT 0 234 235 236 /*Register VDD2 (0x80) register.RegisterDescription */ 237 #define VDD2_VGAIN_SEL_MASK 0xC0 238 #define VDD2_VGAIN_SEL_SHIFT 6 239 #define VDD2_ILMAX_MASK 0x20 240 #define VDD2_ILMAX_SHIFT 5 241 #define VDD2_TSTEP_MASK 0x1C 242 #define VDD2_TSTEP_SHIFT 2 243 #define VDD2_ST_MASK 0x03 244 #define VDD2_ST_SHIFT 0 245 246 247 /*Register VDD2_OP (0x80) register.RegisterDescription */ 248 #define VDD2_OP_CMD_MASK 0x80 249 #define VDD2_OP_CMD_SHIFT 7 250 #define VDD2_OP_SEL_MASK 0x7F 251 #define VDD2_OP_SEL_SHIFT 0 252 253 /*Register VDD2_SR (0x80) register.RegisterDescription */ 254 #define VDD2_SR_SEL_MASK 0x7F 255 #define VDD2_SR_SEL_SHIFT 0 256 257 258 /*Registers VDD1, VDD2 voltage values definitions */ 259 #define VDD1_2_NUM_VOLT_FINE 73 260 #define VDD1_2_NUM_VOLT_COARSE 3 261 #define VDD1_2_MIN_VOLT 6000 262 #define VDD1_2_OFFSET 125 263 264 265 /*Register VDD3 (0x80) register.RegisterDescription */ 266 #define VDD3_CKINEN_MASK 0x04 267 #define VDD3_CKINEN_SHIFT 2 268 #define VDD3_ST_MASK 0x03 269 #define VDD3_ST_SHIFT 0 270 #define VDDCTRL_MIN_VOLT 6000 271 #define VDDCTRL_OFFSET 125 272 273 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */ 274 #define LDO_SEL_MASK 0x0C 275 #define LDO_SEL_SHIFT 2 276 #define LDO_ST_MASK 0x03 277 #define LDO_ST_SHIFT 0 278 #define LDO_ST_ON_BIT 0x01 279 #define LDO_ST_MODE_BIT 0x02 280 281 282 /* Registers LDO1 to LDO8 in tps65910 */ 283 #define LDO1_SEL_MASK 0xFC 284 #define LDO3_SEL_MASK 0x7C 285 #define LDO_MIN_VOLT 1000 286 #define LDO_MAX_VOLT 3300 287 288 289 /*Register VDIG1 (0x80) register.RegisterDescription */ 290 #define VDIG1_SEL_MASK 0x0C 291 #define VDIG1_SEL_SHIFT 2 292 #define VDIG1_ST_MASK 0x03 293 #define VDIG1_ST_SHIFT 0 294 295 296 /*Register VDIG2 (0x80) register.RegisterDescription */ 297 #define VDIG2_SEL_MASK 0x0C 298 #define VDIG2_SEL_SHIFT 2 299 #define VDIG2_ST_MASK 0x03 300 #define VDIG2_ST_SHIFT 0 301 302 303 /*Register VAUX1 (0x80) register.RegisterDescription */ 304 #define VAUX1_SEL_MASK 0x0C 305 #define VAUX1_SEL_SHIFT 2 306 #define VAUX1_ST_MASK 0x03 307 #define VAUX1_ST_SHIFT 0 308 309 310 /*Register VAUX2 (0x80) register.RegisterDescription */ 311 #define VAUX2_SEL_MASK 0x0C 312 #define VAUX2_SEL_SHIFT 2 313 #define VAUX2_ST_MASK 0x03 314 #define VAUX2_ST_SHIFT 0 315 316 317 /*Register VAUX33 (0x80) register.RegisterDescription */ 318 #define VAUX33_SEL_MASK 0x0C 319 #define VAUX33_SEL_SHIFT 2 320 #define VAUX33_ST_MASK 0x03 321 #define VAUX33_ST_SHIFT 0 322 323 324 /*Register VMMC (0x80) register.RegisterDescription */ 325 #define VMMC_SEL_MASK 0x0C 326 #define VMMC_SEL_SHIFT 2 327 #define VMMC_ST_MASK 0x03 328 #define VMMC_ST_SHIFT 0 329 330 331 /*Register VPLL (0x80) register.RegisterDescription */ 332 #define VPLL_SEL_MASK 0x0C 333 #define VPLL_SEL_SHIFT 2 334 #define VPLL_ST_MASK 0x03 335 #define VPLL_ST_SHIFT 0 336 337 338 /*Register VDAC (0x80) register.RegisterDescription */ 339 #define VDAC_SEL_MASK 0x0C 340 #define VDAC_SEL_SHIFT 2 341 #define VDAC_ST_MASK 0x03 342 #define VDAC_ST_SHIFT 0 343 344 345 /*Register THERM (0x80) register.RegisterDescription */ 346 #define THERM_THERM_HD_MASK 0x20 347 #define THERM_THERM_HD_SHIFT 5 348 #define THERM_THERM_TS_MASK 0x10 349 #define THERM_THERM_TS_SHIFT 4 350 #define THERM_THERM_HDSEL_MASK 0x0C 351 #define THERM_THERM_HDSEL_SHIFT 2 352 #define THERM_RSVD1_MASK 0x02 353 #define THERM_RSVD1_SHIFT 1 354 #define THERM_THERM_STATE_MASK 0x01 355 #define THERM_THERM_STATE_SHIFT 0 356 357 358 /*Register BBCH (0x80) register.RegisterDescription */ 359 #define BBCH_BBSEL_MASK 0x06 360 #define BBCH_BBSEL_SHIFT 1 361 #define BBCH_BBCHEN_MASK 0x01 362 #define BBCH_BBCHEN_SHIFT 0 363 364 365 /*Register DCDCCTRL (0x80) register.RegisterDescription */ 366 #define DCDCCTRL_VDD2_PSKIP_MASK 0x20 367 #define DCDCCTRL_VDD2_PSKIP_SHIFT 5 368 #define DCDCCTRL_VDD1_PSKIP_MASK 0x10 369 #define DCDCCTRL_VDD1_PSKIP_SHIFT 4 370 #define DCDCCTRL_VIO_PSKIP_MASK 0x08 371 #define DCDCCTRL_VIO_PSKIP_SHIFT 3 372 #define DCDCCTRL_DCDCCKEXT_MASK 0x04 373 #define DCDCCTRL_DCDCCKEXT_SHIFT 2 374 #define DCDCCTRL_DCDCCKSYNC_MASK 0x03 375 #define DCDCCTRL_DCDCCKSYNC_SHIFT 0 376 377 378 /*Register DEVCTRL (0x80) register.RegisterDescription */ 379 #define DEVCTRL_RTC_PWDN_MASK 0x40 380 #define DEVCTRL_RTC_PWDN_SHIFT 6 381 #define DEVCTRL_CK32K_CTRL_MASK 0x20 382 #define DEVCTRL_CK32K_CTRL_SHIFT 5 383 #define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10 384 #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4 385 #define DEVCTRL_DEV_OFF_RST_MASK 0x08 386 #define DEVCTRL_DEV_OFF_RST_SHIFT 3 387 #define DEVCTRL_DEV_ON_MASK 0x04 388 #define DEVCTRL_DEV_ON_SHIFT 2 389 #define DEVCTRL_DEV_SLP_MASK 0x02 390 #define DEVCTRL_DEV_SLP_SHIFT 1 391 #define DEVCTRL_DEV_OFF_MASK 0x01 392 #define DEVCTRL_DEV_OFF_SHIFT 0 393 394 395 /*Register DEVCTRL2 (0x80) register.RegisterDescription */ 396 #define DEVCTRL2_TSLOT_LENGTH_MASK 0x30 397 #define DEVCTRL2_TSLOT_LENGTH_SHIFT 4 398 #define DEVCTRL2_SLEEPSIG_POL_MASK 0x08 399 #define DEVCTRL2_SLEEPSIG_POL_SHIFT 3 400 #define DEVCTRL2_PWON_LP_OFF_MASK 0x04 401 #define DEVCTRL2_PWON_LP_OFF_SHIFT 2 402 #define DEVCTRL2_PWON_LP_RST_MASK 0x02 403 #define DEVCTRL2_PWON_LP_RST_SHIFT 1 404 #define DEVCTRL2_IT_POL_MASK 0x01 405 #define DEVCTRL2_IT_POL_SHIFT 0 406 407 408 /*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */ 409 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80 410 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7 411 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40 412 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6 413 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20 414 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5 415 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10 416 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4 417 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08 418 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3 419 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04 420 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2 421 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02 422 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1 423 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01 424 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0 425 426 427 /*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */ 428 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80 429 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7 430 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40 431 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6 432 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20 433 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5 434 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10 435 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4 436 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08 437 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3 438 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04 439 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2 440 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02 441 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1 442 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01 443 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0 444 445 446 /*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */ 447 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80 448 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7 449 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40 450 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6 451 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20 452 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5 453 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10 454 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4 455 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08 456 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3 457 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04 458 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2 459 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02 460 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1 461 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01 462 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0 463 464 465 /*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */ 466 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80 467 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7 468 #define SLEEP_SET_RES_OFF_RSVD_MASK 0x60 469 #define SLEEP_SET_RES_OFF_RSVD_SHIFT 5 470 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10 471 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4 472 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08 473 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3 474 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04 475 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2 476 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02 477 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1 478 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01 479 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0 480 481 482 /*Register EN1_LDO_ASS (0x80) register.RegisterDescription */ 483 #define EN1_LDO_ASS_VDAC_EN1_MASK 0x80 484 #define EN1_LDO_ASS_VDAC_EN1_SHIFT 7 485 #define EN1_LDO_ASS_VPLL_EN1_MASK 0x40 486 #define EN1_LDO_ASS_VPLL_EN1_SHIFT 6 487 #define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20 488 #define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5 489 #define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10 490 #define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4 491 #define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08 492 #define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3 493 #define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04 494 #define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2 495 #define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02 496 #define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1 497 #define EN1_LDO_ASS_VMMC_EN1_MASK 0x01 498 #define EN1_LDO_ASS_VMMC_EN1_SHIFT 0 499 500 501 /*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */ 502 #define EN1_SMPS_ASS_RSVD_MASK 0xE0 503 #define EN1_SMPS_ASS_RSVD_SHIFT 5 504 #define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10 505 #define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4 506 #define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08 507 #define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3 508 #define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04 509 #define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2 510 #define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02 511 #define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1 512 #define EN1_SMPS_ASS_VIO_EN1_MASK 0x01 513 #define EN1_SMPS_ASS_VIO_EN1_SHIFT 0 514 515 516 /*Register EN2_LDO_ASS (0x80) register.RegisterDescription */ 517 #define EN2_LDO_ASS_VDAC_EN2_MASK 0x80 518 #define EN2_LDO_ASS_VDAC_EN2_SHIFT 7 519 #define EN2_LDO_ASS_VPLL_EN2_MASK 0x40 520 #define EN2_LDO_ASS_VPLL_EN2_SHIFT 6 521 #define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20 522 #define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5 523 #define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10 524 #define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4 525 #define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08 526 #define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3 527 #define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04 528 #define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2 529 #define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02 530 #define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1 531 #define EN2_LDO_ASS_VMMC_EN2_MASK 0x01 532 #define EN2_LDO_ASS_VMMC_EN2_SHIFT 0 533 534 535 /*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */ 536 #define EN2_SMPS_ASS_RSVD_MASK 0xE0 537 #define EN2_SMPS_ASS_RSVD_SHIFT 5 538 #define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10 539 #define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4 540 #define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08 541 #define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3 542 #define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04 543 #define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2 544 #define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02 545 #define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1 546 #define EN2_SMPS_ASS_VIO_EN2_MASK 0x01 547 #define EN2_SMPS_ASS_VIO_EN2_SHIFT 0 548 549 550 /*Register EN3_LDO_ASS (0x80) register.RegisterDescription */ 551 #define EN3_LDO_ASS_VDAC_EN3_MASK 0x80 552 #define EN3_LDO_ASS_VDAC_EN3_SHIFT 7 553 #define EN3_LDO_ASS_VPLL_EN3_MASK 0x40 554 #define EN3_LDO_ASS_VPLL_EN3_SHIFT 6 555 #define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20 556 #define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5 557 #define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10 558 #define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4 559 #define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08 560 #define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3 561 #define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04 562 #define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2 563 #define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02 564 #define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1 565 #define EN3_LDO_ASS_VMMC_EN3_MASK 0x01 566 #define EN3_LDO_ASS_VMMC_EN3_SHIFT 0 567 568 569 /*Register SPARE (0x80) register.RegisterDescription */ 570 #define SPARE_SPARE_MASK 0xFF 571 #define SPARE_SPARE_SHIFT 0 572 573 574 /*Register INT_STS (0x80) register.RegisterDescription */ 575 #define INT_STS_RTC_PERIOD_IT_MASK 0x80 576 #define INT_STS_RTC_PERIOD_IT_SHIFT 7 577 #define INT_STS_RTC_ALARM_IT_MASK 0x40 578 #define INT_STS_RTC_ALARM_IT_SHIFT 6 579 #define INT_STS_HOTDIE_IT_MASK 0x20 580 #define INT_STS_HOTDIE_IT_SHIFT 5 581 #define INT_STS_PWRHOLD_IT_MASK 0x10 582 #define INT_STS_PWRHOLD_IT_SHIFT 4 583 #define INT_STS_PWRON_LP_IT_MASK 0x08 584 #define INT_STS_PWRON_LP_IT_SHIFT 3 585 #define INT_STS_PWRON_IT_MASK 0x04 586 #define INT_STS_PWRON_IT_SHIFT 2 587 #define INT_STS_VMBHI_IT_MASK 0x02 588 #define INT_STS_VMBHI_IT_SHIFT 1 589 #define INT_STS_VMBDCH_IT_MASK 0x01 590 #define INT_STS_VMBDCH_IT_SHIFT 0 591 592 593 /*Register INT_MSK (0x80) register.RegisterDescription */ 594 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80 595 #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7 596 #define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40 597 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6 598 #define INT_MSK_HOTDIE_IT_MSK_MASK 0x20 599 #define INT_MSK_HOTDIE_IT_MSK_SHIFT 5 600 #define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10 601 #define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4 602 #define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08 603 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3 604 #define INT_MSK_PWRON_IT_MSK_MASK 0x04 605 #define INT_MSK_PWRON_IT_MSK_SHIFT 2 606 #define INT_MSK_VMBHI_IT_MSK_MASK 0x02 607 #define INT_MSK_VMBHI_IT_MSK_SHIFT 1 608 #define INT_MSK_VMBDCH_IT_MSK_MASK 0x01 609 #define INT_MSK_VMBDCH_IT_MSK_SHIFT 0 610 611 612 /*Register INT_STS2 (0x80) register.RegisterDescription */ 613 #define INT_STS2_GPIO3_F_IT_MASK 0x80 614 #define INT_STS2_GPIO3_F_IT_SHIFT 7 615 #define INT_STS2_GPIO3_R_IT_MASK 0x40 616 #define INT_STS2_GPIO3_R_IT_SHIFT 6 617 #define INT_STS2_GPIO2_F_IT_MASK 0x20 618 #define INT_STS2_GPIO2_F_IT_SHIFT 5 619 #define INT_STS2_GPIO2_R_IT_MASK 0x10 620 #define INT_STS2_GPIO2_R_IT_SHIFT 4 621 #define INT_STS2_GPIO1_F_IT_MASK 0x08 622 #define INT_STS2_GPIO1_F_IT_SHIFT 3 623 #define INT_STS2_GPIO1_R_IT_MASK 0x04 624 #define INT_STS2_GPIO1_R_IT_SHIFT 2 625 #define INT_STS2_GPIO0_F_IT_MASK 0x02 626 #define INT_STS2_GPIO0_F_IT_SHIFT 1 627 #define INT_STS2_GPIO0_R_IT_MASK 0x01 628 #define INT_STS2_GPIO0_R_IT_SHIFT 0 629 630 631 /*Register INT_MSK2 (0x80) register.RegisterDescription */ 632 #define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80 633 #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7 634 #define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40 635 #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6 636 #define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20 637 #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5 638 #define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10 639 #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4 640 #define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08 641 #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3 642 #define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04 643 #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2 644 #define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02 645 #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1 646 #define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01 647 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0 648 649 650 /*Register INT_STS3 (0x80) register.RegisterDescription */ 651 #define INT_STS3_GPIO5_F_IT_MASK 0x08 652 #define INT_STS3_GPIO5_F_IT_SHIFT 3 653 #define INT_STS3_GPIO5_R_IT_MASK 0x04 654 #define INT_STS3_GPIO5_R_IT_SHIFT 2 655 #define INT_STS3_GPIO4_F_IT_MASK 0x02 656 #define INT_STS3_GPIO4_F_IT_SHIFT 1 657 #define INT_STS3_GPIO4_R_IT_MASK 0x01 658 #define INT_STS3_GPIO4_R_IT_SHIFT 0 659 660 661 /*Register INT_MSK3 (0x80) register.RegisterDescription */ 662 #define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08 663 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3 664 #define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04 665 #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2 666 #define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02 667 #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1 668 #define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01 669 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0 670 671 672 /*Register GPIO (0x80) register.RegisterDescription */ 673 #define GPIO_SLEEP_MASK 0x80 674 #define GPIO_SLEEP_SHIFT 7 675 #define GPIO_DEB_MASK 0x10 676 #define GPIO_DEB_SHIFT 4 677 #define GPIO_PUEN_MASK 0x08 678 #define GPIO_PUEN_SHIFT 3 679 #define GPIO_CFG_MASK 0x04 680 #define GPIO_CFG_SHIFT 2 681 #define GPIO_STS_MASK 0x02 682 #define GPIO_STS_SHIFT 1 683 #define GPIO_SET_MASK 0x01 684 #define GPIO_SET_SHIFT 0 685 686 687 /*Register JTAGVERNUM (0x80) register.RegisterDescription */ 688 #define JTAGVERNUM_VERNUM_MASK 0x0F 689 #define JTAGVERNUM_VERNUM_SHIFT 0 690 691 692 /* Register VDDCTRL (0x27) bit definitions */ 693 #define VDDCTRL_ST_MASK 0x03 694 #define VDDCTRL_ST_SHIFT 0 695 696 697 /*Register VDDCTRL_OP (0x28) bit definitios */ 698 #define VDDCTRL_OP_CMD_MASK 0x80 699 #define VDDCTRL_OP_CMD_SHIFT 7 700 #define VDDCTRL_OP_SEL_MASK 0x7F 701 #define VDDCTRL_OP_SEL_SHIFT 0 702 703 704 /*Register VDDCTRL_SR (0x29) bit definitions */ 705 #define VDDCTRL_SR_SEL_MASK 0x7F 706 #define VDDCTRL_SR_SEL_SHIFT 0 707 708 709 /* IRQ Definitions */ 710 #define TPS65910_IRQ_VBAT_VMBDCH 0 711 #define TPS65910_IRQ_VBAT_VMHI 1 712 #define TPS65910_IRQ_PWRON 2 713 #define TPS65910_IRQ_PWRON_LP 3 714 #define TPS65910_IRQ_PWRHOLD 4 715 #define TPS65910_IRQ_HOTDIE 5 716 #define TPS65910_IRQ_RTC_ALARM 6 717 #define TPS65910_IRQ_RTC_PERIOD 7 718 #define TPS65910_IRQ_GPIO_R 8 719 #define TPS65910_IRQ_GPIO_F 9 720 #define TPS65910_NUM_IRQ 10 721 722 #define TPS65911_IRQ_VBAT_VMBDCH 0 723 #define TPS65911_IRQ_VBAT_VMBDCH2L 1 724 #define TPS65911_IRQ_VBAT_VMBDCH2H 2 725 #define TPS65911_IRQ_VBAT_VMHI 3 726 #define TPS65911_IRQ_PWRON 4 727 #define TPS65911_IRQ_PWRON_LP 5 728 #define TPS65911_IRQ_PWRHOLD_F 6 729 #define TPS65911_IRQ_PWRHOLD_R 7 730 #define TPS65911_IRQ_HOTDIE 8 731 #define TPS65911_IRQ_RTC_ALARM 9 732 #define TPS65911_IRQ_RTC_PERIOD 10 733 #define TPS65911_IRQ_GPIO0_R 11 734 #define TPS65911_IRQ_GPIO0_F 12 735 #define TPS65911_IRQ_GPIO1_R 13 736 #define TPS65911_IRQ_GPIO1_F 14 737 #define TPS65911_IRQ_GPIO2_R 15 738 #define TPS65911_IRQ_GPIO2_F 16 739 #define TPS65911_IRQ_GPIO3_R 17 740 #define TPS65911_IRQ_GPIO3_F 18 741 #define TPS65911_IRQ_GPIO4_R 19 742 #define TPS65911_IRQ_GPIO4_F 20 743 #define TPS65911_IRQ_GPIO5_R 21 744 #define TPS65911_IRQ_GPIO5_F 22 745 #define TPS65911_IRQ_WTCHDG 23 746 #define TPS65911_IRQ_PWRDN 24 747 748 #define TPS65911_NUM_IRQ 25 749 750 751 /* GPIO Register Definitions */ 752 #define TPS65910_GPIO_DEB BIT(2) 753 #define TPS65910_GPIO_PUEN BIT(3) 754 #define TPS65910_GPIO_CFG BIT(2) 755 #define TPS65910_GPIO_STS BIT(1) 756 #define TPS65910_GPIO_SET BIT(0) 757 758 /* Max number of TPS65910/11 GPIOs */ 759 #define TPS65910_NUM_GPIO 6 760 #define TPS65911_NUM_GPIO 9 761 #define TPS6591X_MAX_NUM_GPIO 9 762 763 /* Regulator Index Definitions */ 764 #define TPS65910_REG_VRTC 0 765 #define TPS65910_REG_VIO 1 766 #define TPS65910_REG_VDD1 2 767 #define TPS65910_REG_VDD2 3 768 #define TPS65910_REG_VDD3 4 769 #define TPS65910_REG_VDIG1 5 770 #define TPS65910_REG_VDIG2 6 771 #define TPS65910_REG_VPLL 7 772 #define TPS65910_REG_VDAC 8 773 #define TPS65910_REG_VAUX1 9 774 #define TPS65910_REG_VAUX2 10 775 #define TPS65910_REG_VAUX33 11 776 #define TPS65910_REG_VMMC 12 777 778 #define TPS65911_REG_VDDCTRL 4 779 #define TPS65911_REG_LDO1 5 780 #define TPS65911_REG_LDO2 6 781 #define TPS65911_REG_LDO3 7 782 #define TPS65911_REG_LDO4 8 783 #define TPS65911_REG_LDO5 9 784 #define TPS65911_REG_LDO6 10 785 #define TPS65911_REG_LDO7 11 786 #define TPS65911_REG_LDO8 12 787 788 /* Max number of TPS65910/11 regulators */ 789 #define TPS65910_NUM_REGS 13 790 791 /* External sleep controls through EN1/EN2/EN3/SLEEP inputs */ 792 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 0x1 793 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 0x2 794 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 0x4 795 #define TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP 0x8 796 797 /* 798 * Sleep keepon data: Maintains the state in sleep mode 799 * @therm_keepon: Keep on the thermal monitoring in sleep state. 800 * @clkout32k_keepon: Keep on the 32KHz clock output in sleep state. 801 * @i2chs_keepon: Keep on high speed internal clock in sleep state. 802 */ 803 struct tps65910_sleep_keepon_data { 804 unsigned therm_keepon:1; 805 unsigned clkout32k_keepon:1; 806 unsigned i2chs_keepon:1; 807 }; 808 809 /** 810 * struct tps65910_board 811 * Board platform data may be used to initialize regulators. 812 */ 813 814 struct tps65910_board { 815 int gpio_base; 816 int irq; 817 int irq_base; 818 int vmbch_threshold; 819 int vmbch2_threshold; 820 bool en_ck32k_xtal; 821 bool en_dev_slp; 822 struct tps65910_sleep_keepon_data *slp_keepon; 823 bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO]; 824 unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS]; 825 struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS]; 826 }; 827 828 /** 829 * struct tps65910 - tps65910 sub-driver chip access routines 830 */ 831 832 struct tps65910 { 833 struct device *dev; 834 struct i2c_client *i2c_client; 835 struct regmap *regmap; 836 struct mutex io_mutex; 837 unsigned int id; 838 839 /* Client devices */ 840 struct tps65910_pmic *pmic; 841 struct tps65910_rtc *rtc; 842 struct tps65910_power *power; 843 844 /* Device node parsed board data */ 845 struct tps65910_board *of_plat_data; 846 847 /* IRQ Handling */ 848 struct mutex irq_lock; 849 int chip_irq; 850 int irq_base; 851 int irq_num; 852 u32 irq_mask; 853 struct irq_domain *domain; 854 }; 855 856 struct tps65910_platform_data { 857 int irq; 858 int irq_base; 859 }; 860 861 int tps65910_irq_init(struct tps65910 *tps65910, int irq, 862 struct tps65910_platform_data *pdata); 863 int tps65910_irq_exit(struct tps65910 *tps65910); 864 865 static inline int tps65910_chip_id(struct tps65910 *tps65910) 866 { 867 return tps65910->id; 868 } 869 870 static inline int tps65910_reg_read(struct tps65910 *tps65910, u8 reg, 871 unsigned int *val) 872 { 873 return regmap_read(tps65910->regmap, reg, val); 874 } 875 876 static inline int tps65910_reg_write(struct tps65910 *tps65910, u8 reg, 877 unsigned int val) 878 { 879 return regmap_write(tps65910->regmap, reg, val); 880 } 881 882 static inline int tps65910_reg_set_bits(struct tps65910 *tps65910, u8 reg, 883 u8 mask) 884 { 885 return regmap_update_bits(tps65910->regmap, reg, mask, mask); 886 } 887 888 static inline int tps65910_reg_clear_bits(struct tps65910 *tps65910, u8 reg, 889 u8 mask) 890 { 891 return regmap_update_bits(tps65910->regmap, reg, mask, 0); 892 } 893 894 static inline int tps65910_reg_update_bits(struct tps65910 *tps65910, u8 reg, 895 u8 mask, u8 val) 896 { 897 return regmap_update_bits(tps65910->regmap, reg, mask, val); 898 } 899 900 #endif /* __LINUX_MFD_TPS65910_H */ 901