1 /* 2 * tps65910.h -- TI TPS6591x 3 * 4 * Copyright 2010-2011 Texas Instruments Inc. 5 * 6 * Author: Graeme Gregory <[email protected]> 7 * Author: Jorge Eduardo Candelaria <[email protected]> 8 * Author: Arnaud Deconinck <[email protected]> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 17 #ifndef __LINUX_MFD_TPS65910_H 18 #define __LINUX_MFD_TPS65910_H 19 20 #include <linux/gpio.h> 21 #include <linux/regmap.h> 22 23 /* TPS chip id list */ 24 #define TPS65910 0 25 #define TPS65911 1 26 27 /* TPS regulator type list */ 28 #define REGULATOR_LDO 0 29 #define REGULATOR_DCDC 1 30 31 /* 32 * List of registers for component TPS65910 33 * 34 */ 35 36 #define TPS65910_SECONDS 0x0 37 #define TPS65910_MINUTES 0x1 38 #define TPS65910_HOURS 0x2 39 #define TPS65910_DAYS 0x3 40 #define TPS65910_MONTHS 0x4 41 #define TPS65910_YEARS 0x5 42 #define TPS65910_WEEKS 0x6 43 #define TPS65910_ALARM_SECONDS 0x8 44 #define TPS65910_ALARM_MINUTES 0x9 45 #define TPS65910_ALARM_HOURS 0xA 46 #define TPS65910_ALARM_DAYS 0xB 47 #define TPS65910_ALARM_MONTHS 0xC 48 #define TPS65910_ALARM_YEARS 0xD 49 #define TPS65910_RTC_CTRL 0x10 50 #define TPS65910_RTC_STATUS 0x11 51 #define TPS65910_RTC_INTERRUPTS 0x12 52 #define TPS65910_RTC_COMP_LSB 0x13 53 #define TPS65910_RTC_COMP_MSB 0x14 54 #define TPS65910_RTC_RES_PROG 0x15 55 #define TPS65910_RTC_RESET_STATUS 0x16 56 #define TPS65910_BCK1 0x17 57 #define TPS65910_BCK2 0x18 58 #define TPS65910_BCK3 0x19 59 #define TPS65910_BCK4 0x1A 60 #define TPS65910_BCK5 0x1B 61 #define TPS65910_PUADEN 0x1C 62 #define TPS65910_REF 0x1D 63 #define TPS65910_VRTC 0x1E 64 #define TPS65910_VIO 0x20 65 #define TPS65910_VDD1 0x21 66 #define TPS65910_VDD1_OP 0x22 67 #define TPS65910_VDD1_SR 0x23 68 #define TPS65910_VDD2 0x24 69 #define TPS65910_VDD2_OP 0x25 70 #define TPS65910_VDD2_SR 0x26 71 #define TPS65910_VDD3 0x27 72 #define TPS65910_VDIG1 0x30 73 #define TPS65910_VDIG2 0x31 74 #define TPS65910_VAUX1 0x32 75 #define TPS65910_VAUX2 0x33 76 #define TPS65910_VAUX33 0x34 77 #define TPS65910_VMMC 0x35 78 #define TPS65910_VPLL 0x36 79 #define TPS65910_VDAC 0x37 80 #define TPS65910_THERM 0x38 81 #define TPS65910_BBCH 0x39 82 #define TPS65910_DCDCCTRL 0x3E 83 #define TPS65910_DEVCTRL 0x3F 84 #define TPS65910_DEVCTRL2 0x40 85 #define TPS65910_SLEEP_KEEP_LDO_ON 0x41 86 #define TPS65910_SLEEP_KEEP_RES_ON 0x42 87 #define TPS65910_SLEEP_SET_LDO_OFF 0x43 88 #define TPS65910_SLEEP_SET_RES_OFF 0x44 89 #define TPS65910_EN1_LDO_ASS 0x45 90 #define TPS65910_EN1_SMPS_ASS 0x46 91 #define TPS65910_EN2_LDO_ASS 0x47 92 #define TPS65910_EN2_SMPS_ASS 0x48 93 #define TPS65910_EN3_LDO_ASS 0x49 94 #define TPS65910_SPARE 0x4A 95 #define TPS65910_INT_STS 0x50 96 #define TPS65910_INT_MSK 0x51 97 #define TPS65910_INT_STS2 0x52 98 #define TPS65910_INT_MSK2 0x53 99 #define TPS65910_INT_STS3 0x54 100 #define TPS65910_INT_MSK3 0x55 101 #define TPS65910_GPIO0 0x60 102 #define TPS65910_GPIO1 0x61 103 #define TPS65910_GPIO2 0x62 104 #define TPS65910_GPIO3 0x63 105 #define TPS65910_GPIO4 0x64 106 #define TPS65910_GPIO5 0x65 107 #define TPS65910_GPIO6 0x66 108 #define TPS65910_GPIO7 0x67 109 #define TPS65910_GPIO8 0x68 110 #define TPS65910_JTAGVERNUM 0x80 111 #define TPS65910_MAX_REGISTER 0x80 112 113 /* 114 * List of registers specific to TPS65911 115 */ 116 #define TPS65911_VDDCTRL 0x27 117 #define TPS65911_VDDCTRL_OP 0x28 118 #define TPS65911_VDDCTRL_SR 0x29 119 #define TPS65911_LDO1 0x30 120 #define TPS65911_LDO2 0x31 121 #define TPS65911_LDO5 0x32 122 #define TPS65911_LDO8 0x33 123 #define TPS65911_LDO7 0x34 124 #define TPS65911_LDO6 0x35 125 #define TPS65911_LDO4 0x36 126 #define TPS65911_LDO3 0x37 127 #define TPS65911_VMBCH 0x6A 128 #define TPS65911_VMBCH2 0x6B 129 130 /* 131 * List of register bitfields for component TPS65910 132 * 133 */ 134 135 /* RTC_CTRL_REG bitfields */ 136 #define TPS65910_RTC_CTRL_STOP_RTC 0x01 /*0=stop, 1=run */ 137 #define TPS65910_RTC_CTRL_GET_TIME 0x40 138 139 /* RTC_STATUS_REG bitfields */ 140 #define TPS65910_RTC_STATUS_ALARM 0x40 141 142 /* RTC_INTERRUPTS_REG bitfields */ 143 #define TPS65910_RTC_INTERRUPTS_EVERY 0x03 144 #define TPS65910_RTC_INTERRUPTS_IT_ALARM 0x08 145 146 /*Register BCK1 (0x80) register.RegisterDescription */ 147 #define BCK1_BCKUP_MASK 0xFF 148 #define BCK1_BCKUP_SHIFT 0 149 150 151 /*Register BCK2 (0x80) register.RegisterDescription */ 152 #define BCK2_BCKUP_MASK 0xFF 153 #define BCK2_BCKUP_SHIFT 0 154 155 156 /*Register BCK3 (0x80) register.RegisterDescription */ 157 #define BCK3_BCKUP_MASK 0xFF 158 #define BCK3_BCKUP_SHIFT 0 159 160 161 /*Register BCK4 (0x80) register.RegisterDescription */ 162 #define BCK4_BCKUP_MASK 0xFF 163 #define BCK4_BCKUP_SHIFT 0 164 165 166 /*Register BCK5 (0x80) register.RegisterDescription */ 167 #define BCK5_BCKUP_MASK 0xFF 168 #define BCK5_BCKUP_SHIFT 0 169 170 171 /*Register PUADEN (0x80) register.RegisterDescription */ 172 #define PUADEN_EN3P_MASK 0x80 173 #define PUADEN_EN3P_SHIFT 7 174 #define PUADEN_I2CCTLP_MASK 0x40 175 #define PUADEN_I2CCTLP_SHIFT 6 176 #define PUADEN_I2CSRP_MASK 0x20 177 #define PUADEN_I2CSRP_SHIFT 5 178 #define PUADEN_PWRONP_MASK 0x10 179 #define PUADEN_PWRONP_SHIFT 4 180 #define PUADEN_SLEEPP_MASK 0x08 181 #define PUADEN_SLEEPP_SHIFT 3 182 #define PUADEN_PWRHOLDP_MASK 0x04 183 #define PUADEN_PWRHOLDP_SHIFT 2 184 #define PUADEN_BOOT1P_MASK 0x02 185 #define PUADEN_BOOT1P_SHIFT 1 186 #define PUADEN_BOOT0P_MASK 0x01 187 #define PUADEN_BOOT0P_SHIFT 0 188 189 190 /*Register REF (0x80) register.RegisterDescription */ 191 #define REF_VMBCH_SEL_MASK 0x0C 192 #define REF_VMBCH_SEL_SHIFT 2 193 #define REF_ST_MASK 0x03 194 #define REF_ST_SHIFT 0 195 196 197 /*Register VRTC (0x80) register.RegisterDescription */ 198 #define VRTC_VRTC_OFFMASK_MASK 0x08 199 #define VRTC_VRTC_OFFMASK_SHIFT 3 200 #define VRTC_ST_MASK 0x03 201 #define VRTC_ST_SHIFT 0 202 203 204 /*Register VIO (0x80) register.RegisterDescription */ 205 #define VIO_ILMAX_MASK 0xC0 206 #define VIO_ILMAX_SHIFT 6 207 #define VIO_SEL_MASK 0x0C 208 #define VIO_SEL_SHIFT 2 209 #define VIO_ST_MASK 0x03 210 #define VIO_ST_SHIFT 0 211 212 213 /*Register VDD1 (0x80) register.RegisterDescription */ 214 #define VDD1_VGAIN_SEL_MASK 0xC0 215 #define VDD1_VGAIN_SEL_SHIFT 6 216 #define VDD1_ILMAX_MASK 0x20 217 #define VDD1_ILMAX_SHIFT 5 218 #define VDD1_TSTEP_MASK 0x1C 219 #define VDD1_TSTEP_SHIFT 2 220 #define VDD1_ST_MASK 0x03 221 #define VDD1_ST_SHIFT 0 222 223 224 /*Register VDD1_OP (0x80) register.RegisterDescription */ 225 #define VDD1_OP_CMD_MASK 0x80 226 #define VDD1_OP_CMD_SHIFT 7 227 #define VDD1_OP_SEL_MASK 0x7F 228 #define VDD1_OP_SEL_SHIFT 0 229 230 231 /*Register VDD1_SR (0x80) register.RegisterDescription */ 232 #define VDD1_SR_SEL_MASK 0x7F 233 #define VDD1_SR_SEL_SHIFT 0 234 235 236 /*Register VDD2 (0x80) register.RegisterDescription */ 237 #define VDD2_VGAIN_SEL_MASK 0xC0 238 #define VDD2_VGAIN_SEL_SHIFT 6 239 #define VDD2_ILMAX_MASK 0x20 240 #define VDD2_ILMAX_SHIFT 5 241 #define VDD2_TSTEP_MASK 0x1C 242 #define VDD2_TSTEP_SHIFT 2 243 #define VDD2_ST_MASK 0x03 244 #define VDD2_ST_SHIFT 0 245 246 247 /*Register VDD2_OP (0x80) register.RegisterDescription */ 248 #define VDD2_OP_CMD_MASK 0x80 249 #define VDD2_OP_CMD_SHIFT 7 250 #define VDD2_OP_SEL_MASK 0x7F 251 #define VDD2_OP_SEL_SHIFT 0 252 253 /*Register VDD2_SR (0x80) register.RegisterDescription */ 254 #define VDD2_SR_SEL_MASK 0x7F 255 #define VDD2_SR_SEL_SHIFT 0 256 257 258 /*Registers VDD1, VDD2 voltage values definitions */ 259 #define VDD1_2_NUM_VOLT_FINE 73 260 #define VDD1_2_NUM_VOLT_COARSE 3 261 #define VDD1_2_MIN_VOLT 6000 262 #define VDD1_2_OFFSET 125 263 264 265 /*Register VDD3 (0x80) register.RegisterDescription */ 266 #define VDD3_CKINEN_MASK 0x04 267 #define VDD3_CKINEN_SHIFT 2 268 #define VDD3_ST_MASK 0x03 269 #define VDD3_ST_SHIFT 0 270 #define VDDCTRL_MIN_VOLT 6000 271 #define VDDCTRL_OFFSET 125 272 273 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */ 274 #define LDO_SEL_MASK 0x0C 275 #define LDO_SEL_SHIFT 2 276 #define LDO_ST_MASK 0x03 277 #define LDO_ST_SHIFT 0 278 #define LDO_ST_ON_BIT 0x01 279 #define LDO_ST_MODE_BIT 0x02 280 281 282 /* Registers LDO1 to LDO8 in tps65910 */ 283 #define LDO1_SEL_MASK 0xFC 284 #define LDO3_SEL_MASK 0x7C 285 #define LDO_MIN_VOLT 1000 286 #define LDO_MAX_VOLT 3300 287 288 289 /*Register VDIG1 (0x80) register.RegisterDescription */ 290 #define VDIG1_SEL_MASK 0x0C 291 #define VDIG1_SEL_SHIFT 2 292 #define VDIG1_ST_MASK 0x03 293 #define VDIG1_ST_SHIFT 0 294 295 296 /*Register VDIG2 (0x80) register.RegisterDescription */ 297 #define VDIG2_SEL_MASK 0x0C 298 #define VDIG2_SEL_SHIFT 2 299 #define VDIG2_ST_MASK 0x03 300 #define VDIG2_ST_SHIFT 0 301 302 303 /*Register VAUX1 (0x80) register.RegisterDescription */ 304 #define VAUX1_SEL_MASK 0x0C 305 #define VAUX1_SEL_SHIFT 2 306 #define VAUX1_ST_MASK 0x03 307 #define VAUX1_ST_SHIFT 0 308 309 310 /*Register VAUX2 (0x80) register.RegisterDescription */ 311 #define VAUX2_SEL_MASK 0x0C 312 #define VAUX2_SEL_SHIFT 2 313 #define VAUX2_ST_MASK 0x03 314 #define VAUX2_ST_SHIFT 0 315 316 317 /*Register VAUX33 (0x80) register.RegisterDescription */ 318 #define VAUX33_SEL_MASK 0x0C 319 #define VAUX33_SEL_SHIFT 2 320 #define VAUX33_ST_MASK 0x03 321 #define VAUX33_ST_SHIFT 0 322 323 324 /*Register VMMC (0x80) register.RegisterDescription */ 325 #define VMMC_SEL_MASK 0x0C 326 #define VMMC_SEL_SHIFT 2 327 #define VMMC_ST_MASK 0x03 328 #define VMMC_ST_SHIFT 0 329 330 331 /*Register VPLL (0x80) register.RegisterDescription */ 332 #define VPLL_SEL_MASK 0x0C 333 #define VPLL_SEL_SHIFT 2 334 #define VPLL_ST_MASK 0x03 335 #define VPLL_ST_SHIFT 0 336 337 338 /*Register VDAC (0x80) register.RegisterDescription */ 339 #define VDAC_SEL_MASK 0x0C 340 #define VDAC_SEL_SHIFT 2 341 #define VDAC_ST_MASK 0x03 342 #define VDAC_ST_SHIFT 0 343 344 345 /*Register THERM (0x80) register.RegisterDescription */ 346 #define THERM_THERM_HD_MASK 0x20 347 #define THERM_THERM_HD_SHIFT 5 348 #define THERM_THERM_TS_MASK 0x10 349 #define THERM_THERM_TS_SHIFT 4 350 #define THERM_THERM_HDSEL_MASK 0x0C 351 #define THERM_THERM_HDSEL_SHIFT 2 352 #define THERM_RSVD1_MASK 0x02 353 #define THERM_RSVD1_SHIFT 1 354 #define THERM_THERM_STATE_MASK 0x01 355 #define THERM_THERM_STATE_SHIFT 0 356 357 358 /*Register BBCH (0x80) register.RegisterDescription */ 359 #define BBCH_BBSEL_MASK 0x06 360 #define BBCH_BBSEL_SHIFT 1 361 #define BBCH_BBCHEN_MASK 0x01 362 #define BBCH_BBCHEN_SHIFT 0 363 364 365 /*Register DCDCCTRL (0x80) register.RegisterDescription */ 366 #define DCDCCTRL_VDD2_PSKIP_MASK 0x20 367 #define DCDCCTRL_VDD2_PSKIP_SHIFT 5 368 #define DCDCCTRL_VDD1_PSKIP_MASK 0x10 369 #define DCDCCTRL_VDD1_PSKIP_SHIFT 4 370 #define DCDCCTRL_VIO_PSKIP_MASK 0x08 371 #define DCDCCTRL_VIO_PSKIP_SHIFT 3 372 #define DCDCCTRL_DCDCCKEXT_MASK 0x04 373 #define DCDCCTRL_DCDCCKEXT_SHIFT 2 374 #define DCDCCTRL_DCDCCKSYNC_MASK 0x03 375 #define DCDCCTRL_DCDCCKSYNC_SHIFT 0 376 377 378 /*Register DEVCTRL (0x80) register.RegisterDescription */ 379 #define DEVCTRL_PWR_OFF_MASK 0x80 380 #define DEVCTRL_PWR_OFF_SHIFT 7 381 #define DEVCTRL_RTC_PWDN_MASK 0x40 382 #define DEVCTRL_RTC_PWDN_SHIFT 6 383 #define DEVCTRL_CK32K_CTRL_MASK 0x20 384 #define DEVCTRL_CK32K_CTRL_SHIFT 5 385 #define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10 386 #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4 387 #define DEVCTRL_DEV_OFF_RST_MASK 0x08 388 #define DEVCTRL_DEV_OFF_RST_SHIFT 3 389 #define DEVCTRL_DEV_ON_MASK 0x04 390 #define DEVCTRL_DEV_ON_SHIFT 2 391 #define DEVCTRL_DEV_SLP_MASK 0x02 392 #define DEVCTRL_DEV_SLP_SHIFT 1 393 #define DEVCTRL_DEV_OFF_MASK 0x01 394 #define DEVCTRL_DEV_OFF_SHIFT 0 395 396 397 /*Register DEVCTRL2 (0x80) register.RegisterDescription */ 398 #define DEVCTRL2_TSLOT_LENGTH_MASK 0x30 399 #define DEVCTRL2_TSLOT_LENGTH_SHIFT 4 400 #define DEVCTRL2_SLEEPSIG_POL_MASK 0x08 401 #define DEVCTRL2_SLEEPSIG_POL_SHIFT 3 402 #define DEVCTRL2_PWON_LP_OFF_MASK 0x04 403 #define DEVCTRL2_PWON_LP_OFF_SHIFT 2 404 #define DEVCTRL2_PWON_LP_RST_MASK 0x02 405 #define DEVCTRL2_PWON_LP_RST_SHIFT 1 406 #define DEVCTRL2_IT_POL_MASK 0x01 407 #define DEVCTRL2_IT_POL_SHIFT 0 408 409 410 /*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */ 411 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80 412 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7 413 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40 414 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6 415 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20 416 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5 417 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10 418 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4 419 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08 420 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3 421 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04 422 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2 423 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02 424 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1 425 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01 426 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0 427 428 429 /*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */ 430 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80 431 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7 432 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40 433 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6 434 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20 435 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5 436 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10 437 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4 438 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08 439 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3 440 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04 441 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2 442 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02 443 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1 444 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01 445 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0 446 447 448 /*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */ 449 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80 450 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7 451 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40 452 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6 453 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20 454 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5 455 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10 456 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4 457 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08 458 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3 459 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04 460 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2 461 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02 462 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1 463 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01 464 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0 465 466 467 /*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */ 468 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80 469 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7 470 #define SLEEP_SET_RES_OFF_RSVD_MASK 0x60 471 #define SLEEP_SET_RES_OFF_RSVD_SHIFT 5 472 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10 473 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4 474 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08 475 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3 476 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04 477 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2 478 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02 479 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1 480 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01 481 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0 482 483 484 /*Register EN1_LDO_ASS (0x80) register.RegisterDescription */ 485 #define EN1_LDO_ASS_VDAC_EN1_MASK 0x80 486 #define EN1_LDO_ASS_VDAC_EN1_SHIFT 7 487 #define EN1_LDO_ASS_VPLL_EN1_MASK 0x40 488 #define EN1_LDO_ASS_VPLL_EN1_SHIFT 6 489 #define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20 490 #define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5 491 #define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10 492 #define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4 493 #define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08 494 #define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3 495 #define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04 496 #define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2 497 #define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02 498 #define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1 499 #define EN1_LDO_ASS_VMMC_EN1_MASK 0x01 500 #define EN1_LDO_ASS_VMMC_EN1_SHIFT 0 501 502 503 /*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */ 504 #define EN1_SMPS_ASS_RSVD_MASK 0xE0 505 #define EN1_SMPS_ASS_RSVD_SHIFT 5 506 #define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10 507 #define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4 508 #define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08 509 #define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3 510 #define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04 511 #define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2 512 #define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02 513 #define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1 514 #define EN1_SMPS_ASS_VIO_EN1_MASK 0x01 515 #define EN1_SMPS_ASS_VIO_EN1_SHIFT 0 516 517 518 /*Register EN2_LDO_ASS (0x80) register.RegisterDescription */ 519 #define EN2_LDO_ASS_VDAC_EN2_MASK 0x80 520 #define EN2_LDO_ASS_VDAC_EN2_SHIFT 7 521 #define EN2_LDO_ASS_VPLL_EN2_MASK 0x40 522 #define EN2_LDO_ASS_VPLL_EN2_SHIFT 6 523 #define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20 524 #define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5 525 #define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10 526 #define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4 527 #define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08 528 #define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3 529 #define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04 530 #define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2 531 #define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02 532 #define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1 533 #define EN2_LDO_ASS_VMMC_EN2_MASK 0x01 534 #define EN2_LDO_ASS_VMMC_EN2_SHIFT 0 535 536 537 /*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */ 538 #define EN2_SMPS_ASS_RSVD_MASK 0xE0 539 #define EN2_SMPS_ASS_RSVD_SHIFT 5 540 #define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10 541 #define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4 542 #define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08 543 #define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3 544 #define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04 545 #define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2 546 #define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02 547 #define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1 548 #define EN2_SMPS_ASS_VIO_EN2_MASK 0x01 549 #define EN2_SMPS_ASS_VIO_EN2_SHIFT 0 550 551 552 /*Register EN3_LDO_ASS (0x80) register.RegisterDescription */ 553 #define EN3_LDO_ASS_VDAC_EN3_MASK 0x80 554 #define EN3_LDO_ASS_VDAC_EN3_SHIFT 7 555 #define EN3_LDO_ASS_VPLL_EN3_MASK 0x40 556 #define EN3_LDO_ASS_VPLL_EN3_SHIFT 6 557 #define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20 558 #define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5 559 #define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10 560 #define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4 561 #define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08 562 #define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3 563 #define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04 564 #define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2 565 #define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02 566 #define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1 567 #define EN3_LDO_ASS_VMMC_EN3_MASK 0x01 568 #define EN3_LDO_ASS_VMMC_EN3_SHIFT 0 569 570 571 /*Register SPARE (0x80) register.RegisterDescription */ 572 #define SPARE_SPARE_MASK 0xFF 573 #define SPARE_SPARE_SHIFT 0 574 575 #define TPS65910_INT_STS_RTC_PERIOD_IT_MASK 0x80 576 #define TPS65910_INT_STS_RTC_PERIOD_IT_SHIFT 7 577 #define TPS65910_INT_STS_RTC_ALARM_IT_MASK 0x40 578 #define TPS65910_INT_STS_RTC_ALARM_IT_SHIFT 6 579 #define TPS65910_INT_STS_HOTDIE_IT_MASK 0x20 580 #define TPS65910_INT_STS_HOTDIE_IT_SHIFT 5 581 #define TPS65910_INT_STS_PWRHOLD_F_IT_MASK 0x10 582 #define TPS65910_INT_STS_PWRHOLD_F_IT_SHIFT 4 583 #define TPS65910_INT_STS_PWRON_LP_IT_MASK 0x08 584 #define TPS65910_INT_STS_PWRON_LP_IT_SHIFT 3 585 #define TPS65910_INT_STS_PWRON_IT_MASK 0x04 586 #define TPS65910_INT_STS_PWRON_IT_SHIFT 2 587 #define TPS65910_INT_STS_VMBHI_IT_MASK 0x02 588 #define TPS65910_INT_STS_VMBHI_IT_SHIFT 1 589 #define TPS65910_INT_STS_VMBDCH_IT_MASK 0x01 590 #define TPS65910_INT_STS_VMBDCH_IT_SHIFT 0 591 592 #define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80 593 #define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7 594 #define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40 595 #define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6 596 #define TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK 0x20 597 #define TPS65910_INT_MSK_HOTDIE_IT_MSK_SHIFT 5 598 #define TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK 0x10 599 #define TPS65910_INT_MSK_PWRHOLD_IT_MSK_SHIFT 4 600 #define TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK 0x08 601 #define TPS65910_INT_MSK_PWRON_LP_IT_MSK_SHIFT 3 602 #define TPS65910_INT_MSK_PWRON_IT_MSK_MASK 0x04 603 #define TPS65910_INT_MSK_PWRON_IT_MSK_SHIFT 2 604 #define TPS65910_INT_MSK_VMBHI_IT_MSK_MASK 0x02 605 #define TPS65910_INT_MSK_VMBHI_IT_MSK_SHIFT 1 606 #define TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK 0x01 607 #define TPS65910_INT_MSK_VMBDCH_IT_MSK_SHIFT 0 608 609 #define TPS65910_INT_STS2_GPIO0_F_IT_SHIFT 2 610 #define TPS65910_INT_STS2_GPIO0_F_IT_MASK 0x02 611 #define TPS65910_INT_STS2_GPIO0_R_IT_SHIFT 1 612 #define TPS65910_INT_STS2_GPIO0_R_IT_MASK 0x01 613 614 #define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_SHIFT 2 615 #define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02 616 #define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_SHIFT 1 617 #define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01 618 619 /*Register INT_STS (0x80) register.RegisterDescription */ 620 #define INT_STS_RTC_PERIOD_IT_MASK 0x80 621 #define INT_STS_RTC_PERIOD_IT_SHIFT 7 622 #define INT_STS_RTC_ALARM_IT_MASK 0x40 623 #define INT_STS_RTC_ALARM_IT_SHIFT 6 624 #define INT_STS_HOTDIE_IT_MASK 0x20 625 #define INT_STS_HOTDIE_IT_SHIFT 5 626 #define INT_STS_PWRHOLD_R_IT_MASK 0x10 627 #define INT_STS_PWRHOLD_R_IT_SHIFT 4 628 #define INT_STS_PWRON_LP_IT_MASK 0x08 629 #define INT_STS_PWRON_LP_IT_SHIFT 3 630 #define INT_STS_PWRON_IT_MASK 0x04 631 #define INT_STS_PWRON_IT_SHIFT 2 632 #define INT_STS_VMBHI_IT_MASK 0x02 633 #define INT_STS_VMBHI_IT_SHIFT 1 634 #define INT_STS_PWRHOLD_F_IT_MASK 0x01 635 #define INT_STS_PWRHOLD_F_IT_SHIFT 0 636 637 638 /*Register INT_MSK (0x80) register.RegisterDescription */ 639 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80 640 #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7 641 #define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40 642 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6 643 #define INT_MSK_HOTDIE_IT_MSK_MASK 0x20 644 #define INT_MSK_HOTDIE_IT_MSK_SHIFT 5 645 #define INT_MSK_PWRHOLD_R_IT_MSK_MASK 0x10 646 #define INT_MSK_PWRHOLD_R_IT_MSK_SHIFT 4 647 #define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08 648 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3 649 #define INT_MSK_PWRON_IT_MSK_MASK 0x04 650 #define INT_MSK_PWRON_IT_MSK_SHIFT 2 651 #define INT_MSK_VMBHI_IT_MSK_MASK 0x02 652 #define INT_MSK_VMBHI_IT_MSK_SHIFT 1 653 #define INT_MSK_PWRHOLD_F_IT_MSK_MASK 0x01 654 #define INT_MSK_PWRHOLD_F_IT_MSK_SHIFT 0 655 656 657 /*Register INT_STS2 (0x80) register.RegisterDescription */ 658 #define INT_STS2_GPIO3_F_IT_MASK 0x80 659 #define INT_STS2_GPIO3_F_IT_SHIFT 7 660 #define INT_STS2_GPIO3_R_IT_MASK 0x40 661 #define INT_STS2_GPIO3_R_IT_SHIFT 6 662 #define INT_STS2_GPIO2_F_IT_MASK 0x20 663 #define INT_STS2_GPIO2_F_IT_SHIFT 5 664 #define INT_STS2_GPIO2_R_IT_MASK 0x10 665 #define INT_STS2_GPIO2_R_IT_SHIFT 4 666 #define INT_STS2_GPIO1_F_IT_MASK 0x08 667 #define INT_STS2_GPIO1_F_IT_SHIFT 3 668 #define INT_STS2_GPIO1_R_IT_MASK 0x04 669 #define INT_STS2_GPIO1_R_IT_SHIFT 2 670 #define INT_STS2_GPIO0_F_IT_MASK 0x02 671 #define INT_STS2_GPIO0_F_IT_SHIFT 1 672 #define INT_STS2_GPIO0_R_IT_MASK 0x01 673 #define INT_STS2_GPIO0_R_IT_SHIFT 0 674 675 676 /*Register INT_MSK2 (0x80) register.RegisterDescription */ 677 #define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80 678 #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7 679 #define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40 680 #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6 681 #define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20 682 #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5 683 #define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10 684 #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4 685 #define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08 686 #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3 687 #define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04 688 #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2 689 #define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02 690 #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1 691 #define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01 692 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0 693 694 695 /*Register INT_STS3 (0x80) register.RegisterDescription */ 696 #define INT_STS3_PWRDN_IT_MASK 0x80 697 #define INT_STS3_PWRDN_IT_SHIFT 7 698 #define INT_STS3_VMBCH2_L_IT_MASK 0x40 699 #define INT_STS3_VMBCH2_L_IT_SHIFT 6 700 #define INT_STS3_VMBCH2_H_IT_MASK 0x20 701 #define INT_STS3_VMBCH2_H_IT_SHIFT 5 702 #define INT_STS3_WTCHDG_IT_MASK 0x10 703 #define INT_STS3_WTCHDG_IT_SHIFT 4 704 #define INT_STS3_GPIO5_F_IT_MASK 0x08 705 #define INT_STS3_GPIO5_F_IT_SHIFT 3 706 #define INT_STS3_GPIO5_R_IT_MASK 0x04 707 #define INT_STS3_GPIO5_R_IT_SHIFT 2 708 #define INT_STS3_GPIO4_F_IT_MASK 0x02 709 #define INT_STS3_GPIO4_F_IT_SHIFT 1 710 #define INT_STS3_GPIO4_R_IT_MASK 0x01 711 #define INT_STS3_GPIO4_R_IT_SHIFT 0 712 713 714 /*Register INT_MSK3 (0x80) register.RegisterDescription */ 715 #define INT_MSK3_PWRDN_IT_MSK_MASK 0x80 716 #define INT_MSK3_PWRDN_IT_MSK_SHIFT 7 717 #define INT_MSK3_VMBCH2_L_IT_MSK_MASK 0x40 718 #define INT_MSK3_VMBCH2_L_IT_MSK_SHIFT 6 719 #define INT_MSK3_VMBCH2_H_IT_MSK_MASK 0x20 720 #define INT_MSK3_VMBCH2_H_IT_MSK_SHIFT 5 721 #define INT_MSK3_WTCHDG_IT_MSK_MASK 0x10 722 #define INT_MSK3_WTCHDG_IT_MSK_SHIFT 4 723 #define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08 724 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3 725 #define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04 726 #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2 727 #define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02 728 #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1 729 #define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01 730 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0 731 732 733 /*Register GPIO (0x80) register.RegisterDescription */ 734 #define GPIO_SLEEP_MASK 0x80 735 #define GPIO_SLEEP_SHIFT 7 736 #define GPIO_DEB_MASK 0x10 737 #define GPIO_DEB_SHIFT 4 738 #define GPIO_PUEN_MASK 0x08 739 #define GPIO_PUEN_SHIFT 3 740 #define GPIO_CFG_MASK 0x04 741 #define GPIO_CFG_SHIFT 2 742 #define GPIO_STS_MASK 0x02 743 #define GPIO_STS_SHIFT 1 744 #define GPIO_SET_MASK 0x01 745 #define GPIO_SET_SHIFT 0 746 747 748 /*Register JTAGVERNUM (0x80) register.RegisterDescription */ 749 #define JTAGVERNUM_VERNUM_MASK 0x0F 750 #define JTAGVERNUM_VERNUM_SHIFT 0 751 752 753 /* Register VDDCTRL (0x27) bit definitions */ 754 #define VDDCTRL_ST_MASK 0x03 755 #define VDDCTRL_ST_SHIFT 0 756 757 758 /*Register VDDCTRL_OP (0x28) bit definitios */ 759 #define VDDCTRL_OP_CMD_MASK 0x80 760 #define VDDCTRL_OP_CMD_SHIFT 7 761 #define VDDCTRL_OP_SEL_MASK 0x7F 762 #define VDDCTRL_OP_SEL_SHIFT 0 763 764 765 /*Register VDDCTRL_SR (0x29) bit definitions */ 766 #define VDDCTRL_SR_SEL_MASK 0x7F 767 #define VDDCTRL_SR_SEL_SHIFT 0 768 769 770 /* IRQ Definitions */ 771 #define TPS65910_IRQ_VBAT_VMBDCH 0 772 #define TPS65910_IRQ_VBAT_VMHI 1 773 #define TPS65910_IRQ_PWRON 2 774 #define TPS65910_IRQ_PWRON_LP 3 775 #define TPS65910_IRQ_PWRHOLD 4 776 #define TPS65910_IRQ_HOTDIE 5 777 #define TPS65910_IRQ_RTC_ALARM 6 778 #define TPS65910_IRQ_RTC_PERIOD 7 779 #define TPS65910_IRQ_GPIO_R 8 780 #define TPS65910_IRQ_GPIO_F 9 781 #define TPS65910_NUM_IRQ 10 782 783 #define TPS65911_IRQ_PWRHOLD_F 0 784 #define TPS65911_IRQ_VBAT_VMHI 1 785 #define TPS65911_IRQ_PWRON 2 786 #define TPS65911_IRQ_PWRON_LP 3 787 #define TPS65911_IRQ_PWRHOLD_R 4 788 #define TPS65911_IRQ_HOTDIE 5 789 #define TPS65911_IRQ_RTC_ALARM 6 790 #define TPS65911_IRQ_RTC_PERIOD 7 791 #define TPS65911_IRQ_GPIO0_R 8 792 #define TPS65911_IRQ_GPIO0_F 9 793 #define TPS65911_IRQ_GPIO1_R 10 794 #define TPS65911_IRQ_GPIO1_F 11 795 #define TPS65911_IRQ_GPIO2_R 12 796 #define TPS65911_IRQ_GPIO2_F 13 797 #define TPS65911_IRQ_GPIO3_R 14 798 #define TPS65911_IRQ_GPIO3_F 15 799 #define TPS65911_IRQ_GPIO4_R 16 800 #define TPS65911_IRQ_GPIO4_F 17 801 #define TPS65911_IRQ_GPIO5_R 18 802 #define TPS65911_IRQ_GPIO5_F 19 803 #define TPS65911_IRQ_WTCHDG 20 804 #define TPS65911_IRQ_VMBCH2_H 21 805 #define TPS65911_IRQ_VMBCH2_L 22 806 #define TPS65911_IRQ_PWRDN 23 807 808 #define TPS65911_NUM_IRQ 24 809 810 /* GPIO Register Definitions */ 811 #define TPS65910_GPIO_DEB BIT(2) 812 #define TPS65910_GPIO_PUEN BIT(3) 813 #define TPS65910_GPIO_CFG BIT(2) 814 #define TPS65910_GPIO_STS BIT(1) 815 #define TPS65910_GPIO_SET BIT(0) 816 817 /* Max number of TPS65910/11 GPIOs */ 818 #define TPS65910_NUM_GPIO 6 819 #define TPS65911_NUM_GPIO 9 820 #define TPS6591X_MAX_NUM_GPIO 9 821 822 /* Regulator Index Definitions */ 823 #define TPS65910_REG_VRTC 0 824 #define TPS65910_REG_VIO 1 825 #define TPS65910_REG_VDD1 2 826 #define TPS65910_REG_VDD2 3 827 #define TPS65910_REG_VDD3 4 828 #define TPS65910_REG_VDIG1 5 829 #define TPS65910_REG_VDIG2 6 830 #define TPS65910_REG_VPLL 7 831 #define TPS65910_REG_VDAC 8 832 #define TPS65910_REG_VAUX1 9 833 #define TPS65910_REG_VAUX2 10 834 #define TPS65910_REG_VAUX33 11 835 #define TPS65910_REG_VMMC 12 836 837 #define TPS65911_REG_VDDCTRL 4 838 #define TPS65911_REG_LDO1 5 839 #define TPS65911_REG_LDO2 6 840 #define TPS65911_REG_LDO3 7 841 #define TPS65911_REG_LDO4 8 842 #define TPS65911_REG_LDO5 9 843 #define TPS65911_REG_LDO6 10 844 #define TPS65911_REG_LDO7 11 845 #define TPS65911_REG_LDO8 12 846 847 /* Max number of TPS65910/11 regulators */ 848 #define TPS65910_NUM_REGS 13 849 850 /* External sleep controls through EN1/EN2/EN3/SLEEP inputs */ 851 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 0x1 852 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 0x2 853 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 0x4 854 #define TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP 0x8 855 856 /* 857 * Sleep keepon data: Maintains the state in sleep mode 858 * @therm_keepon: Keep on the thermal monitoring in sleep state. 859 * @clkout32k_keepon: Keep on the 32KHz clock output in sleep state. 860 * @i2chs_keepon: Keep on high speed internal clock in sleep state. 861 */ 862 struct tps65910_sleep_keepon_data { 863 unsigned therm_keepon:1; 864 unsigned clkout32k_keepon:1; 865 unsigned i2chs_keepon:1; 866 }; 867 868 /** 869 * struct tps65910_board 870 * Board platform data may be used to initialize regulators. 871 */ 872 873 struct tps65910_board { 874 int gpio_base; 875 int irq; 876 int irq_base; 877 int vmbch_threshold; 878 int vmbch2_threshold; 879 bool en_ck32k_xtal; 880 bool en_dev_slp; 881 bool pm_off; 882 struct tps65910_sleep_keepon_data *slp_keepon; 883 bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO]; 884 unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS]; 885 struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS]; 886 }; 887 888 /** 889 * struct tps65910 - tps65910 sub-driver chip access routines 890 */ 891 892 struct tps65910 { 893 struct device *dev; 894 struct i2c_client *i2c_client; 895 struct regmap *regmap; 896 unsigned int id; 897 898 /* Client devices */ 899 struct tps65910_pmic *pmic; 900 struct tps65910_rtc *rtc; 901 struct tps65910_power *power; 902 903 /* Device node parsed board data */ 904 struct tps65910_board *of_plat_data; 905 906 /* IRQ Handling */ 907 int chip_irq; 908 struct regmap_irq_chip_data *irq_data; 909 }; 910 911 struct tps65910_platform_data { 912 int irq; 913 int irq_base; 914 }; 915 916 static inline int tps65910_chip_id(struct tps65910 *tps65910) 917 { 918 return tps65910->id; 919 } 920 921 static inline int tps65910_reg_read(struct tps65910 *tps65910, u8 reg, 922 unsigned int *val) 923 { 924 return regmap_read(tps65910->regmap, reg, val); 925 } 926 927 static inline int tps65910_reg_write(struct tps65910 *tps65910, u8 reg, 928 unsigned int val) 929 { 930 return regmap_write(tps65910->regmap, reg, val); 931 } 932 933 static inline int tps65910_reg_set_bits(struct tps65910 *tps65910, u8 reg, 934 u8 mask) 935 { 936 return regmap_update_bits(tps65910->regmap, reg, mask, mask); 937 } 938 939 static inline int tps65910_reg_clear_bits(struct tps65910 *tps65910, u8 reg, 940 u8 mask) 941 { 942 return regmap_update_bits(tps65910->regmap, reg, mask, 0); 943 } 944 945 static inline int tps65910_reg_update_bits(struct tps65910 *tps65910, u8 reg, 946 u8 mask, u8 val) 947 { 948 return regmap_update_bits(tps65910->regmap, reg, mask, val); 949 } 950 951 static inline int tps65910_irq_get_virq(struct tps65910 *tps65910, int irq) 952 { 953 return regmap_irq_get_virq(tps65910->irq_data, irq); 954 } 955 956 #endif /* __LINUX_MFD_TPS65910_H */ 957