1 /* 2 * tps65910.h -- TI TPS6591x 3 * 4 * Copyright 2010-2011 Texas Instruments Inc. 5 * 6 * Author: Graeme Gregory <[email protected]> 7 * Author: Jorge Eduardo Candelaria <[email protected]> 8 * Author: Arnaud Deconinck <[email protected]> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 17 #ifndef __LINUX_MFD_TPS65910_H 18 #define __LINUX_MFD_TPS65910_H 19 20 #include <linux/gpio.h> 21 22 /* TPS chip id list */ 23 #define TPS65910 0 24 #define TPS65911 1 25 26 /* TPS regulator type list */ 27 #define REGULATOR_LDO 0 28 #define REGULATOR_DCDC 1 29 30 /* 31 * List of registers for component TPS65910 32 * 33 */ 34 35 #define TPS65910_SECONDS 0x0 36 #define TPS65910_MINUTES 0x1 37 #define TPS65910_HOURS 0x2 38 #define TPS65910_DAYS 0x3 39 #define TPS65910_MONTHS 0x4 40 #define TPS65910_YEARS 0x5 41 #define TPS65910_WEEKS 0x6 42 #define TPS65910_ALARM_SECONDS 0x8 43 #define TPS65910_ALARM_MINUTES 0x9 44 #define TPS65910_ALARM_HOURS 0xA 45 #define TPS65910_ALARM_DAYS 0xB 46 #define TPS65910_ALARM_MONTHS 0xC 47 #define TPS65910_ALARM_YEARS 0xD 48 #define TPS65910_RTC_CTRL 0x10 49 #define TPS65910_RTC_STATUS 0x11 50 #define TPS65910_RTC_INTERRUPTS 0x12 51 #define TPS65910_RTC_COMP_LSB 0x13 52 #define TPS65910_RTC_COMP_MSB 0x14 53 #define TPS65910_RTC_RES_PROG 0x15 54 #define TPS65910_RTC_RESET_STATUS 0x16 55 #define TPS65910_BCK1 0x17 56 #define TPS65910_BCK2 0x18 57 #define TPS65910_BCK3 0x19 58 #define TPS65910_BCK4 0x1A 59 #define TPS65910_BCK5 0x1B 60 #define TPS65910_PUADEN 0x1C 61 #define TPS65910_REF 0x1D 62 #define TPS65910_VRTC 0x1E 63 #define TPS65910_VIO 0x20 64 #define TPS65910_VDD1 0x21 65 #define TPS65910_VDD1_OP 0x22 66 #define TPS65910_VDD1_SR 0x23 67 #define TPS65910_VDD2 0x24 68 #define TPS65910_VDD2_OP 0x25 69 #define TPS65910_VDD2_SR 0x26 70 #define TPS65910_VDD3 0x27 71 #define TPS65910_VDIG1 0x30 72 #define TPS65910_VDIG2 0x31 73 #define TPS65910_VAUX1 0x32 74 #define TPS65910_VAUX2 0x33 75 #define TPS65910_VAUX33 0x34 76 #define TPS65910_VMMC 0x35 77 #define TPS65910_VPLL 0x36 78 #define TPS65910_VDAC 0x37 79 #define TPS65910_THERM 0x38 80 #define TPS65910_BBCH 0x39 81 #define TPS65910_DCDCCTRL 0x3E 82 #define TPS65910_DEVCTRL 0x3F 83 #define TPS65910_DEVCTRL2 0x40 84 #define TPS65910_SLEEP_KEEP_LDO_ON 0x41 85 #define TPS65910_SLEEP_KEEP_RES_ON 0x42 86 #define TPS65910_SLEEP_SET_LDO_OFF 0x43 87 #define TPS65910_SLEEP_SET_RES_OFF 0x44 88 #define TPS65910_EN1_LDO_ASS 0x45 89 #define TPS65910_EN1_SMPS_ASS 0x46 90 #define TPS65910_EN2_LDO_ASS 0x47 91 #define TPS65910_EN2_SMPS_ASS 0x48 92 #define TPS65910_EN3_LDO_ASS 0x49 93 #define TPS65910_SPARE 0x4A 94 #define TPS65910_INT_STS 0x50 95 #define TPS65910_INT_MSK 0x51 96 #define TPS65910_INT_STS2 0x52 97 #define TPS65910_INT_MSK2 0x53 98 #define TPS65910_INT_STS3 0x54 99 #define TPS65910_INT_MSK3 0x55 100 #define TPS65910_GPIO0 0x60 101 #define TPS65910_GPIO1 0x61 102 #define TPS65910_GPIO2 0x62 103 #define TPS65910_GPIO3 0x63 104 #define TPS65910_GPIO4 0x64 105 #define TPS65910_GPIO5 0x65 106 #define TPS65910_GPIO6 0x66 107 #define TPS65910_GPIO7 0x67 108 #define TPS65910_GPIO8 0x68 109 #define TPS65910_JTAGVERNUM 0x80 110 #define TPS65910_MAX_REGISTER 0x80 111 112 /* 113 * List of registers specific to TPS65911 114 */ 115 #define TPS65911_VDDCTRL 0x27 116 #define TPS65911_VDDCTRL_OP 0x28 117 #define TPS65911_VDDCTRL_SR 0x29 118 #define TPS65911_LDO1 0x30 119 #define TPS65911_LDO2 0x31 120 #define TPS65911_LDO5 0x32 121 #define TPS65911_LDO8 0x33 122 #define TPS65911_LDO7 0x34 123 #define TPS65911_LDO6 0x35 124 #define TPS65911_LDO4 0x36 125 #define TPS65911_LDO3 0x37 126 #define TPS65911_VMBCH 0x6A 127 #define TPS65911_VMBCH2 0x6B 128 129 /* 130 * List of register bitfields for component TPS65910 131 * 132 */ 133 134 135 /*Register BCK1 (0x80) register.RegisterDescription */ 136 #define BCK1_BCKUP_MASK 0xFF 137 #define BCK1_BCKUP_SHIFT 0 138 139 140 /*Register BCK2 (0x80) register.RegisterDescription */ 141 #define BCK2_BCKUP_MASK 0xFF 142 #define BCK2_BCKUP_SHIFT 0 143 144 145 /*Register BCK3 (0x80) register.RegisterDescription */ 146 #define BCK3_BCKUP_MASK 0xFF 147 #define BCK3_BCKUP_SHIFT 0 148 149 150 /*Register BCK4 (0x80) register.RegisterDescription */ 151 #define BCK4_BCKUP_MASK 0xFF 152 #define BCK4_BCKUP_SHIFT 0 153 154 155 /*Register BCK5 (0x80) register.RegisterDescription */ 156 #define BCK5_BCKUP_MASK 0xFF 157 #define BCK5_BCKUP_SHIFT 0 158 159 160 /*Register PUADEN (0x80) register.RegisterDescription */ 161 #define PUADEN_EN3P_MASK 0x80 162 #define PUADEN_EN3P_SHIFT 7 163 #define PUADEN_I2CCTLP_MASK 0x40 164 #define PUADEN_I2CCTLP_SHIFT 6 165 #define PUADEN_I2CSRP_MASK 0x20 166 #define PUADEN_I2CSRP_SHIFT 5 167 #define PUADEN_PWRONP_MASK 0x10 168 #define PUADEN_PWRONP_SHIFT 4 169 #define PUADEN_SLEEPP_MASK 0x08 170 #define PUADEN_SLEEPP_SHIFT 3 171 #define PUADEN_PWRHOLDP_MASK 0x04 172 #define PUADEN_PWRHOLDP_SHIFT 2 173 #define PUADEN_BOOT1P_MASK 0x02 174 #define PUADEN_BOOT1P_SHIFT 1 175 #define PUADEN_BOOT0P_MASK 0x01 176 #define PUADEN_BOOT0P_SHIFT 0 177 178 179 /*Register REF (0x80) register.RegisterDescription */ 180 #define REF_VMBCH_SEL_MASK 0x0C 181 #define REF_VMBCH_SEL_SHIFT 2 182 #define REF_ST_MASK 0x03 183 #define REF_ST_SHIFT 0 184 185 186 /*Register VRTC (0x80) register.RegisterDescription */ 187 #define VRTC_VRTC_OFFMASK_MASK 0x08 188 #define VRTC_VRTC_OFFMASK_SHIFT 3 189 #define VRTC_ST_MASK 0x03 190 #define VRTC_ST_SHIFT 0 191 192 193 /*Register VIO (0x80) register.RegisterDescription */ 194 #define VIO_ILMAX_MASK 0xC0 195 #define VIO_ILMAX_SHIFT 6 196 #define VIO_SEL_MASK 0x0C 197 #define VIO_SEL_SHIFT 2 198 #define VIO_ST_MASK 0x03 199 #define VIO_ST_SHIFT 0 200 201 202 /*Register VDD1 (0x80) register.RegisterDescription */ 203 #define VDD1_VGAIN_SEL_MASK 0xC0 204 #define VDD1_VGAIN_SEL_SHIFT 6 205 #define VDD1_ILMAX_MASK 0x20 206 #define VDD1_ILMAX_SHIFT 5 207 #define VDD1_TSTEP_MASK 0x1C 208 #define VDD1_TSTEP_SHIFT 2 209 #define VDD1_ST_MASK 0x03 210 #define VDD1_ST_SHIFT 0 211 212 213 /*Register VDD1_OP (0x80) register.RegisterDescription */ 214 #define VDD1_OP_CMD_MASK 0x80 215 #define VDD1_OP_CMD_SHIFT 7 216 #define VDD1_OP_SEL_MASK 0x7F 217 #define VDD1_OP_SEL_SHIFT 0 218 219 220 /*Register VDD1_SR (0x80) register.RegisterDescription */ 221 #define VDD1_SR_SEL_MASK 0x7F 222 #define VDD1_SR_SEL_SHIFT 0 223 224 225 /*Register VDD2 (0x80) register.RegisterDescription */ 226 #define VDD2_VGAIN_SEL_MASK 0xC0 227 #define VDD2_VGAIN_SEL_SHIFT 6 228 #define VDD2_ILMAX_MASK 0x20 229 #define VDD2_ILMAX_SHIFT 5 230 #define VDD2_TSTEP_MASK 0x1C 231 #define VDD2_TSTEP_SHIFT 2 232 #define VDD2_ST_MASK 0x03 233 #define VDD2_ST_SHIFT 0 234 235 236 /*Register VDD2_OP (0x80) register.RegisterDescription */ 237 #define VDD2_OP_CMD_MASK 0x80 238 #define VDD2_OP_CMD_SHIFT 7 239 #define VDD2_OP_SEL_MASK 0x7F 240 #define VDD2_OP_SEL_SHIFT 0 241 242 /*Register VDD2_SR (0x80) register.RegisterDescription */ 243 #define VDD2_SR_SEL_MASK 0x7F 244 #define VDD2_SR_SEL_SHIFT 0 245 246 247 /*Registers VDD1, VDD2 voltage values definitions */ 248 #define VDD1_2_NUM_VOLT_FINE 73 249 #define VDD1_2_NUM_VOLT_COARSE 3 250 #define VDD1_2_MIN_VOLT 6000 251 #define VDD1_2_OFFSET 125 252 253 254 /*Register VDD3 (0x80) register.RegisterDescription */ 255 #define VDD3_CKINEN_MASK 0x04 256 #define VDD3_CKINEN_SHIFT 2 257 #define VDD3_ST_MASK 0x03 258 #define VDD3_ST_SHIFT 0 259 #define VDDCTRL_MIN_VOLT 6000 260 #define VDDCTRL_OFFSET 125 261 262 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */ 263 #define LDO_SEL_MASK 0x0C 264 #define LDO_SEL_SHIFT 2 265 #define LDO_ST_MASK 0x03 266 #define LDO_ST_SHIFT 0 267 #define LDO_ST_ON_BIT 0x01 268 #define LDO_ST_MODE_BIT 0x02 269 270 271 /* Registers LDO1 to LDO8 in tps65910 */ 272 #define LDO1_SEL_MASK 0xFC 273 #define LDO3_SEL_MASK 0x7C 274 #define LDO_MIN_VOLT 1000 275 #define LDO_MAX_VOLT 3300 276 277 278 /*Register VDIG1 (0x80) register.RegisterDescription */ 279 #define VDIG1_SEL_MASK 0x0C 280 #define VDIG1_SEL_SHIFT 2 281 #define VDIG1_ST_MASK 0x03 282 #define VDIG1_ST_SHIFT 0 283 284 285 /*Register VDIG2 (0x80) register.RegisterDescription */ 286 #define VDIG2_SEL_MASK 0x0C 287 #define VDIG2_SEL_SHIFT 2 288 #define VDIG2_ST_MASK 0x03 289 #define VDIG2_ST_SHIFT 0 290 291 292 /*Register VAUX1 (0x80) register.RegisterDescription */ 293 #define VAUX1_SEL_MASK 0x0C 294 #define VAUX1_SEL_SHIFT 2 295 #define VAUX1_ST_MASK 0x03 296 #define VAUX1_ST_SHIFT 0 297 298 299 /*Register VAUX2 (0x80) register.RegisterDescription */ 300 #define VAUX2_SEL_MASK 0x0C 301 #define VAUX2_SEL_SHIFT 2 302 #define VAUX2_ST_MASK 0x03 303 #define VAUX2_ST_SHIFT 0 304 305 306 /*Register VAUX33 (0x80) register.RegisterDescription */ 307 #define VAUX33_SEL_MASK 0x0C 308 #define VAUX33_SEL_SHIFT 2 309 #define VAUX33_ST_MASK 0x03 310 #define VAUX33_ST_SHIFT 0 311 312 313 /*Register VMMC (0x80) register.RegisterDescription */ 314 #define VMMC_SEL_MASK 0x0C 315 #define VMMC_SEL_SHIFT 2 316 #define VMMC_ST_MASK 0x03 317 #define VMMC_ST_SHIFT 0 318 319 320 /*Register VPLL (0x80) register.RegisterDescription */ 321 #define VPLL_SEL_MASK 0x0C 322 #define VPLL_SEL_SHIFT 2 323 #define VPLL_ST_MASK 0x03 324 #define VPLL_ST_SHIFT 0 325 326 327 /*Register VDAC (0x80) register.RegisterDescription */ 328 #define VDAC_SEL_MASK 0x0C 329 #define VDAC_SEL_SHIFT 2 330 #define VDAC_ST_MASK 0x03 331 #define VDAC_ST_SHIFT 0 332 333 334 /*Register THERM (0x80) register.RegisterDescription */ 335 #define THERM_THERM_HD_MASK 0x20 336 #define THERM_THERM_HD_SHIFT 5 337 #define THERM_THERM_TS_MASK 0x10 338 #define THERM_THERM_TS_SHIFT 4 339 #define THERM_THERM_HDSEL_MASK 0x0C 340 #define THERM_THERM_HDSEL_SHIFT 2 341 #define THERM_RSVD1_MASK 0x02 342 #define THERM_RSVD1_SHIFT 1 343 #define THERM_THERM_STATE_MASK 0x01 344 #define THERM_THERM_STATE_SHIFT 0 345 346 347 /*Register BBCH (0x80) register.RegisterDescription */ 348 #define BBCH_BBSEL_MASK 0x06 349 #define BBCH_BBSEL_SHIFT 1 350 #define BBCH_BBCHEN_MASK 0x01 351 #define BBCH_BBCHEN_SHIFT 0 352 353 354 /*Register DCDCCTRL (0x80) register.RegisterDescription */ 355 #define DCDCCTRL_VDD2_PSKIP_MASK 0x20 356 #define DCDCCTRL_VDD2_PSKIP_SHIFT 5 357 #define DCDCCTRL_VDD1_PSKIP_MASK 0x10 358 #define DCDCCTRL_VDD1_PSKIP_SHIFT 4 359 #define DCDCCTRL_VIO_PSKIP_MASK 0x08 360 #define DCDCCTRL_VIO_PSKIP_SHIFT 3 361 #define DCDCCTRL_DCDCCKEXT_MASK 0x04 362 #define DCDCCTRL_DCDCCKEXT_SHIFT 2 363 #define DCDCCTRL_DCDCCKSYNC_MASK 0x03 364 #define DCDCCTRL_DCDCCKSYNC_SHIFT 0 365 366 367 /*Register DEVCTRL (0x80) register.RegisterDescription */ 368 #define DEVCTRL_RTC_PWDN_MASK 0x40 369 #define DEVCTRL_RTC_PWDN_SHIFT 6 370 #define DEVCTRL_CK32K_CTRL_MASK 0x20 371 #define DEVCTRL_CK32K_CTRL_SHIFT 5 372 #define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10 373 #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4 374 #define DEVCTRL_DEV_OFF_RST_MASK 0x08 375 #define DEVCTRL_DEV_OFF_RST_SHIFT 3 376 #define DEVCTRL_DEV_ON_MASK 0x04 377 #define DEVCTRL_DEV_ON_SHIFT 2 378 #define DEVCTRL_DEV_SLP_MASK 0x02 379 #define DEVCTRL_DEV_SLP_SHIFT 1 380 #define DEVCTRL_DEV_OFF_MASK 0x01 381 #define DEVCTRL_DEV_OFF_SHIFT 0 382 383 384 /*Register DEVCTRL2 (0x80) register.RegisterDescription */ 385 #define DEVCTRL2_TSLOT_LENGTH_MASK 0x30 386 #define DEVCTRL2_TSLOT_LENGTH_SHIFT 4 387 #define DEVCTRL2_SLEEPSIG_POL_MASK 0x08 388 #define DEVCTRL2_SLEEPSIG_POL_SHIFT 3 389 #define DEVCTRL2_PWON_LP_OFF_MASK 0x04 390 #define DEVCTRL2_PWON_LP_OFF_SHIFT 2 391 #define DEVCTRL2_PWON_LP_RST_MASK 0x02 392 #define DEVCTRL2_PWON_LP_RST_SHIFT 1 393 #define DEVCTRL2_IT_POL_MASK 0x01 394 #define DEVCTRL2_IT_POL_SHIFT 0 395 396 397 /*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */ 398 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80 399 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7 400 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40 401 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6 402 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20 403 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5 404 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10 405 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4 406 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08 407 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3 408 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04 409 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2 410 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02 411 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1 412 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01 413 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0 414 415 416 /*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */ 417 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80 418 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7 419 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40 420 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6 421 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20 422 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5 423 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10 424 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4 425 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08 426 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3 427 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04 428 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2 429 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02 430 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1 431 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01 432 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0 433 434 435 /*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */ 436 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80 437 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7 438 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40 439 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6 440 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20 441 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5 442 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10 443 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4 444 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08 445 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3 446 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04 447 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2 448 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02 449 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1 450 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01 451 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0 452 453 454 /*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */ 455 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80 456 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7 457 #define SLEEP_SET_RES_OFF_RSVD_MASK 0x60 458 #define SLEEP_SET_RES_OFF_RSVD_SHIFT 5 459 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10 460 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4 461 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08 462 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3 463 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04 464 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2 465 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02 466 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1 467 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01 468 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0 469 470 471 /*Register EN1_LDO_ASS (0x80) register.RegisterDescription */ 472 #define EN1_LDO_ASS_VDAC_EN1_MASK 0x80 473 #define EN1_LDO_ASS_VDAC_EN1_SHIFT 7 474 #define EN1_LDO_ASS_VPLL_EN1_MASK 0x40 475 #define EN1_LDO_ASS_VPLL_EN1_SHIFT 6 476 #define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20 477 #define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5 478 #define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10 479 #define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4 480 #define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08 481 #define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3 482 #define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04 483 #define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2 484 #define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02 485 #define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1 486 #define EN1_LDO_ASS_VMMC_EN1_MASK 0x01 487 #define EN1_LDO_ASS_VMMC_EN1_SHIFT 0 488 489 490 /*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */ 491 #define EN1_SMPS_ASS_RSVD_MASK 0xE0 492 #define EN1_SMPS_ASS_RSVD_SHIFT 5 493 #define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10 494 #define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4 495 #define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08 496 #define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3 497 #define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04 498 #define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2 499 #define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02 500 #define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1 501 #define EN1_SMPS_ASS_VIO_EN1_MASK 0x01 502 #define EN1_SMPS_ASS_VIO_EN1_SHIFT 0 503 504 505 /*Register EN2_LDO_ASS (0x80) register.RegisterDescription */ 506 #define EN2_LDO_ASS_VDAC_EN2_MASK 0x80 507 #define EN2_LDO_ASS_VDAC_EN2_SHIFT 7 508 #define EN2_LDO_ASS_VPLL_EN2_MASK 0x40 509 #define EN2_LDO_ASS_VPLL_EN2_SHIFT 6 510 #define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20 511 #define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5 512 #define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10 513 #define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4 514 #define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08 515 #define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3 516 #define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04 517 #define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2 518 #define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02 519 #define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1 520 #define EN2_LDO_ASS_VMMC_EN2_MASK 0x01 521 #define EN2_LDO_ASS_VMMC_EN2_SHIFT 0 522 523 524 /*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */ 525 #define EN2_SMPS_ASS_RSVD_MASK 0xE0 526 #define EN2_SMPS_ASS_RSVD_SHIFT 5 527 #define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10 528 #define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4 529 #define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08 530 #define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3 531 #define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04 532 #define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2 533 #define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02 534 #define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1 535 #define EN2_SMPS_ASS_VIO_EN2_MASK 0x01 536 #define EN2_SMPS_ASS_VIO_EN2_SHIFT 0 537 538 539 /*Register EN3_LDO_ASS (0x80) register.RegisterDescription */ 540 #define EN3_LDO_ASS_VDAC_EN3_MASK 0x80 541 #define EN3_LDO_ASS_VDAC_EN3_SHIFT 7 542 #define EN3_LDO_ASS_VPLL_EN3_MASK 0x40 543 #define EN3_LDO_ASS_VPLL_EN3_SHIFT 6 544 #define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20 545 #define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5 546 #define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10 547 #define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4 548 #define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08 549 #define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3 550 #define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04 551 #define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2 552 #define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02 553 #define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1 554 #define EN3_LDO_ASS_VMMC_EN3_MASK 0x01 555 #define EN3_LDO_ASS_VMMC_EN3_SHIFT 0 556 557 558 /*Register SPARE (0x80) register.RegisterDescription */ 559 #define SPARE_SPARE_MASK 0xFF 560 #define SPARE_SPARE_SHIFT 0 561 562 563 /*Register INT_STS (0x80) register.RegisterDescription */ 564 #define INT_STS_RTC_PERIOD_IT_MASK 0x80 565 #define INT_STS_RTC_PERIOD_IT_SHIFT 7 566 #define INT_STS_RTC_ALARM_IT_MASK 0x40 567 #define INT_STS_RTC_ALARM_IT_SHIFT 6 568 #define INT_STS_HOTDIE_IT_MASK 0x20 569 #define INT_STS_HOTDIE_IT_SHIFT 5 570 #define INT_STS_PWRHOLD_IT_MASK 0x10 571 #define INT_STS_PWRHOLD_IT_SHIFT 4 572 #define INT_STS_PWRON_LP_IT_MASK 0x08 573 #define INT_STS_PWRON_LP_IT_SHIFT 3 574 #define INT_STS_PWRON_IT_MASK 0x04 575 #define INT_STS_PWRON_IT_SHIFT 2 576 #define INT_STS_VMBHI_IT_MASK 0x02 577 #define INT_STS_VMBHI_IT_SHIFT 1 578 #define INT_STS_VMBDCH_IT_MASK 0x01 579 #define INT_STS_VMBDCH_IT_SHIFT 0 580 581 582 /*Register INT_MSK (0x80) register.RegisterDescription */ 583 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80 584 #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7 585 #define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40 586 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6 587 #define INT_MSK_HOTDIE_IT_MSK_MASK 0x20 588 #define INT_MSK_HOTDIE_IT_MSK_SHIFT 5 589 #define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10 590 #define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4 591 #define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08 592 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3 593 #define INT_MSK_PWRON_IT_MSK_MASK 0x04 594 #define INT_MSK_PWRON_IT_MSK_SHIFT 2 595 #define INT_MSK_VMBHI_IT_MSK_MASK 0x02 596 #define INT_MSK_VMBHI_IT_MSK_SHIFT 1 597 #define INT_MSK_VMBDCH_IT_MSK_MASK 0x01 598 #define INT_MSK_VMBDCH_IT_MSK_SHIFT 0 599 600 601 /*Register INT_STS2 (0x80) register.RegisterDescription */ 602 #define INT_STS2_GPIO3_F_IT_MASK 0x80 603 #define INT_STS2_GPIO3_F_IT_SHIFT 7 604 #define INT_STS2_GPIO3_R_IT_MASK 0x40 605 #define INT_STS2_GPIO3_R_IT_SHIFT 6 606 #define INT_STS2_GPIO2_F_IT_MASK 0x20 607 #define INT_STS2_GPIO2_F_IT_SHIFT 5 608 #define INT_STS2_GPIO2_R_IT_MASK 0x10 609 #define INT_STS2_GPIO2_R_IT_SHIFT 4 610 #define INT_STS2_GPIO1_F_IT_MASK 0x08 611 #define INT_STS2_GPIO1_F_IT_SHIFT 3 612 #define INT_STS2_GPIO1_R_IT_MASK 0x04 613 #define INT_STS2_GPIO1_R_IT_SHIFT 2 614 #define INT_STS2_GPIO0_F_IT_MASK 0x02 615 #define INT_STS2_GPIO0_F_IT_SHIFT 1 616 #define INT_STS2_GPIO0_R_IT_MASK 0x01 617 #define INT_STS2_GPIO0_R_IT_SHIFT 0 618 619 620 /*Register INT_MSK2 (0x80) register.RegisterDescription */ 621 #define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80 622 #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7 623 #define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40 624 #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6 625 #define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20 626 #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5 627 #define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10 628 #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4 629 #define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08 630 #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3 631 #define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04 632 #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2 633 #define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02 634 #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1 635 #define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01 636 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0 637 638 639 /*Register INT_STS3 (0x80) register.RegisterDescription */ 640 #define INT_STS3_GPIO5_F_IT_MASK 0x08 641 #define INT_STS3_GPIO5_F_IT_SHIFT 3 642 #define INT_STS3_GPIO5_R_IT_MASK 0x04 643 #define INT_STS3_GPIO5_R_IT_SHIFT 2 644 #define INT_STS3_GPIO4_F_IT_MASK 0x02 645 #define INT_STS3_GPIO4_F_IT_SHIFT 1 646 #define INT_STS3_GPIO4_R_IT_MASK 0x01 647 #define INT_STS3_GPIO4_R_IT_SHIFT 0 648 649 650 /*Register INT_MSK3 (0x80) register.RegisterDescription */ 651 #define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08 652 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3 653 #define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04 654 #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2 655 #define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02 656 #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1 657 #define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01 658 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0 659 660 661 /*Register GPIO (0x80) register.RegisterDescription */ 662 #define GPIO_DEB_MASK 0x10 663 #define GPIO_DEB_SHIFT 4 664 #define GPIO_PUEN_MASK 0x08 665 #define GPIO_PUEN_SHIFT 3 666 #define GPIO_CFG_MASK 0x04 667 #define GPIO_CFG_SHIFT 2 668 #define GPIO_STS_MASK 0x02 669 #define GPIO_STS_SHIFT 1 670 #define GPIO_SET_MASK 0x01 671 #define GPIO_SET_SHIFT 0 672 673 674 /*Register JTAGVERNUM (0x80) register.RegisterDescription */ 675 #define JTAGVERNUM_VERNUM_MASK 0x0F 676 #define JTAGVERNUM_VERNUM_SHIFT 0 677 678 679 /* Register VDDCTRL (0x27) bit definitions */ 680 #define VDDCTRL_ST_MASK 0x03 681 #define VDDCTRL_ST_SHIFT 0 682 683 684 /*Register VDDCTRL_OP (0x28) bit definitios */ 685 #define VDDCTRL_OP_CMD_MASK 0x80 686 #define VDDCTRL_OP_CMD_SHIFT 7 687 #define VDDCTRL_OP_SEL_MASK 0x7F 688 #define VDDCTRL_OP_SEL_SHIFT 0 689 690 691 /*Register VDDCTRL_SR (0x29) bit definitions */ 692 #define VDDCTRL_SR_SEL_MASK 0x7F 693 #define VDDCTRL_SR_SEL_SHIFT 0 694 695 696 /* IRQ Definitions */ 697 #define TPS65910_IRQ_VBAT_VMBDCH 0 698 #define TPS65910_IRQ_VBAT_VMHI 1 699 #define TPS65910_IRQ_PWRON 2 700 #define TPS65910_IRQ_PWRON_LP 3 701 #define TPS65910_IRQ_PWRHOLD 4 702 #define TPS65910_IRQ_HOTDIE 5 703 #define TPS65910_IRQ_RTC_ALARM 6 704 #define TPS65910_IRQ_RTC_PERIOD 7 705 #define TPS65910_IRQ_GPIO_R 8 706 #define TPS65910_IRQ_GPIO_F 9 707 #define TPS65910_NUM_IRQ 10 708 709 #define TPS65911_IRQ_VBAT_VMBDCH 0 710 #define TPS65911_IRQ_VBAT_VMBDCH2L 1 711 #define TPS65911_IRQ_VBAT_VMBDCH2H 2 712 #define TPS65911_IRQ_VBAT_VMHI 3 713 #define TPS65911_IRQ_PWRON 4 714 #define TPS65911_IRQ_PWRON_LP 5 715 #define TPS65911_IRQ_PWRHOLD_F 6 716 #define TPS65911_IRQ_PWRHOLD_R 7 717 #define TPS65911_IRQ_HOTDIE 8 718 #define TPS65911_IRQ_RTC_ALARM 9 719 #define TPS65911_IRQ_RTC_PERIOD 10 720 #define TPS65911_IRQ_GPIO0_R 11 721 #define TPS65911_IRQ_GPIO0_F 12 722 #define TPS65911_IRQ_GPIO1_R 13 723 #define TPS65911_IRQ_GPIO1_F 14 724 #define TPS65911_IRQ_GPIO2_R 15 725 #define TPS65911_IRQ_GPIO2_F 16 726 #define TPS65911_IRQ_GPIO3_R 17 727 #define TPS65911_IRQ_GPIO3_F 18 728 #define TPS65911_IRQ_GPIO4_R 19 729 #define TPS65911_IRQ_GPIO4_F 20 730 #define TPS65911_IRQ_GPIO5_R 21 731 #define TPS65911_IRQ_GPIO5_F 22 732 #define TPS65911_IRQ_WTCHDG 23 733 #define TPS65911_IRQ_PWRDN 24 734 735 #define TPS65911_NUM_IRQ 25 736 737 738 /* GPIO Register Definitions */ 739 #define TPS65910_GPIO_DEB BIT(2) 740 #define TPS65910_GPIO_PUEN BIT(3) 741 #define TPS65910_GPIO_CFG BIT(2) 742 #define TPS65910_GPIO_STS BIT(1) 743 #define TPS65910_GPIO_SET BIT(0) 744 745 /* Regulator Index Definitions */ 746 #define TPS65910_REG_VRTC 0 747 #define TPS65910_REG_VIO 1 748 #define TPS65910_REG_VDD1 2 749 #define TPS65910_REG_VDD2 3 750 #define TPS65910_REG_VDD3 4 751 #define TPS65910_REG_VDIG1 5 752 #define TPS65910_REG_VDIG2 6 753 #define TPS65910_REG_VPLL 7 754 #define TPS65910_REG_VDAC 8 755 #define TPS65910_REG_VAUX1 9 756 #define TPS65910_REG_VAUX2 10 757 #define TPS65910_REG_VAUX33 11 758 #define TPS65910_REG_VMMC 12 759 760 #define TPS65911_REG_VDDCTRL 4 761 #define TPS65911_REG_LDO1 5 762 #define TPS65911_REG_LDO2 6 763 #define TPS65911_REG_LDO3 7 764 #define TPS65911_REG_LDO4 8 765 #define TPS65911_REG_LDO5 9 766 #define TPS65911_REG_LDO6 10 767 #define TPS65911_REG_LDO7 11 768 #define TPS65911_REG_LDO8 12 769 770 /* Max number of TPS65910/11 regulators */ 771 #define TPS65910_NUM_REGS 13 772 773 /** 774 * struct tps65910_board 775 * Board platform data may be used to initialize regulators. 776 */ 777 778 struct tps65910_board { 779 int gpio_base; 780 int irq; 781 int irq_base; 782 int vmbch_threshold; 783 int vmbch2_threshold; 784 struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS]; 785 }; 786 787 /** 788 * struct tps65910 - tps65910 sub-driver chip access routines 789 */ 790 791 struct tps65910 { 792 struct device *dev; 793 struct i2c_client *i2c_client; 794 struct regmap *regmap; 795 struct mutex io_mutex; 796 unsigned int id; 797 int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest); 798 int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src); 799 800 /* Client devices */ 801 struct tps65910_pmic *pmic; 802 struct tps65910_rtc *rtc; 803 struct tps65910_power *power; 804 805 /* GPIO Handling */ 806 struct gpio_chip gpio; 807 808 /* IRQ Handling */ 809 struct mutex irq_lock; 810 int chip_irq; 811 int irq_base; 812 int irq_num; 813 u32 irq_mask; 814 }; 815 816 struct tps65910_platform_data { 817 int irq; 818 int irq_base; 819 }; 820 821 int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask); 822 int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask); 823 void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base); 824 int tps65910_irq_init(struct tps65910 *tps65910, int irq, 825 struct tps65910_platform_data *pdata); 826 int tps65910_irq_exit(struct tps65910 *tps65910); 827 828 static inline int tps65910_chip_id(struct tps65910 *tps65910) 829 { 830 return tps65910->id; 831 } 832 833 #endif /* __LINUX_MFD_TPS65910_H */ 834