1 /* 2 * Copyright (C) STMicroelectronics 2016 3 * 4 * Author: Benjamin Gaignard <[email protected]> 5 * 6 * License terms: GNU General Public License (GPL), version 2 7 */ 8 9 #ifndef _LINUX_STM32_GPTIMER_H_ 10 #define _LINUX_STM32_GPTIMER_H_ 11 12 #include <linux/clk.h> 13 #include <linux/regmap.h> 14 15 #define TIM_CR1 0x00 /* Control Register 1 */ 16 #define TIM_CR2 0x04 /* Control Register 2 */ 17 #define TIM_SMCR 0x08 /* Slave mode control reg */ 18 #define TIM_DIER 0x0C /* DMA/interrupt register */ 19 #define TIM_SR 0x10 /* Status register */ 20 #define TIM_EGR 0x14 /* Event Generation Reg */ 21 #define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */ 22 #define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */ 23 #define TIM_CCER 0x20 /* Capt/Comp Enable Reg */ 24 #define TIM_PSC 0x28 /* Prescaler */ 25 #define TIM_ARR 0x2c /* Auto-Reload Register */ 26 #define TIM_CCR1 0x34 /* Capt/Comp Register 1 */ 27 #define TIM_CCR2 0x38 /* Capt/Comp Register 2 */ 28 #define TIM_CCR3 0x3C /* Capt/Comp Register 3 */ 29 #define TIM_CCR4 0x40 /* Capt/Comp Register 4 */ 30 #define TIM_BDTR 0x44 /* Break and Dead-Time Reg */ 31 32 #define TIM_CR1_CEN BIT(0) /* Counter Enable */ 33 #define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */ 34 #define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */ 35 #define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */ 36 #define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */ 37 #define TIM_DIER_UIE BIT(0) /* Update interrupt */ 38 #define TIM_SR_UIF BIT(0) /* Update interrupt flag */ 39 #define TIM_EGR_UG BIT(0) /* Update Generation */ 40 #define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */ 41 #define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ 42 #define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */ 43 #define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */ 44 #define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */ 45 #define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ 46 #define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */ 47 #define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */ 48 #define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */ 49 #define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) 50 #define TIM_BDTR_BKE BIT(12) /* Break input enable */ 51 #define TIM_BDTR_BKP BIT(13) /* Break input polarity */ 52 #define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */ 53 #define TIM_BDTR_MOE BIT(15) /* Main Output Enable */ 54 #define TIM_BDTR_BKF (BIT(16) | BIT(17) | BIT(18) | BIT(19)) 55 #define TIM_BDTR_BK2F (BIT(20) | BIT(21) | BIT(22) | BIT(23)) 56 #define TIM_BDTR_BK2E BIT(24) /* Break 2 input enable */ 57 #define TIM_BDTR_BK2P BIT(25) /* Break 2 input polarity */ 58 59 #define MAX_TIM_PSC 0xFFFF 60 #define TIM_CR2_MMS_SHIFT 4 61 #define TIM_SMCR_TS_SHIFT 4 62 #define TIM_BDTR_BKF_MASK 0xF 63 #define TIM_BDTR_BKF_SHIFT 16 64 #define TIM_BDTR_BK2F_SHIFT 20 65 66 struct stm32_timers { 67 struct clk *clk; 68 struct regmap *regmap; 69 u32 max_arr; 70 }; 71 #endif 72