1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * core.h -- Core driver for NXP PCF50633 4 * 5 * (C) 2006-2008 by Openmoko, Inc. 6 * All rights reserved. 7 */ 8 9 #ifndef __LINUX_MFD_PCF50633_CORE_H 10 #define __LINUX_MFD_PCF50633_CORE_H 11 12 #include <linux/i2c.h> 13 #include <linux/workqueue.h> 14 #include <linux/regulator/driver.h> 15 #include <linux/regulator/machine.h> 16 #include <linux/pm.h> 17 #include <linux/power_supply.h> 18 19 struct pcf50633; 20 struct regmap; 21 22 #define PCF50633_NUM_REGULATORS 11 23 24 struct pcf50633_platform_data { 25 struct regulator_init_data reg_init_data[PCF50633_NUM_REGULATORS]; 26 27 char **batteries; 28 int num_batteries; 29 30 /* 31 * Should be set accordingly to the reference resistor used, see 32 * I_{ch(ref)} charger reference current in the pcf50633 User 33 * Manual. 34 */ 35 int charger_reference_current_ma; 36 37 /* Callbacks */ 38 void (*probe_done)(struct pcf50633 *); 39 void (*mbc_event_callback)(struct pcf50633 *, int); 40 void (*regulator_registered)(struct pcf50633 *, int); 41 void (*force_shutdown)(struct pcf50633 *); 42 43 u8 resumers[5]; 44 }; 45 46 struct pcf50633_irq { 47 void (*handler) (int, void *); 48 void *data; 49 }; 50 51 int pcf50633_register_irq(struct pcf50633 *pcf, int irq, 52 void (*handler) (int, void *), void *data); 53 int pcf50633_free_irq(struct pcf50633 *pcf, int irq); 54 55 int pcf50633_irq_mask(struct pcf50633 *pcf, int irq); 56 int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq); 57 int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq); 58 59 int pcf50633_read_block(struct pcf50633 *, u8 reg, 60 int nr_regs, u8 *data); 61 int pcf50633_write_block(struct pcf50633 *pcf, u8 reg, 62 int nr_regs, u8 *data); 63 u8 pcf50633_reg_read(struct pcf50633 *, u8 reg); 64 int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val); 65 66 int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val); 67 int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits); 68 69 /* Interrupt registers */ 70 71 #define PCF50633_REG_INT1 0x02 72 #define PCF50633_REG_INT2 0x03 73 #define PCF50633_REG_INT3 0x04 74 #define PCF50633_REG_INT4 0x05 75 #define PCF50633_REG_INT5 0x06 76 77 #define PCF50633_REG_INT1M 0x07 78 #define PCF50633_REG_INT2M 0x08 79 #define PCF50633_REG_INT3M 0x09 80 #define PCF50633_REG_INT4M 0x0a 81 #define PCF50633_REG_INT5M 0x0b 82 83 enum { 84 /* Chip IRQs */ 85 PCF50633_IRQ_ADPINS, 86 PCF50633_IRQ_ADPREM, 87 PCF50633_IRQ_USBINS, 88 PCF50633_IRQ_USBREM, 89 PCF50633_IRQ_RESERVED1, 90 PCF50633_IRQ_RESERVED2, 91 PCF50633_IRQ_ALARM, 92 PCF50633_IRQ_SECOND, 93 PCF50633_IRQ_ONKEYR, 94 PCF50633_IRQ_ONKEYF, 95 PCF50633_IRQ_EXTON1R, 96 PCF50633_IRQ_EXTON1F, 97 PCF50633_IRQ_EXTON2R, 98 PCF50633_IRQ_EXTON2F, 99 PCF50633_IRQ_EXTON3R, 100 PCF50633_IRQ_EXTON3F, 101 PCF50633_IRQ_BATFULL, 102 PCF50633_IRQ_CHGHALT, 103 PCF50633_IRQ_THLIMON, 104 PCF50633_IRQ_THLIMOFF, 105 PCF50633_IRQ_USBLIMON, 106 PCF50633_IRQ_USBLIMOFF, 107 PCF50633_IRQ_ADCRDY, 108 PCF50633_IRQ_ONKEY1S, 109 PCF50633_IRQ_LOWSYS, 110 PCF50633_IRQ_LOWBAT, 111 PCF50633_IRQ_HIGHTMP, 112 PCF50633_IRQ_AUTOPWRFAIL, 113 PCF50633_IRQ_DWN1PWRFAIL, 114 PCF50633_IRQ_DWN2PWRFAIL, 115 PCF50633_IRQ_LEDPWRFAIL, 116 PCF50633_IRQ_LEDOVP, 117 PCF50633_IRQ_LDO1PWRFAIL, 118 PCF50633_IRQ_LDO2PWRFAIL, 119 PCF50633_IRQ_LDO3PWRFAIL, 120 PCF50633_IRQ_LDO4PWRFAIL, 121 PCF50633_IRQ_LDO5PWRFAIL, 122 PCF50633_IRQ_LDO6PWRFAIL, 123 PCF50633_IRQ_HCLDOPWRFAIL, 124 PCF50633_IRQ_HCLDOOVL, 125 126 /* Always last */ 127 PCF50633_NUM_IRQ, 128 }; 129 130 struct pcf50633 { 131 struct device *dev; 132 struct regmap *regmap; 133 134 struct pcf50633_platform_data *pdata; 135 int irq; 136 struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ]; 137 struct work_struct irq_work; 138 struct workqueue_struct *work_queue; 139 struct mutex lock; 140 141 u8 mask_regs[5]; 142 143 u8 suspend_irq_masks[5]; 144 u8 resume_reason[5]; 145 int is_suspended; 146 147 int onkey1s_held; 148 149 struct platform_device *rtc_pdev; 150 struct platform_device *mbc_pdev; 151 struct platform_device *adc_pdev; 152 struct platform_device *input_pdev; 153 struct platform_device *bl_pdev; 154 struct platform_device *regulator_pdev[PCF50633_NUM_REGULATORS]; 155 }; 156 157 enum pcf50633_reg_int1 { 158 PCF50633_INT1_ADPINS = 0x01, /* Adapter inserted */ 159 PCF50633_INT1_ADPREM = 0x02, /* Adapter removed */ 160 PCF50633_INT1_USBINS = 0x04, /* USB inserted */ 161 PCF50633_INT1_USBREM = 0x08, /* USB removed */ 162 /* reserved */ 163 PCF50633_INT1_ALARM = 0x40, /* RTC alarm time is reached */ 164 PCF50633_INT1_SECOND = 0x80, /* RTC periodic second interrupt */ 165 }; 166 167 enum pcf50633_reg_int2 { 168 PCF50633_INT2_ONKEYR = 0x01, /* ONKEY rising edge */ 169 PCF50633_INT2_ONKEYF = 0x02, /* ONKEY falling edge */ 170 PCF50633_INT2_EXTON1R = 0x04, /* EXTON1 rising edge */ 171 PCF50633_INT2_EXTON1F = 0x08, /* EXTON1 falling edge */ 172 PCF50633_INT2_EXTON2R = 0x10, /* EXTON2 rising edge */ 173 PCF50633_INT2_EXTON2F = 0x20, /* EXTON2 falling edge */ 174 PCF50633_INT2_EXTON3R = 0x40, /* EXTON3 rising edge */ 175 PCF50633_INT2_EXTON3F = 0x80, /* EXTON3 falling edge */ 176 }; 177 178 enum pcf50633_reg_int3 { 179 PCF50633_INT3_BATFULL = 0x01, /* Battery full */ 180 PCF50633_INT3_CHGHALT = 0x02, /* Charger halt */ 181 PCF50633_INT3_THLIMON = 0x04, 182 PCF50633_INT3_THLIMOFF = 0x08, 183 PCF50633_INT3_USBLIMON = 0x10, 184 PCF50633_INT3_USBLIMOFF = 0x20, 185 PCF50633_INT3_ADCRDY = 0x40, /* ADC result ready */ 186 PCF50633_INT3_ONKEY1S = 0x80, /* ONKEY pressed 1 second */ 187 }; 188 189 enum pcf50633_reg_int4 { 190 PCF50633_INT4_LOWSYS = 0x01, 191 PCF50633_INT4_LOWBAT = 0x02, 192 PCF50633_INT4_HIGHTMP = 0x04, 193 PCF50633_INT4_AUTOPWRFAIL = 0x08, 194 PCF50633_INT4_DWN1PWRFAIL = 0x10, 195 PCF50633_INT4_DWN2PWRFAIL = 0x20, 196 PCF50633_INT4_LEDPWRFAIL = 0x40, 197 PCF50633_INT4_LEDOVP = 0x80, 198 }; 199 200 enum pcf50633_reg_int5 { 201 PCF50633_INT5_LDO1PWRFAIL = 0x01, 202 PCF50633_INT5_LDO2PWRFAIL = 0x02, 203 PCF50633_INT5_LDO3PWRFAIL = 0x04, 204 PCF50633_INT5_LDO4PWRFAIL = 0x08, 205 PCF50633_INT5_LDO5PWRFAIL = 0x10, 206 PCF50633_INT5_LDO6PWRFAIL = 0x20, 207 PCF50633_INT5_HCLDOPWRFAIL = 0x40, 208 PCF50633_INT5_HCLDOOVL = 0x80, 209 }; 210 211 /* misc. registers */ 212 #define PCF50633_REG_OOCSHDWN 0x0c 213 214 /* LED registers */ 215 #define PCF50633_REG_LEDOUT 0x28 216 #define PCF50633_REG_LEDENA 0x29 217 #define PCF50633_REG_LEDCTL 0x2a 218 #define PCF50633_REG_LEDDIM 0x2b 219 220 static inline struct pcf50633 *dev_to_pcf50633(struct device *dev) 221 { 222 return dev_get_drvdata(dev); 223 } 224 225 int pcf50633_irq_init(struct pcf50633 *pcf, int irq); 226 void pcf50633_irq_free(struct pcf50633 *pcf); 227 extern const struct dev_pm_ops pcf50633_pm; 228 229 #endif 230