1 /* 2 * core.h -- Core driver for NXP PCF50633 3 * 4 * (C) 2006-2008 by Openmoko, Inc. 5 * All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #ifndef __LINUX_MFD_PCF50633_CORE_H 14 #define __LINUX_MFD_PCF50633_CORE_H 15 16 #include <linux/i2c.h> 17 #include <linux/workqueue.h> 18 #include <linux/regulator/driver.h> 19 #include <linux/regulator/machine.h> 20 #include <linux/power_supply.h> 21 22 struct pcf50633; 23 24 #define PCF50633_NUM_REGULATORS 11 25 26 struct pcf50633_platform_data { 27 struct regulator_init_data reg_init_data[PCF50633_NUM_REGULATORS]; 28 29 char **batteries; 30 int num_batteries; 31 32 int charging_restart_interval; 33 34 /* 35 * Should be set accordingly to the reference resistor used, see 36 * I_{ch(ref)} charger reference current in the pcf50633 User 37 * Manual. 38 */ 39 int charger_reference_current_ma; 40 41 /* Callbacks */ 42 void (*probe_done)(struct pcf50633 *); 43 void (*mbc_event_callback)(struct pcf50633 *, int); 44 void (*regulator_registered)(struct pcf50633 *, int); 45 void (*force_shutdown)(struct pcf50633 *); 46 47 u8 resumers[5]; 48 }; 49 50 struct pcf50633_subdev_pdata { 51 struct pcf50633 *pcf; 52 }; 53 54 struct pcf50633_irq { 55 void (*handler) (int, void *); 56 void *data; 57 }; 58 59 int pcf50633_register_irq(struct pcf50633 *pcf, int irq, 60 void (*handler) (int, void *), void *data); 61 int pcf50633_free_irq(struct pcf50633 *pcf, int irq); 62 63 int pcf50633_irq_mask(struct pcf50633 *pcf, int irq); 64 int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq); 65 int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq); 66 67 int pcf50633_read_block(struct pcf50633 *, u8 reg, 68 int nr_regs, u8 *data); 69 int pcf50633_write_block(struct pcf50633 *pcf, u8 reg, 70 int nr_regs, u8 *data); 71 u8 pcf50633_reg_read(struct pcf50633 *, u8 reg); 72 int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val); 73 74 int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val); 75 int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits); 76 77 /* Interrupt registers */ 78 79 #define PCF50633_REG_INT1 0x02 80 #define PCF50633_REG_INT2 0x03 81 #define PCF50633_REG_INT3 0x04 82 #define PCF50633_REG_INT4 0x05 83 #define PCF50633_REG_INT5 0x06 84 85 #define PCF50633_REG_INT1M 0x07 86 #define PCF50633_REG_INT2M 0x08 87 #define PCF50633_REG_INT3M 0x09 88 #define PCF50633_REG_INT4M 0x0a 89 #define PCF50633_REG_INT5M 0x0b 90 91 enum { 92 /* Chip IRQs */ 93 PCF50633_IRQ_ADPINS, 94 PCF50633_IRQ_ADPREM, 95 PCF50633_IRQ_USBINS, 96 PCF50633_IRQ_USBREM, 97 PCF50633_IRQ_RESERVED1, 98 PCF50633_IRQ_RESERVED2, 99 PCF50633_IRQ_ALARM, 100 PCF50633_IRQ_SECOND, 101 PCF50633_IRQ_ONKEYR, 102 PCF50633_IRQ_ONKEYF, 103 PCF50633_IRQ_EXTON1R, 104 PCF50633_IRQ_EXTON1F, 105 PCF50633_IRQ_EXTON2R, 106 PCF50633_IRQ_EXTON2F, 107 PCF50633_IRQ_EXTON3R, 108 PCF50633_IRQ_EXTON3F, 109 PCF50633_IRQ_BATFULL, 110 PCF50633_IRQ_CHGHALT, 111 PCF50633_IRQ_THLIMON, 112 PCF50633_IRQ_THLIMOFF, 113 PCF50633_IRQ_USBLIMON, 114 PCF50633_IRQ_USBLIMOFF, 115 PCF50633_IRQ_ADCRDY, 116 PCF50633_IRQ_ONKEY1S, 117 PCF50633_IRQ_LOWSYS, 118 PCF50633_IRQ_LOWBAT, 119 PCF50633_IRQ_HIGHTMP, 120 PCF50633_IRQ_AUTOPWRFAIL, 121 PCF50633_IRQ_DWN1PWRFAIL, 122 PCF50633_IRQ_DWN2PWRFAIL, 123 PCF50633_IRQ_LEDPWRFAIL, 124 PCF50633_IRQ_LEDOVP, 125 PCF50633_IRQ_LDO1PWRFAIL, 126 PCF50633_IRQ_LDO2PWRFAIL, 127 PCF50633_IRQ_LDO3PWRFAIL, 128 PCF50633_IRQ_LDO4PWRFAIL, 129 PCF50633_IRQ_LDO5PWRFAIL, 130 PCF50633_IRQ_LDO6PWRFAIL, 131 PCF50633_IRQ_HCLDOPWRFAIL, 132 PCF50633_IRQ_HCLDOOVL, 133 134 /* Always last */ 135 PCF50633_NUM_IRQ, 136 }; 137 138 struct pcf50633 { 139 struct device *dev; 140 struct i2c_client *i2c_client; 141 142 struct pcf50633_platform_data *pdata; 143 int irq; 144 struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ]; 145 struct work_struct irq_work; 146 struct workqueue_struct *work_queue; 147 struct mutex lock; 148 149 u8 mask_regs[5]; 150 151 u8 suspend_irq_masks[5]; 152 u8 resume_reason[5]; 153 int is_suspended; 154 155 int onkey1s_held; 156 157 struct platform_device *rtc_pdev; 158 struct platform_device *mbc_pdev; 159 struct platform_device *adc_pdev; 160 struct platform_device *input_pdev; 161 struct platform_device *regulator_pdev[PCF50633_NUM_REGULATORS]; 162 }; 163 164 enum pcf50633_reg_int1 { 165 PCF50633_INT1_ADPINS = 0x01, /* Adapter inserted */ 166 PCF50633_INT1_ADPREM = 0x02, /* Adapter removed */ 167 PCF50633_INT1_USBINS = 0x04, /* USB inserted */ 168 PCF50633_INT1_USBREM = 0x08, /* USB removed */ 169 /* reserved */ 170 PCF50633_INT1_ALARM = 0x40, /* RTC alarm time is reached */ 171 PCF50633_INT1_SECOND = 0x80, /* RTC periodic second interrupt */ 172 }; 173 174 enum pcf50633_reg_int2 { 175 PCF50633_INT2_ONKEYR = 0x01, /* ONKEY rising edge */ 176 PCF50633_INT2_ONKEYF = 0x02, /* ONKEY falling edge */ 177 PCF50633_INT2_EXTON1R = 0x04, /* EXTON1 rising edge */ 178 PCF50633_INT2_EXTON1F = 0x08, /* EXTON1 falling edge */ 179 PCF50633_INT2_EXTON2R = 0x10, /* EXTON2 rising edge */ 180 PCF50633_INT2_EXTON2F = 0x20, /* EXTON2 falling edge */ 181 PCF50633_INT2_EXTON3R = 0x40, /* EXTON3 rising edge */ 182 PCF50633_INT2_EXTON3F = 0x80, /* EXTON3 falling edge */ 183 }; 184 185 enum pcf50633_reg_int3 { 186 PCF50633_INT3_BATFULL = 0x01, /* Battery full */ 187 PCF50633_INT3_CHGHALT = 0x02, /* Charger halt */ 188 PCF50633_INT3_THLIMON = 0x04, 189 PCF50633_INT3_THLIMOFF = 0x08, 190 PCF50633_INT3_USBLIMON = 0x10, 191 PCF50633_INT3_USBLIMOFF = 0x20, 192 PCF50633_INT3_ADCRDY = 0x40, /* ADC result ready */ 193 PCF50633_INT3_ONKEY1S = 0x80, /* ONKEY pressed 1 second */ 194 }; 195 196 enum pcf50633_reg_int4 { 197 PCF50633_INT4_LOWSYS = 0x01, 198 PCF50633_INT4_LOWBAT = 0x02, 199 PCF50633_INT4_HIGHTMP = 0x04, 200 PCF50633_INT4_AUTOPWRFAIL = 0x08, 201 PCF50633_INT4_DWN1PWRFAIL = 0x10, 202 PCF50633_INT4_DWN2PWRFAIL = 0x20, 203 PCF50633_INT4_LEDPWRFAIL = 0x40, 204 PCF50633_INT4_LEDOVP = 0x80, 205 }; 206 207 enum pcf50633_reg_int5 { 208 PCF50633_INT5_LDO1PWRFAIL = 0x01, 209 PCF50633_INT5_LDO2PWRFAIL = 0x02, 210 PCF50633_INT5_LDO3PWRFAIL = 0x04, 211 PCF50633_INT5_LDO4PWRFAIL = 0x08, 212 PCF50633_INT5_LDO5PWRFAIL = 0x10, 213 PCF50633_INT5_LDO6PWRFAIL = 0x20, 214 PCF50633_INT5_HCLDOPWRFAIL = 0x40, 215 PCF50633_INT5_HCLDOOVL = 0x80, 216 }; 217 218 /* misc. registers */ 219 #define PCF50633_REG_OOCSHDWN 0x0c 220 221 /* LED registers */ 222 #define PCF50633_REG_LEDOUT 0x28 223 #define PCF50633_REG_LEDENA 0x29 224 #define PCF50633_REG_LEDCTL 0x2a 225 #define PCF50633_REG_LEDDIM 0x2b 226 227 #endif 228 229