1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * TI Palmas 4 * 5 * Copyright 2011-2013 Texas Instruments Inc. 6 * 7 * Author: Graeme Gregory <[email protected]> 8 * Author: Ian Lartey <[email protected]> 9 */ 10 11 #ifndef __LINUX_MFD_PALMAS_H 12 #define __LINUX_MFD_PALMAS_H 13 14 #include <linux/usb/otg.h> 15 #include <linux/leds.h> 16 #include <linux/regmap.h> 17 #include <linux/regulator/driver.h> 18 #include <linux/extcon-provider.h> 19 #include <linux/usb/phy_companion.h> 20 21 #define PALMAS_NUM_CLIENTS 3 22 23 /* The ID_REVISION NUMBERS */ 24 #define PALMAS_CHIP_OLD_ID 0x0000 25 #define PALMAS_CHIP_ID 0xC035 26 #define PALMAS_CHIP_CHARGER_ID 0xC036 27 28 #define TPS65917_RESERVED -1 29 30 #define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \ 31 ((a) == PALMAS_CHIP_ID)) 32 #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID) 33 34 /** 35 * Palmas PMIC feature types 36 * 37 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST 38 * regulator. 39 * 40 * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a 41 * specific feature (above) or not. Return non-zero, if yes. 42 */ 43 #define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0) 44 #define PALMAS_PMIC_HAS(b, f) \ 45 ((b)->features & PALMAS_PMIC_FEATURE_ ## f) 46 47 struct palmas_pmic; 48 struct palmas_gpadc; 49 struct palmas_resource; 50 struct palmas_usb; 51 struct palmas_pmic_driver_data; 52 struct palmas_pmic_platform_data; 53 54 enum palmas_usb_state { 55 PALMAS_USB_STATE_DISCONNECT, 56 PALMAS_USB_STATE_VBUS, 57 PALMAS_USB_STATE_ID, 58 }; 59 60 struct palmas { 61 struct device *dev; 62 63 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS]; 64 struct regmap *regmap[PALMAS_NUM_CLIENTS]; 65 66 /* Stored chip id */ 67 int id; 68 69 unsigned int features; 70 /* IRQ Data */ 71 int irq; 72 u32 irq_mask; 73 struct mutex irq_lock; 74 struct regmap_irq_chip_data *irq_data; 75 76 struct palmas_pmic_driver_data *pmic_ddata; 77 78 /* Child Devices */ 79 struct palmas_pmic *pmic; 80 struct palmas_gpadc *gpadc; 81 struct palmas_resource *resource; 82 struct palmas_usb *usb; 83 84 /* GPIO MUXing */ 85 u8 gpio_muxed; 86 u8 led_muxed; 87 u8 pwm_muxed; 88 }; 89 90 #define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \ 91 PALMAS_EXT_CONTROL_ENABLE2 | \ 92 PALMAS_EXT_CONTROL_NSLEEP) 93 94 struct palmas_sleep_requestor_info { 95 int id; 96 int reg_offset; 97 int bit_pos; 98 }; 99 100 struct palmas_regs_info { 101 char *name; 102 char *sname; 103 u8 vsel_addr; 104 u8 ctrl_addr; 105 u8 tstep_addr; 106 int sleep_id; 107 }; 108 109 struct palmas_pmic_driver_data { 110 int smps_start; 111 int smps_end; 112 int ldo_begin; 113 int ldo_end; 114 int max_reg; 115 bool has_regen3; 116 struct palmas_regs_info *palmas_regs_info; 117 struct of_regulator_match *palmas_matches; 118 struct palmas_sleep_requestor_info *sleep_req_info; 119 int (*smps_register)(struct palmas_pmic *pmic, 120 struct palmas_pmic_driver_data *ddata, 121 struct palmas_pmic_platform_data *pdata, 122 const char *pdev_name, 123 struct regulator_config config); 124 int (*ldo_register)(struct palmas_pmic *pmic, 125 struct palmas_pmic_driver_data *ddata, 126 struct palmas_pmic_platform_data *pdata, 127 const char *pdev_name, 128 struct regulator_config config); 129 }; 130 131 struct palmas_adc_wakeup_property { 132 int adc_channel_number; 133 int adc_high_threshold; 134 int adc_low_threshold; 135 }; 136 137 struct palmas_gpadc_platform_data { 138 /* Channel 3 current source is only enabled during conversion */ 139 int ch3_current; /* 0: off; 1: 10uA; 2: 400uA; 3: 800 uA */ 140 141 /* Channel 0 current source can be used for battery detection. 142 * If used for battery detection this will cause a permanent current 143 * consumption depending on current level set here. 144 */ 145 int ch0_current; /* 0: off; 1: 5uA; 2: 15uA; 3: 20 uA */ 146 bool extended_delay; /* use extended delay for conversion */ 147 148 /* default BAT_REMOVAL_DAT setting on device probe */ 149 int bat_removal; 150 151 /* Sets the START_POLARITY bit in the RT_CTRL register */ 152 int start_polarity; 153 154 int auto_conversion_period_ms; 155 struct palmas_adc_wakeup_property *adc_wakeup1_data; 156 struct palmas_adc_wakeup_property *adc_wakeup2_data; 157 }; 158 159 struct palmas_reg_init { 160 /* warm_rest controls the voltage levels after a warm reset 161 * 162 * 0: reload default values from OTP on warm reset 163 * 1: maintain voltage from VSEL on warm reset 164 */ 165 int warm_reset; 166 167 /* roof_floor controls whether the regulator uses the i2c style 168 * of DVS or uses the method where a GPIO or other control method is 169 * attached to the NSLEEP/ENABLE1/ENABLE2 pins 170 * 171 * For SMPS 172 * 173 * 0: i2c selection of voltage 174 * 1: pin selection of voltage. 175 * 176 * For LDO unused 177 */ 178 int roof_floor; 179 180 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in 181 * the data sheet. 182 * 183 * For SMPS 184 * 185 * 0: Off 186 * 1: AUTO 187 * 2: ECO 188 * 3: Forced PWM 189 * 190 * For LDO 191 * 192 * 0: Off 193 * 1: On 194 */ 195 int mode_sleep; 196 197 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE 198 * register. Set this is the default voltage set in OTP needs 199 * to be overridden. 200 */ 201 u8 vsel; 202 203 }; 204 205 enum palmas_regulators { 206 /* SMPS regulators */ 207 PALMAS_REG_SMPS12, 208 PALMAS_REG_SMPS123, 209 PALMAS_REG_SMPS3, 210 PALMAS_REG_SMPS45, 211 PALMAS_REG_SMPS457, 212 PALMAS_REG_SMPS6, 213 PALMAS_REG_SMPS7, 214 PALMAS_REG_SMPS8, 215 PALMAS_REG_SMPS9, 216 PALMAS_REG_SMPS10_OUT2, 217 PALMAS_REG_SMPS10_OUT1, 218 /* LDO regulators */ 219 PALMAS_REG_LDO1, 220 PALMAS_REG_LDO2, 221 PALMAS_REG_LDO3, 222 PALMAS_REG_LDO4, 223 PALMAS_REG_LDO5, 224 PALMAS_REG_LDO6, 225 PALMAS_REG_LDO7, 226 PALMAS_REG_LDO8, 227 PALMAS_REG_LDO9, 228 PALMAS_REG_LDOLN, 229 PALMAS_REG_LDOUSB, 230 /* External regulators */ 231 PALMAS_REG_REGEN1, 232 PALMAS_REG_REGEN2, 233 PALMAS_REG_REGEN3, 234 PALMAS_REG_SYSEN1, 235 PALMAS_REG_SYSEN2, 236 /* Total number of regulators */ 237 PALMAS_NUM_REGS, 238 }; 239 240 enum tps65917_regulators { 241 /* SMPS regulators */ 242 TPS65917_REG_SMPS1, 243 TPS65917_REG_SMPS2, 244 TPS65917_REG_SMPS3, 245 TPS65917_REG_SMPS4, 246 TPS65917_REG_SMPS5, 247 TPS65917_REG_SMPS12, 248 /* LDO regulators */ 249 TPS65917_REG_LDO1, 250 TPS65917_REG_LDO2, 251 TPS65917_REG_LDO3, 252 TPS65917_REG_LDO4, 253 TPS65917_REG_LDO5, 254 TPS65917_REG_REGEN1, 255 TPS65917_REG_REGEN2, 256 TPS65917_REG_REGEN3, 257 258 /* Total number of regulators */ 259 TPS65917_NUM_REGS, 260 }; 261 262 /* External controll signal name */ 263 enum { 264 PALMAS_EXT_CONTROL_ENABLE1 = 0x1, 265 PALMAS_EXT_CONTROL_ENABLE2 = 0x2, 266 PALMAS_EXT_CONTROL_NSLEEP = 0x4, 267 }; 268 269 /* 270 * Palmas device resources can be controlled externally for 271 * enabling/disabling it rather than register write through i2c. 272 * Add the external controlled requestor ID for different resources. 273 */ 274 enum palmas_external_requestor_id { 275 PALMAS_EXTERNAL_REQSTR_ID_REGEN1, 276 PALMAS_EXTERNAL_REQSTR_ID_REGEN2, 277 PALMAS_EXTERNAL_REQSTR_ID_SYSEN1, 278 PALMAS_EXTERNAL_REQSTR_ID_SYSEN2, 279 PALMAS_EXTERNAL_REQSTR_ID_CLK32KG, 280 PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO, 281 PALMAS_EXTERNAL_REQSTR_ID_REGEN3, 282 PALMAS_EXTERNAL_REQSTR_ID_SMPS12, 283 PALMAS_EXTERNAL_REQSTR_ID_SMPS3, 284 PALMAS_EXTERNAL_REQSTR_ID_SMPS45, 285 PALMAS_EXTERNAL_REQSTR_ID_SMPS6, 286 PALMAS_EXTERNAL_REQSTR_ID_SMPS7, 287 PALMAS_EXTERNAL_REQSTR_ID_SMPS8, 288 PALMAS_EXTERNAL_REQSTR_ID_SMPS9, 289 PALMAS_EXTERNAL_REQSTR_ID_SMPS10, 290 PALMAS_EXTERNAL_REQSTR_ID_LDO1, 291 PALMAS_EXTERNAL_REQSTR_ID_LDO2, 292 PALMAS_EXTERNAL_REQSTR_ID_LDO3, 293 PALMAS_EXTERNAL_REQSTR_ID_LDO4, 294 PALMAS_EXTERNAL_REQSTR_ID_LDO5, 295 PALMAS_EXTERNAL_REQSTR_ID_LDO6, 296 PALMAS_EXTERNAL_REQSTR_ID_LDO7, 297 PALMAS_EXTERNAL_REQSTR_ID_LDO8, 298 PALMAS_EXTERNAL_REQSTR_ID_LDO9, 299 PALMAS_EXTERNAL_REQSTR_ID_LDOLN, 300 PALMAS_EXTERNAL_REQSTR_ID_LDOUSB, 301 302 /* Last entry */ 303 PALMAS_EXTERNAL_REQSTR_ID_MAX, 304 }; 305 306 enum tps65917_external_requestor_id { 307 TPS65917_EXTERNAL_REQSTR_ID_REGEN1, 308 TPS65917_EXTERNAL_REQSTR_ID_REGEN2, 309 TPS65917_EXTERNAL_REQSTR_ID_REGEN3, 310 TPS65917_EXTERNAL_REQSTR_ID_SMPS1, 311 TPS65917_EXTERNAL_REQSTR_ID_SMPS2, 312 TPS65917_EXTERNAL_REQSTR_ID_SMPS3, 313 TPS65917_EXTERNAL_REQSTR_ID_SMPS4, 314 TPS65917_EXTERNAL_REQSTR_ID_SMPS5, 315 TPS65917_EXTERNAL_REQSTR_ID_SMPS12, 316 TPS65917_EXTERNAL_REQSTR_ID_LDO1, 317 TPS65917_EXTERNAL_REQSTR_ID_LDO2, 318 TPS65917_EXTERNAL_REQSTR_ID_LDO3, 319 TPS65917_EXTERNAL_REQSTR_ID_LDO4, 320 TPS65917_EXTERNAL_REQSTR_ID_LDO5, 321 /* Last entry */ 322 TPS65917_EXTERNAL_REQSTR_ID_MAX, 323 }; 324 325 struct palmas_pmic_platform_data { 326 /* An array of pointers to regulator init data indexed by regulator 327 * ID 328 */ 329 struct regulator_init_data *reg_data[PALMAS_NUM_REGS]; 330 331 /* An array of pointers to structures containing sleep mode and DVS 332 * configuration for regulators indexed by ID 333 */ 334 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS]; 335 336 /* use LDO6 for vibrator control */ 337 int ldo6_vibrator; 338 339 /* Enable tracking mode of LDO8 */ 340 bool enable_ldo8_tracking; 341 }; 342 343 struct palmas_usb_platform_data { 344 /* Do we enable the wakeup comparator on probe */ 345 int wakeup; 346 }; 347 348 struct palmas_resource_platform_data { 349 int regen1_mode_sleep; 350 int regen2_mode_sleep; 351 int sysen1_mode_sleep; 352 int sysen2_mode_sleep; 353 354 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */ 355 u8 nsleep_res; 356 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */ 357 u8 nsleep_smps; 358 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */ 359 u8 nsleep_ldo1; 360 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */ 361 u8 nsleep_ldo2; 362 363 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */ 364 u8 enable1_res; 365 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */ 366 u8 enable1_smps; 367 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */ 368 u8 enable1_ldo1; 369 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */ 370 u8 enable1_ldo2; 371 372 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */ 373 u8 enable2_res; 374 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */ 375 u8 enable2_smps; 376 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */ 377 u8 enable2_ldo1; 378 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */ 379 u8 enable2_ldo2; 380 }; 381 382 struct palmas_clk_platform_data { 383 int clk32kg_mode_sleep; 384 int clk32kgaudio_mode_sleep; 385 }; 386 387 struct palmas_platform_data { 388 int irq_flags; 389 int gpio_base; 390 391 /* bit value to be loaded to the POWER_CTRL register */ 392 u8 power_ctrl; 393 394 /* 395 * boolean to select if we want to configure muxing here 396 * then the two value to load into the registers if true 397 */ 398 int mux_from_pdata; 399 u8 pad1, pad2; 400 bool pm_off; 401 402 struct palmas_pmic_platform_data *pmic_pdata; 403 struct palmas_gpadc_platform_data *gpadc_pdata; 404 struct palmas_usb_platform_data *usb_pdata; 405 struct palmas_resource_platform_data *resource_pdata; 406 struct palmas_clk_platform_data *clk_pdata; 407 }; 408 409 struct palmas_gpadc_calibration { 410 s32 gain; 411 s32 gain_error; 412 s32 offset_error; 413 }; 414 415 #define PALMAS_DATASHEET_NAME(_name) "palmas-gpadc-chan-"#_name 416 417 struct palmas_gpadc_result { 418 s32 raw_code; 419 s32 corrected_code; 420 s32 result; 421 }; 422 423 #define PALMAS_MAX_CHANNELS 16 424 425 /* Define the tps65917 IRQ numbers */ 426 enum tps65917_irqs { 427 /* INT1 registers */ 428 TPS65917_RESERVED1, 429 TPS65917_PWRON_IRQ, 430 TPS65917_LONG_PRESS_KEY_IRQ, 431 TPS65917_RESERVED2, 432 TPS65917_PWRDOWN_IRQ, 433 TPS65917_HOTDIE_IRQ, 434 TPS65917_VSYS_MON_IRQ, 435 TPS65917_RESERVED3, 436 /* INT2 registers */ 437 TPS65917_RESERVED4, 438 TPS65917_OTP_ERROR_IRQ, 439 TPS65917_WDT_IRQ, 440 TPS65917_RESERVED5, 441 TPS65917_RESET_IN_IRQ, 442 TPS65917_FSD_IRQ, 443 TPS65917_SHORT_IRQ, 444 TPS65917_RESERVED6, 445 /* INT3 registers */ 446 TPS65917_GPADC_AUTO_0_IRQ, 447 TPS65917_GPADC_AUTO_1_IRQ, 448 TPS65917_GPADC_EOC_SW_IRQ, 449 TPS65917_RESREVED6, 450 TPS65917_RESERVED7, 451 TPS65917_RESERVED8, 452 TPS65917_RESERVED9, 453 TPS65917_VBUS_IRQ, 454 /* INT4 registers */ 455 TPS65917_GPIO_0_IRQ, 456 TPS65917_GPIO_1_IRQ, 457 TPS65917_GPIO_2_IRQ, 458 TPS65917_GPIO_3_IRQ, 459 TPS65917_GPIO_4_IRQ, 460 TPS65917_GPIO_5_IRQ, 461 TPS65917_GPIO_6_IRQ, 462 TPS65917_RESERVED10, 463 /* Total Number IRQs */ 464 TPS65917_NUM_IRQ, 465 }; 466 467 /* Define the palmas IRQ numbers */ 468 enum palmas_irqs { 469 /* INT1 registers */ 470 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ, 471 PALMAS_PWRON_IRQ, 472 PALMAS_LONG_PRESS_KEY_IRQ, 473 PALMAS_RPWRON_IRQ, 474 PALMAS_PWRDOWN_IRQ, 475 PALMAS_HOTDIE_IRQ, 476 PALMAS_VSYS_MON_IRQ, 477 PALMAS_VBAT_MON_IRQ, 478 /* INT2 registers */ 479 PALMAS_RTC_ALARM_IRQ, 480 PALMAS_RTC_TIMER_IRQ, 481 PALMAS_WDT_IRQ, 482 PALMAS_BATREMOVAL_IRQ, 483 PALMAS_RESET_IN_IRQ, 484 PALMAS_FBI_BB_IRQ, 485 PALMAS_SHORT_IRQ, 486 PALMAS_VAC_ACOK_IRQ, 487 /* INT3 registers */ 488 PALMAS_GPADC_AUTO_0_IRQ, 489 PALMAS_GPADC_AUTO_1_IRQ, 490 PALMAS_GPADC_EOC_SW_IRQ, 491 PALMAS_GPADC_EOC_RT_IRQ, 492 PALMAS_ID_OTG_IRQ, 493 PALMAS_ID_IRQ, 494 PALMAS_VBUS_OTG_IRQ, 495 PALMAS_VBUS_IRQ, 496 /* INT4 registers */ 497 PALMAS_GPIO_0_IRQ, 498 PALMAS_GPIO_1_IRQ, 499 PALMAS_GPIO_2_IRQ, 500 PALMAS_GPIO_3_IRQ, 501 PALMAS_GPIO_4_IRQ, 502 PALMAS_GPIO_5_IRQ, 503 PALMAS_GPIO_6_IRQ, 504 PALMAS_GPIO_7_IRQ, 505 /* Total Number IRQs */ 506 PALMAS_NUM_IRQ, 507 }; 508 509 /* Palmas GPADC Channels */ 510 enum { 511 PALMAS_ADC_CH_IN0, 512 PALMAS_ADC_CH_IN1, 513 PALMAS_ADC_CH_IN2, 514 PALMAS_ADC_CH_IN3, 515 PALMAS_ADC_CH_IN4, 516 PALMAS_ADC_CH_IN5, 517 PALMAS_ADC_CH_IN6, 518 PALMAS_ADC_CH_IN7, 519 PALMAS_ADC_CH_IN8, 520 PALMAS_ADC_CH_IN9, 521 PALMAS_ADC_CH_IN10, 522 PALMAS_ADC_CH_IN11, 523 PALMAS_ADC_CH_IN12, 524 PALMAS_ADC_CH_IN13, 525 PALMAS_ADC_CH_IN14, 526 PALMAS_ADC_CH_IN15, 527 PALMAS_ADC_CH_MAX, 528 }; 529 530 /* Palmas GPADC Channel0 Current Source */ 531 enum { 532 PALMAS_ADC_CH0_CURRENT_SRC_0, 533 PALMAS_ADC_CH0_CURRENT_SRC_5, 534 PALMAS_ADC_CH0_CURRENT_SRC_15, 535 PALMAS_ADC_CH0_CURRENT_SRC_20, 536 }; 537 538 /* Palmas GPADC Channel3 Current Source */ 539 enum { 540 PALMAS_ADC_CH3_CURRENT_SRC_0, 541 PALMAS_ADC_CH3_CURRENT_SRC_10, 542 PALMAS_ADC_CH3_CURRENT_SRC_400, 543 PALMAS_ADC_CH3_CURRENT_SRC_800, 544 }; 545 546 struct palmas_pmic { 547 struct palmas *palmas; 548 struct device *dev; 549 struct regulator_desc desc[PALMAS_NUM_REGS]; 550 struct mutex mutex; 551 552 int smps123; 553 int smps457; 554 int smps12; 555 556 int range[PALMAS_REG_SMPS10_OUT1]; 557 unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1]; 558 unsigned int current_reg_mode[PALMAS_REG_SMPS10_OUT1]; 559 }; 560 561 struct palmas_resource { 562 struct palmas *palmas; 563 struct device *dev; 564 }; 565 566 struct palmas_usb { 567 struct palmas *palmas; 568 struct device *dev; 569 570 struct extcon_dev *edev; 571 572 int id_otg_irq; 573 int id_irq; 574 int vbus_otg_irq; 575 int vbus_irq; 576 577 int gpio_id_irq; 578 int gpio_vbus_irq; 579 struct gpio_desc *id_gpiod; 580 struct gpio_desc *vbus_gpiod; 581 unsigned long sw_debounce_jiffies; 582 struct delayed_work wq_detectid; 583 584 enum palmas_usb_state linkstat; 585 int wakeup; 586 bool enable_vbus_detection; 587 bool enable_id_detection; 588 bool enable_gpio_id_detection; 589 bool enable_gpio_vbus_detection; 590 }; 591 592 #define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator) 593 594 enum usb_irq_events { 595 /* Wakeup events from INT3 */ 596 PALMAS_USB_ID_WAKEPUP, 597 PALMAS_USB_VBUS_WAKEUP, 598 599 /* ID_OTG_EVENTS */ 600 PALMAS_USB_ID_GND, 601 N_PALMAS_USB_ID_GND, 602 PALMAS_USB_ID_C, 603 N_PALMAS_USB_ID_C, 604 PALMAS_USB_ID_B, 605 N_PALMAS_USB_ID_B, 606 PALMAS_USB_ID_A, 607 N_PALMAS_USB_ID_A, 608 PALMAS_USB_ID_FLOAT, 609 N_PALMAS_USB_ID_FLOAT, 610 611 /* VBUS_OTG_EVENTS */ 612 PALMAS_USB_VB_SESS_END, 613 N_PALMAS_USB_VB_SESS_END, 614 PALMAS_USB_VB_SESS_VLD, 615 N_PALMAS_USB_VB_SESS_VLD, 616 PALMAS_USB_VA_SESS_VLD, 617 N_PALMAS_USB_VA_SESS_VLD, 618 PALMAS_USB_VA_VBUS_VLD, 619 N_PALMAS_USB_VA_VBUS_VLD, 620 PALMAS_USB_VADP_SNS, 621 N_PALMAS_USB_VADP_SNS, 622 PALMAS_USB_VADP_PRB, 623 N_PALMAS_USB_VADP_PRB, 624 PALMAS_USB_VOTG_SESS_VLD, 625 N_PALMAS_USB_VOTG_SESS_VLD, 626 }; 627 628 /* defines so we can store the mux settings */ 629 #define PALMAS_GPIO_0_MUXED (1 << 0) 630 #define PALMAS_GPIO_1_MUXED (1 << 1) 631 #define PALMAS_GPIO_2_MUXED (1 << 2) 632 #define PALMAS_GPIO_3_MUXED (1 << 3) 633 #define PALMAS_GPIO_4_MUXED (1 << 4) 634 #define PALMAS_GPIO_5_MUXED (1 << 5) 635 #define PALMAS_GPIO_6_MUXED (1 << 6) 636 #define PALMAS_GPIO_7_MUXED (1 << 7) 637 638 #define PALMAS_LED1_MUXED (1 << 0) 639 #define PALMAS_LED2_MUXED (1 << 1) 640 641 #define PALMAS_PWM1_MUXED (1 << 0) 642 #define PALMAS_PWM2_MUXED (1 << 1) 643 644 /* helper macro to get correct slave number */ 645 #define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1) 646 #define PALMAS_BASE_TO_REG(x, y) ((x & 0xFF) + y) 647 648 /* Base addresses of IP blocks in Palmas */ 649 #define PALMAS_SMPS_DVS_BASE 0x020 650 #define PALMAS_RTC_BASE 0x100 651 #define PALMAS_VALIDITY_BASE 0x118 652 #define PALMAS_SMPS_BASE 0x120 653 #define PALMAS_LDO_BASE 0x150 654 #define PALMAS_DVFS_BASE 0x180 655 #define PALMAS_PMU_CONTROL_BASE 0x1A0 656 #define PALMAS_RESOURCE_BASE 0x1D4 657 #define PALMAS_PU_PD_OD_BASE 0x1F0 658 #define PALMAS_LED_BASE 0x200 659 #define PALMAS_INTERRUPT_BASE 0x210 660 #define PALMAS_USB_OTG_BASE 0x250 661 #define PALMAS_VIBRATOR_BASE 0x270 662 #define PALMAS_GPIO_BASE 0x280 663 #define PALMAS_USB_BASE 0x290 664 #define PALMAS_GPADC_BASE 0x2C0 665 #define PALMAS_TRIM_GPADC_BASE 0x3CD 666 667 /* Registers for function RTC */ 668 #define PALMAS_SECONDS_REG 0x00 669 #define PALMAS_MINUTES_REG 0x01 670 #define PALMAS_HOURS_REG 0x02 671 #define PALMAS_DAYS_REG 0x03 672 #define PALMAS_MONTHS_REG 0x04 673 #define PALMAS_YEARS_REG 0x05 674 #define PALMAS_WEEKS_REG 0x06 675 #define PALMAS_ALARM_SECONDS_REG 0x08 676 #define PALMAS_ALARM_MINUTES_REG 0x09 677 #define PALMAS_ALARM_HOURS_REG 0x0A 678 #define PALMAS_ALARM_DAYS_REG 0x0B 679 #define PALMAS_ALARM_MONTHS_REG 0x0C 680 #define PALMAS_ALARM_YEARS_REG 0x0D 681 #define PALMAS_RTC_CTRL_REG 0x10 682 #define PALMAS_RTC_STATUS_REG 0x11 683 #define PALMAS_RTC_INTERRUPTS_REG 0x12 684 #define PALMAS_RTC_COMP_LSB_REG 0x13 685 #define PALMAS_RTC_COMP_MSB_REG 0x14 686 #define PALMAS_RTC_RES_PROG_REG 0x15 687 #define PALMAS_RTC_RESET_STATUS_REG 0x16 688 689 /* Bit definitions for SECONDS_REG */ 690 #define PALMAS_SECONDS_REG_SEC1_MASK 0x70 691 #define PALMAS_SECONDS_REG_SEC1_SHIFT 0x04 692 #define PALMAS_SECONDS_REG_SEC0_MASK 0x0F 693 #define PALMAS_SECONDS_REG_SEC0_SHIFT 0x00 694 695 /* Bit definitions for MINUTES_REG */ 696 #define PALMAS_MINUTES_REG_MIN1_MASK 0x70 697 #define PALMAS_MINUTES_REG_MIN1_SHIFT 0x04 698 #define PALMAS_MINUTES_REG_MIN0_MASK 0x0F 699 #define PALMAS_MINUTES_REG_MIN0_SHIFT 0x00 700 701 /* Bit definitions for HOURS_REG */ 702 #define PALMAS_HOURS_REG_PM_NAM 0x80 703 #define PALMAS_HOURS_REG_PM_NAM_SHIFT 0x07 704 #define PALMAS_HOURS_REG_HOUR1_MASK 0x30 705 #define PALMAS_HOURS_REG_HOUR1_SHIFT 0x04 706 #define PALMAS_HOURS_REG_HOUR0_MASK 0x0F 707 #define PALMAS_HOURS_REG_HOUR0_SHIFT 0x00 708 709 /* Bit definitions for DAYS_REG */ 710 #define PALMAS_DAYS_REG_DAY1_MASK 0x30 711 #define PALMAS_DAYS_REG_DAY1_SHIFT 0x04 712 #define PALMAS_DAYS_REG_DAY0_MASK 0x0F 713 #define PALMAS_DAYS_REG_DAY0_SHIFT 0x00 714 715 /* Bit definitions for MONTHS_REG */ 716 #define PALMAS_MONTHS_REG_MONTH1 0x10 717 #define PALMAS_MONTHS_REG_MONTH1_SHIFT 0x04 718 #define PALMAS_MONTHS_REG_MONTH0_MASK 0x0F 719 #define PALMAS_MONTHS_REG_MONTH0_SHIFT 0x00 720 721 /* Bit definitions for YEARS_REG */ 722 #define PALMAS_YEARS_REG_YEAR1_MASK 0xf0 723 #define PALMAS_YEARS_REG_YEAR1_SHIFT 0x04 724 #define PALMAS_YEARS_REG_YEAR0_MASK 0x0F 725 #define PALMAS_YEARS_REG_YEAR0_SHIFT 0x00 726 727 /* Bit definitions for WEEKS_REG */ 728 #define PALMAS_WEEKS_REG_WEEK_MASK 0x07 729 #define PALMAS_WEEKS_REG_WEEK_SHIFT 0x00 730 731 /* Bit definitions for ALARM_SECONDS_REG */ 732 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70 733 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 0x04 734 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0F 735 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0x00 736 737 /* Bit definitions for ALARM_MINUTES_REG */ 738 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70 739 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 0x04 740 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0F 741 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0x00 742 743 /* Bit definitions for ALARM_HOURS_REG */ 744 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80 745 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 0x07 746 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30 747 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 0x04 748 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0F 749 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0x00 750 751 /* Bit definitions for ALARM_DAYS_REG */ 752 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30 753 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 0x04 754 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0F 755 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0x00 756 757 /* Bit definitions for ALARM_MONTHS_REG */ 758 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10 759 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 0x04 760 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0F 761 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0x00 762 763 /* Bit definitions for ALARM_YEARS_REG */ 764 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0 765 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 0x04 766 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0F 767 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0x00 768 769 /* Bit definitions for RTC_CTRL_REG */ 770 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80 771 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 0x07 772 #define PALMAS_RTC_CTRL_REG_GET_TIME 0x40 773 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 0x06 774 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20 775 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 0x05 776 #define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10 777 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 0x04 778 #define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08 779 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 0x03 780 #define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04 781 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 0x02 782 #define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02 783 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 0x01 784 #define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01 785 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0x00 786 787 /* Bit definitions for RTC_STATUS_REG */ 788 #define PALMAS_RTC_STATUS_REG_POWER_UP 0x80 789 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 0x07 790 #define PALMAS_RTC_STATUS_REG_ALARM 0x40 791 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 0x06 792 #define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20 793 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 0x05 794 #define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10 795 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 0x04 796 #define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08 797 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 0x03 798 #define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04 799 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 0x02 800 #define PALMAS_RTC_STATUS_REG_RUN 0x02 801 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT 0x01 802 803 /* Bit definitions for RTC_INTERRUPTS_REG */ 804 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10 805 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 0x04 806 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08 807 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 0x03 808 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04 809 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 0x02 810 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03 811 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0x00 812 813 /* Bit definitions for RTC_COMP_LSB_REG */ 814 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xFF 815 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0x00 816 817 /* Bit definitions for RTC_COMP_MSB_REG */ 818 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xFF 819 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0x00 820 821 /* Bit definitions for RTC_RES_PROG_REG */ 822 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3F 823 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0x00 824 825 /* Bit definitions for RTC_RESET_STATUS_REG */ 826 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01 827 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0x00 828 829 /* Registers for function BACKUP */ 830 #define PALMAS_BACKUP0 0x00 831 #define PALMAS_BACKUP1 0x01 832 #define PALMAS_BACKUP2 0x02 833 #define PALMAS_BACKUP3 0x03 834 #define PALMAS_BACKUP4 0x04 835 #define PALMAS_BACKUP5 0x05 836 #define PALMAS_BACKUP6 0x06 837 #define PALMAS_BACKUP7 0x07 838 839 /* Bit definitions for BACKUP0 */ 840 #define PALMAS_BACKUP0_BACKUP_MASK 0xFF 841 #define PALMAS_BACKUP0_BACKUP_SHIFT 0x00 842 843 /* Bit definitions for BACKUP1 */ 844 #define PALMAS_BACKUP1_BACKUP_MASK 0xFF 845 #define PALMAS_BACKUP1_BACKUP_SHIFT 0x00 846 847 /* Bit definitions for BACKUP2 */ 848 #define PALMAS_BACKUP2_BACKUP_MASK 0xFF 849 #define PALMAS_BACKUP2_BACKUP_SHIFT 0x00 850 851 /* Bit definitions for BACKUP3 */ 852 #define PALMAS_BACKUP3_BACKUP_MASK 0xFF 853 #define PALMAS_BACKUP3_BACKUP_SHIFT 0x00 854 855 /* Bit definitions for BACKUP4 */ 856 #define PALMAS_BACKUP4_BACKUP_MASK 0xFF 857 #define PALMAS_BACKUP4_BACKUP_SHIFT 0x00 858 859 /* Bit definitions for BACKUP5 */ 860 #define PALMAS_BACKUP5_BACKUP_MASK 0xFF 861 #define PALMAS_BACKUP5_BACKUP_SHIFT 0x00 862 863 /* Bit definitions for BACKUP6 */ 864 #define PALMAS_BACKUP6_BACKUP_MASK 0xFF 865 #define PALMAS_BACKUP6_BACKUP_SHIFT 0x00 866 867 /* Bit definitions for BACKUP7 */ 868 #define PALMAS_BACKUP7_BACKUP_MASK 0xFF 869 #define PALMAS_BACKUP7_BACKUP_SHIFT 0x00 870 871 /* Registers for function SMPS */ 872 #define PALMAS_SMPS12_CTRL 0x00 873 #define PALMAS_SMPS12_TSTEP 0x01 874 #define PALMAS_SMPS12_FORCE 0x02 875 #define PALMAS_SMPS12_VOLTAGE 0x03 876 #define PALMAS_SMPS3_CTRL 0x04 877 #define PALMAS_SMPS3_VOLTAGE 0x07 878 #define PALMAS_SMPS45_CTRL 0x08 879 #define PALMAS_SMPS45_TSTEP 0x09 880 #define PALMAS_SMPS45_FORCE 0x0A 881 #define PALMAS_SMPS45_VOLTAGE 0x0B 882 #define PALMAS_SMPS6_CTRL 0x0C 883 #define PALMAS_SMPS6_TSTEP 0x0D 884 #define PALMAS_SMPS6_FORCE 0x0E 885 #define PALMAS_SMPS6_VOLTAGE 0x0F 886 #define PALMAS_SMPS7_CTRL 0x10 887 #define PALMAS_SMPS7_VOLTAGE 0x13 888 #define PALMAS_SMPS8_CTRL 0x14 889 #define PALMAS_SMPS8_TSTEP 0x15 890 #define PALMAS_SMPS8_FORCE 0x16 891 #define PALMAS_SMPS8_VOLTAGE 0x17 892 #define PALMAS_SMPS9_CTRL 0x18 893 #define PALMAS_SMPS9_VOLTAGE 0x1B 894 #define PALMAS_SMPS10_CTRL 0x1C 895 #define PALMAS_SMPS10_STATUS 0x1F 896 #define PALMAS_SMPS_CTRL 0x24 897 #define PALMAS_SMPS_PD_CTRL 0x25 898 #define PALMAS_SMPS_DITHER_EN 0x26 899 #define PALMAS_SMPS_THERMAL_EN 0x27 900 #define PALMAS_SMPS_THERMAL_STATUS 0x28 901 #define PALMAS_SMPS_SHORT_STATUS 0x29 902 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A 903 #define PALMAS_SMPS_POWERGOOD_MASK1 0x2B 904 #define PALMAS_SMPS_POWERGOOD_MASK2 0x2C 905 906 /* Bit definitions for SMPS12_CTRL */ 907 #define PALMAS_SMPS12_CTRL_WR_S 0x80 908 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT 0x07 909 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40 910 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 911 #define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30 912 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT 0x04 913 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c 914 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 0x02 915 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03 916 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0x00 917 918 /* Bit definitions for SMPS12_TSTEP */ 919 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03 920 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0x00 921 922 /* Bit definitions for SMPS12_FORCE */ 923 #define PALMAS_SMPS12_FORCE_CMD 0x80 924 #define PALMAS_SMPS12_FORCE_CMD_SHIFT 0x07 925 #define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7F 926 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0x00 927 928 /* Bit definitions for SMPS12_VOLTAGE */ 929 #define PALMAS_SMPS12_VOLTAGE_RANGE 0x80 930 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 0x07 931 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7F 932 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0x00 933 934 /* Bit definitions for SMPS3_CTRL */ 935 #define PALMAS_SMPS3_CTRL_WR_S 0x80 936 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT 0x07 937 #define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30 938 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT 0x04 939 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c 940 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02 941 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 942 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00 943 944 /* Bit definitions for SMPS3_VOLTAGE */ 945 #define PALMAS_SMPS3_VOLTAGE_RANGE 0x80 946 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 0x07 947 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7F 948 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0x00 949 950 /* Bit definitions for SMPS45_CTRL */ 951 #define PALMAS_SMPS45_CTRL_WR_S 0x80 952 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT 0x07 953 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40 954 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 955 #define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30 956 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT 0x04 957 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c 958 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 0x02 959 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03 960 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0x00 961 962 /* Bit definitions for SMPS45_TSTEP */ 963 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03 964 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0x00 965 966 /* Bit definitions for SMPS45_FORCE */ 967 #define PALMAS_SMPS45_FORCE_CMD 0x80 968 #define PALMAS_SMPS45_FORCE_CMD_SHIFT 0x07 969 #define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7F 970 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0x00 971 972 /* Bit definitions for SMPS45_VOLTAGE */ 973 #define PALMAS_SMPS45_VOLTAGE_RANGE 0x80 974 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 0x07 975 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7F 976 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0x00 977 978 /* Bit definitions for SMPS6_CTRL */ 979 #define PALMAS_SMPS6_CTRL_WR_S 0x80 980 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT 0x07 981 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40 982 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 983 #define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30 984 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT 0x04 985 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c 986 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 0x02 987 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03 988 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0x00 989 990 /* Bit definitions for SMPS6_TSTEP */ 991 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03 992 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0x00 993 994 /* Bit definitions for SMPS6_FORCE */ 995 #define PALMAS_SMPS6_FORCE_CMD 0x80 996 #define PALMAS_SMPS6_FORCE_CMD_SHIFT 0x07 997 #define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7F 998 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0x00 999 1000 /* Bit definitions for SMPS6_VOLTAGE */ 1001 #define PALMAS_SMPS6_VOLTAGE_RANGE 0x80 1002 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 0x07 1003 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7F 1004 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0x00 1005 1006 /* Bit definitions for SMPS7_CTRL */ 1007 #define PALMAS_SMPS7_CTRL_WR_S 0x80 1008 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT 0x07 1009 #define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30 1010 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT 0x04 1011 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c 1012 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 0x02 1013 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03 1014 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0x00 1015 1016 /* Bit definitions for SMPS7_VOLTAGE */ 1017 #define PALMAS_SMPS7_VOLTAGE_RANGE 0x80 1018 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 0x07 1019 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7F 1020 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0x00 1021 1022 /* Bit definitions for SMPS8_CTRL */ 1023 #define PALMAS_SMPS8_CTRL_WR_S 0x80 1024 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT 0x07 1025 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40 1026 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 1027 #define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30 1028 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT 0x04 1029 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c 1030 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 0x02 1031 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03 1032 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0x00 1033 1034 /* Bit definitions for SMPS8_TSTEP */ 1035 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03 1036 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0x00 1037 1038 /* Bit definitions for SMPS8_FORCE */ 1039 #define PALMAS_SMPS8_FORCE_CMD 0x80 1040 #define PALMAS_SMPS8_FORCE_CMD_SHIFT 0x07 1041 #define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7F 1042 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0x00 1043 1044 /* Bit definitions for SMPS8_VOLTAGE */ 1045 #define PALMAS_SMPS8_VOLTAGE_RANGE 0x80 1046 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 0x07 1047 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7F 1048 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0x00 1049 1050 /* Bit definitions for SMPS9_CTRL */ 1051 #define PALMAS_SMPS9_CTRL_WR_S 0x80 1052 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT 0x07 1053 #define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30 1054 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT 0x04 1055 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c 1056 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 0x02 1057 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03 1058 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0x00 1059 1060 /* Bit definitions for SMPS9_VOLTAGE */ 1061 #define PALMAS_SMPS9_VOLTAGE_RANGE 0x80 1062 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 0x07 1063 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7F 1064 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0x00 1065 1066 /* Bit definitions for SMPS10_CTRL */ 1067 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0 1068 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 0x04 1069 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0F 1070 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0x00 1071 1072 /* Bit definitions for SMPS10_STATUS */ 1073 #define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0F 1074 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0x00 1075 1076 /* Bit definitions for SMPS_CTRL */ 1077 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20 1078 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 0x05 1079 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10 1080 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 0x04 1081 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c 1082 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 0x02 1083 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03 1084 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0x00 1085 1086 /* Bit definitions for SMPS_PD_CTRL */ 1087 #define PALMAS_SMPS_PD_CTRL_SMPS9 0x40 1088 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 0x06 1089 #define PALMAS_SMPS_PD_CTRL_SMPS8 0x20 1090 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 0x05 1091 #define PALMAS_SMPS_PD_CTRL_SMPS7 0x10 1092 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 0x04 1093 #define PALMAS_SMPS_PD_CTRL_SMPS6 0x08 1094 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 0x03 1095 #define PALMAS_SMPS_PD_CTRL_SMPS45 0x04 1096 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 0x02 1097 #define PALMAS_SMPS_PD_CTRL_SMPS3 0x02 1098 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 0x01 1099 #define PALMAS_SMPS_PD_CTRL_SMPS12 0x01 1100 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0x00 1101 1102 /* Bit definitions for SMPS_THERMAL_EN */ 1103 #define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40 1104 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 0x06 1105 #define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20 1106 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 0x05 1107 #define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08 1108 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 0x03 1109 #define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04 1110 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 0x02 1111 #define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01 1112 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0x00 1113 1114 /* Bit definitions for SMPS_THERMAL_STATUS */ 1115 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40 1116 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 0x06 1117 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20 1118 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 0x05 1119 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08 1120 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 0x03 1121 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04 1122 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 0x02 1123 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01 1124 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0x00 1125 1126 /* Bit definitions for SMPS_SHORT_STATUS */ 1127 #define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80 1128 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 0x07 1129 #define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40 1130 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 0x06 1131 #define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20 1132 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 0x05 1133 #define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10 1134 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 0x04 1135 #define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08 1136 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 0x03 1137 #define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04 1138 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 0x02 1139 #define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02 1140 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x01 1141 #define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01 1142 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0x00 1143 1144 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ 1145 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40 1146 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 0x06 1147 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20 1148 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 0x05 1149 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10 1150 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 0x04 1151 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08 1152 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 0x03 1153 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04 1154 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 0x02 1155 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02 1156 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x01 1157 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01 1158 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0x00 1159 1160 /* Bit definitions for SMPS_POWERGOOD_MASK1 */ 1161 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80 1162 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 0x07 1163 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40 1164 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 0x06 1165 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20 1166 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 0x05 1167 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10 1168 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 0x04 1169 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08 1170 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 0x03 1171 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04 1172 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 0x02 1173 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02 1174 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x01 1175 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01 1176 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0x00 1177 1178 /* Bit definitions for SMPS_POWERGOOD_MASK2 */ 1179 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 1180 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07 1181 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04 1182 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 0x02 1183 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02 1184 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 0x01 1185 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01 1186 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0x00 1187 1188 /* Registers for function LDO */ 1189 #define PALMAS_LDO1_CTRL 0x00 1190 #define PALMAS_LDO1_VOLTAGE 0x01 1191 #define PALMAS_LDO2_CTRL 0x02 1192 #define PALMAS_LDO2_VOLTAGE 0x03 1193 #define PALMAS_LDO3_CTRL 0x04 1194 #define PALMAS_LDO3_VOLTAGE 0x05 1195 #define PALMAS_LDO4_CTRL 0x06 1196 #define PALMAS_LDO4_VOLTAGE 0x07 1197 #define PALMAS_LDO5_CTRL 0x08 1198 #define PALMAS_LDO5_VOLTAGE 0x09 1199 #define PALMAS_LDO6_CTRL 0x0A 1200 #define PALMAS_LDO6_VOLTAGE 0x0B 1201 #define PALMAS_LDO7_CTRL 0x0C 1202 #define PALMAS_LDO7_VOLTAGE 0x0D 1203 #define PALMAS_LDO8_CTRL 0x0E 1204 #define PALMAS_LDO8_VOLTAGE 0x0F 1205 #define PALMAS_LDO9_CTRL 0x10 1206 #define PALMAS_LDO9_VOLTAGE 0x11 1207 #define PALMAS_LDOLN_CTRL 0x12 1208 #define PALMAS_LDOLN_VOLTAGE 0x13 1209 #define PALMAS_LDOUSB_CTRL 0x14 1210 #define PALMAS_LDOUSB_VOLTAGE 0x15 1211 #define PALMAS_LDO_CTRL 0x1A 1212 #define PALMAS_LDO_PD_CTRL1 0x1B 1213 #define PALMAS_LDO_PD_CTRL2 0x1C 1214 #define PALMAS_LDO_SHORT_STATUS1 0x1D 1215 #define PALMAS_LDO_SHORT_STATUS2 0x1E 1216 1217 /* Bit definitions for LDO1_CTRL */ 1218 #define PALMAS_LDO1_CTRL_WR_S 0x80 1219 #define PALMAS_LDO1_CTRL_WR_S_SHIFT 0x07 1220 #define PALMAS_LDO1_CTRL_STATUS 0x10 1221 #define PALMAS_LDO1_CTRL_STATUS_SHIFT 0x04 1222 #define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04 1223 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02 1224 #define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01 1225 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00 1226 1227 /* Bit definitions for LDO1_VOLTAGE */ 1228 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3F 1229 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0x00 1230 1231 /* Bit definitions for LDO2_CTRL */ 1232 #define PALMAS_LDO2_CTRL_WR_S 0x80 1233 #define PALMAS_LDO2_CTRL_WR_S_SHIFT 0x07 1234 #define PALMAS_LDO2_CTRL_STATUS 0x10 1235 #define PALMAS_LDO2_CTRL_STATUS_SHIFT 0x04 1236 #define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04 1237 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02 1238 #define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01 1239 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00 1240 1241 /* Bit definitions for LDO2_VOLTAGE */ 1242 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3F 1243 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0x00 1244 1245 /* Bit definitions for LDO3_CTRL */ 1246 #define PALMAS_LDO3_CTRL_WR_S 0x80 1247 #define PALMAS_LDO3_CTRL_WR_S_SHIFT 0x07 1248 #define PALMAS_LDO3_CTRL_STATUS 0x10 1249 #define PALMAS_LDO3_CTRL_STATUS_SHIFT 0x04 1250 #define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04 1251 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02 1252 #define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01 1253 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00 1254 1255 /* Bit definitions for LDO3_VOLTAGE */ 1256 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3F 1257 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0x00 1258 1259 /* Bit definitions for LDO4_CTRL */ 1260 #define PALMAS_LDO4_CTRL_WR_S 0x80 1261 #define PALMAS_LDO4_CTRL_WR_S_SHIFT 0x07 1262 #define PALMAS_LDO4_CTRL_STATUS 0x10 1263 #define PALMAS_LDO4_CTRL_STATUS_SHIFT 0x04 1264 #define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04 1265 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02 1266 #define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01 1267 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00 1268 1269 /* Bit definitions for LDO4_VOLTAGE */ 1270 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3F 1271 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0x00 1272 1273 /* Bit definitions for LDO5_CTRL */ 1274 #define PALMAS_LDO5_CTRL_WR_S 0x80 1275 #define PALMAS_LDO5_CTRL_WR_S_SHIFT 0x07 1276 #define PALMAS_LDO5_CTRL_STATUS 0x10 1277 #define PALMAS_LDO5_CTRL_STATUS_SHIFT 0x04 1278 #define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04 1279 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02 1280 #define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01 1281 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00 1282 1283 /* Bit definitions for LDO5_VOLTAGE */ 1284 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3F 1285 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0x00 1286 1287 /* Bit definitions for LDO6_CTRL */ 1288 #define PALMAS_LDO6_CTRL_WR_S 0x80 1289 #define PALMAS_LDO6_CTRL_WR_S_SHIFT 0x07 1290 #define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40 1291 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 0x06 1292 #define PALMAS_LDO6_CTRL_STATUS 0x10 1293 #define PALMAS_LDO6_CTRL_STATUS_SHIFT 0x04 1294 #define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04 1295 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 0x02 1296 #define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01 1297 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0x00 1298 1299 /* Bit definitions for LDO6_VOLTAGE */ 1300 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3F 1301 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0x00 1302 1303 /* Bit definitions for LDO7_CTRL */ 1304 #define PALMAS_LDO7_CTRL_WR_S 0x80 1305 #define PALMAS_LDO7_CTRL_WR_S_SHIFT 0x07 1306 #define PALMAS_LDO7_CTRL_STATUS 0x10 1307 #define PALMAS_LDO7_CTRL_STATUS_SHIFT 0x04 1308 #define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04 1309 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 0x02 1310 #define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01 1311 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0x00 1312 1313 /* Bit definitions for LDO7_VOLTAGE */ 1314 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3F 1315 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0x00 1316 1317 /* Bit definitions for LDO8_CTRL */ 1318 #define PALMAS_LDO8_CTRL_WR_S 0x80 1319 #define PALMAS_LDO8_CTRL_WR_S_SHIFT 0x07 1320 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40 1321 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 0x06 1322 #define PALMAS_LDO8_CTRL_STATUS 0x10 1323 #define PALMAS_LDO8_CTRL_STATUS_SHIFT 0x04 1324 #define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04 1325 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 0x02 1326 #define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01 1327 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0x00 1328 1329 /* Bit definitions for LDO8_VOLTAGE */ 1330 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3F 1331 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0x00 1332 1333 /* Bit definitions for LDO9_CTRL */ 1334 #define PALMAS_LDO9_CTRL_WR_S 0x80 1335 #define PALMAS_LDO9_CTRL_WR_S_SHIFT 0x07 1336 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40 1337 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 0x06 1338 #define PALMAS_LDO9_CTRL_STATUS 0x10 1339 #define PALMAS_LDO9_CTRL_STATUS_SHIFT 0x04 1340 #define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04 1341 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 0x02 1342 #define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01 1343 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0x00 1344 1345 /* Bit definitions for LDO9_VOLTAGE */ 1346 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3F 1347 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0x00 1348 1349 /* Bit definitions for LDOLN_CTRL */ 1350 #define PALMAS_LDOLN_CTRL_WR_S 0x80 1351 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT 0x07 1352 #define PALMAS_LDOLN_CTRL_STATUS 0x10 1353 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT 0x04 1354 #define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04 1355 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 0x02 1356 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01 1357 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0x00 1358 1359 /* Bit definitions for LDOLN_VOLTAGE */ 1360 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3F 1361 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0x00 1362 1363 /* Bit definitions for LDOUSB_CTRL */ 1364 #define PALMAS_LDOUSB_CTRL_WR_S 0x80 1365 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 0x07 1366 #define PALMAS_LDOUSB_CTRL_STATUS 0x10 1367 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 0x04 1368 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04 1369 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 0x02 1370 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01 1371 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0x00 1372 1373 /* Bit definitions for LDOUSB_VOLTAGE */ 1374 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3F 1375 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0x00 1376 1377 /* Bit definitions for LDO_CTRL */ 1378 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01 1379 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0x00 1380 1381 /* Bit definitions for LDO_PD_CTRL1 */ 1382 #define PALMAS_LDO_PD_CTRL1_LDO8 0x80 1383 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 0x07 1384 #define PALMAS_LDO_PD_CTRL1_LDO7 0x40 1385 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 0x06 1386 #define PALMAS_LDO_PD_CTRL1_LDO6 0x20 1387 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 0x05 1388 #define PALMAS_LDO_PD_CTRL1_LDO5 0x10 1389 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 0x04 1390 #define PALMAS_LDO_PD_CTRL1_LDO4 0x08 1391 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 0x03 1392 #define PALMAS_LDO_PD_CTRL1_LDO3 0x04 1393 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 0x02 1394 #define PALMAS_LDO_PD_CTRL1_LDO2 0x02 1395 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 0x01 1396 #define PALMAS_LDO_PD_CTRL1_LDO1 0x01 1397 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0x00 1398 1399 /* Bit definitions for LDO_PD_CTRL2 */ 1400 #define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04 1401 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 0x02 1402 #define PALMAS_LDO_PD_CTRL2_LDOLN 0x02 1403 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 0x01 1404 #define PALMAS_LDO_PD_CTRL2_LDO9 0x01 1405 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0x00 1406 1407 /* Bit definitions for LDO_SHORT_STATUS1 */ 1408 #define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80 1409 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 0x07 1410 #define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40 1411 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 0x06 1412 #define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20 1413 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 0x05 1414 #define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10 1415 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 0x04 1416 #define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08 1417 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 0x03 1418 #define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04 1419 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 0x02 1420 #define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02 1421 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01 1422 #define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01 1423 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00 1424 1425 /* Bit definitions for LDO_SHORT_STATUS2 */ 1426 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08 1427 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x03 1428 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04 1429 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 0x02 1430 #define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02 1431 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 0x01 1432 #define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01 1433 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0x00 1434 1435 /* Registers for function PMU_CONTROL */ 1436 #define PALMAS_DEV_CTRL 0x00 1437 #define PALMAS_POWER_CTRL 0x01 1438 #define PALMAS_VSYS_LO 0x02 1439 #define PALMAS_VSYS_MON 0x03 1440 #define PALMAS_VBAT_MON 0x04 1441 #define PALMAS_WATCHDOG 0x05 1442 #define PALMAS_BOOT_STATUS 0x06 1443 #define PALMAS_BATTERY_BOUNCE 0x07 1444 #define PALMAS_BACKUP_BATTERY_CTRL 0x08 1445 #define PALMAS_LONG_PRESS_KEY 0x09 1446 #define PALMAS_OSC_THERM_CTRL 0x0A 1447 #define PALMAS_BATDEBOUNCING 0x0B 1448 #define PALMAS_SWOFF_HWRST 0x0F 1449 #define PALMAS_SWOFF_COLDRST 0x10 1450 #define PALMAS_SWOFF_STATUS 0x11 1451 #define PALMAS_PMU_CONFIG 0x12 1452 #define PALMAS_SPARE 0x14 1453 #define PALMAS_PMU_SECONDARY_INT 0x15 1454 #define PALMAS_SW_REVISION 0x17 1455 #define PALMAS_EXT_CHRG_CTRL 0x18 1456 #define PALMAS_PMU_SECONDARY_INT2 0x19 1457 1458 /* Bit definitions for DEV_CTRL */ 1459 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c 1460 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 0x02 1461 #define PALMAS_DEV_CTRL_SW_RST 0x02 1462 #define PALMAS_DEV_CTRL_SW_RST_SHIFT 0x01 1463 #define PALMAS_DEV_CTRL_DEV_ON 0x01 1464 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0x00 1465 1466 /* Bit definitions for POWER_CTRL */ 1467 #define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04 1468 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 0x02 1469 #define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02 1470 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 0x01 1471 #define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01 1472 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0x00 1473 1474 /* Bit definitions for VSYS_LO */ 1475 #define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1F 1476 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0x00 1477 1478 /* Bit definitions for VSYS_MON */ 1479 #define PALMAS_VSYS_MON_ENABLE 0x80 1480 #define PALMAS_VSYS_MON_ENABLE_SHIFT 0x07 1481 #define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3F 1482 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0x00 1483 1484 /* Bit definitions for VBAT_MON */ 1485 #define PALMAS_VBAT_MON_ENABLE 0x80 1486 #define PALMAS_VBAT_MON_ENABLE_SHIFT 0x07 1487 #define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3F 1488 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0x00 1489 1490 /* Bit definitions for WATCHDOG */ 1491 #define PALMAS_WATCHDOG_LOCK 0x20 1492 #define PALMAS_WATCHDOG_LOCK_SHIFT 0x05 1493 #define PALMAS_WATCHDOG_ENABLE 0x10 1494 #define PALMAS_WATCHDOG_ENABLE_SHIFT 0x04 1495 #define PALMAS_WATCHDOG_MODE 0x08 1496 #define PALMAS_WATCHDOG_MODE_SHIFT 0x03 1497 #define PALMAS_WATCHDOG_TIMER_MASK 0x07 1498 #define PALMAS_WATCHDOG_TIMER_SHIFT 0x00 1499 1500 /* Bit definitions for BOOT_STATUS */ 1501 #define PALMAS_BOOT_STATUS_BOOT1 0x02 1502 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT 0x01 1503 #define PALMAS_BOOT_STATUS_BOOT0 0x01 1504 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0x00 1505 1506 /* Bit definitions for BATTERY_BOUNCE */ 1507 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3F 1508 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0x00 1509 1510 /* Bit definitions for BACKUP_BATTERY_CTRL */ 1511 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80 1512 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 0x07 1513 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40 1514 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 0x06 1515 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20 1516 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 0x05 1517 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10 1518 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 0x04 1519 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08 1520 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 0x03 1521 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06 1522 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 0x01 1523 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01 1524 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0x00 1525 1526 /* Bit definitions for LONG_PRESS_KEY */ 1527 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80 1528 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 0x07 1529 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10 1530 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 0x04 1531 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c 1532 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 0x02 1533 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03 1534 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0x00 1535 1536 /* Bit definitions for OSC_THERM_CTRL */ 1537 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80 1538 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 0x07 1539 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40 1540 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 0x06 1541 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20 1542 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 0x05 1543 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10 1544 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 0x04 1545 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c 1546 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 0x02 1547 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02 1548 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 0x01 1549 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01 1550 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0x00 1551 1552 /* Bit definitions for BATDEBOUNCING */ 1553 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80 1554 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 0x07 1555 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78 1556 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 0x03 1557 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07 1558 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0x00 1559 1560 /* Bit definitions for SWOFF_HWRST */ 1561 #define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80 1562 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 0x07 1563 #define PALMAS_SWOFF_HWRST_PWRDOWN 0x40 1564 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 0x06 1565 #define PALMAS_SWOFF_HWRST_WTD 0x20 1566 #define PALMAS_SWOFF_HWRST_WTD_SHIFT 0x05 1567 #define PALMAS_SWOFF_HWRST_TSHUT 0x10 1568 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 0x04 1569 #define PALMAS_SWOFF_HWRST_RESET_IN 0x08 1570 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 0x03 1571 #define PALMAS_SWOFF_HWRST_SW_RST 0x04 1572 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 0x02 1573 #define PALMAS_SWOFF_HWRST_VSYS_LO 0x02 1574 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 0x01 1575 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01 1576 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0x00 1577 1578 /* Bit definitions for SWOFF_COLDRST */ 1579 #define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80 1580 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 0x07 1581 #define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40 1582 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 0x06 1583 #define PALMAS_SWOFF_COLDRST_WTD 0x20 1584 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT 0x05 1585 #define PALMAS_SWOFF_COLDRST_TSHUT 0x10 1586 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 0x04 1587 #define PALMAS_SWOFF_COLDRST_RESET_IN 0x08 1588 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 0x03 1589 #define PALMAS_SWOFF_COLDRST_SW_RST 0x04 1590 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 0x02 1591 #define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02 1592 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 0x01 1593 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01 1594 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0x00 1595 1596 /* Bit definitions for SWOFF_STATUS */ 1597 #define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80 1598 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 0x07 1599 #define PALMAS_SWOFF_STATUS_PWRDOWN 0x40 1600 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 0x06 1601 #define PALMAS_SWOFF_STATUS_WTD 0x20 1602 #define PALMAS_SWOFF_STATUS_WTD_SHIFT 0x05 1603 #define PALMAS_SWOFF_STATUS_TSHUT 0x10 1604 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 0x04 1605 #define PALMAS_SWOFF_STATUS_RESET_IN 0x08 1606 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 0x03 1607 #define PALMAS_SWOFF_STATUS_SW_RST 0x04 1608 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 0x02 1609 #define PALMAS_SWOFF_STATUS_VSYS_LO 0x02 1610 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 0x01 1611 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01 1612 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0x00 1613 1614 /* Bit definitions for PMU_CONFIG */ 1615 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40 1616 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 0x06 1617 #define PALMAS_PMU_CONFIG_SPARE_MASK 0x30 1618 #define PALMAS_PMU_CONFIG_SPARE_SHIFT 0x04 1619 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c 1620 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 0x02 1621 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02 1622 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 0x01 1623 #define PALMAS_PMU_CONFIG_AUTODEVON 0x01 1624 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0x00 1625 1626 /* Bit definitions for SPARE */ 1627 #define PALMAS_SPARE_SPARE_MASK 0xf8 1628 #define PALMAS_SPARE_SPARE_SHIFT 0x03 1629 #define PALMAS_SPARE_REGEN3_OD 0x04 1630 #define PALMAS_SPARE_REGEN3_OD_SHIFT 0x02 1631 #define PALMAS_SPARE_REGEN2_OD 0x02 1632 #define PALMAS_SPARE_REGEN2_OD_SHIFT 0x01 1633 #define PALMAS_SPARE_REGEN1_OD 0x01 1634 #define PALMAS_SPARE_REGEN1_OD_SHIFT 0x00 1635 1636 /* Bit definitions for PMU_SECONDARY_INT */ 1637 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80 1638 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 0x07 1639 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40 1640 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 0x06 1641 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20 1642 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 0x05 1643 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10 1644 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 0x04 1645 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08 1646 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 0x03 1647 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04 1648 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 0x02 1649 #define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02 1650 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 0x01 1651 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01 1652 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0x00 1653 1654 /* Bit definitions for SW_REVISION */ 1655 #define PALMAS_SW_REVISION_SW_REVISION_MASK 0xFF 1656 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0x00 1657 1658 /* Bit definitions for EXT_CHRG_CTRL */ 1659 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80 1660 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 0x07 1661 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40 1662 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 0x06 1663 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08 1664 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 0x03 1665 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04 1666 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 0x02 1667 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02 1668 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 0x01 1669 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01 1670 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0x00 1671 1672 /* Bit definitions for PMU_SECONDARY_INT2 */ 1673 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20 1674 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 0x05 1675 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10 1676 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 0x04 1677 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02 1678 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 0x01 1679 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01 1680 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0x00 1681 1682 /* Registers for function RESOURCE */ 1683 #define PALMAS_CLK32KG_CTRL 0x00 1684 #define PALMAS_CLK32KGAUDIO_CTRL 0x01 1685 #define PALMAS_REGEN1_CTRL 0x02 1686 #define PALMAS_REGEN2_CTRL 0x03 1687 #define PALMAS_SYSEN1_CTRL 0x04 1688 #define PALMAS_SYSEN2_CTRL 0x05 1689 #define PALMAS_NSLEEP_RES_ASSIGN 0x06 1690 #define PALMAS_NSLEEP_SMPS_ASSIGN 0x07 1691 #define PALMAS_NSLEEP_LDO_ASSIGN1 0x08 1692 #define PALMAS_NSLEEP_LDO_ASSIGN2 0x09 1693 #define PALMAS_ENABLE1_RES_ASSIGN 0x0A 1694 #define PALMAS_ENABLE1_SMPS_ASSIGN 0x0B 1695 #define PALMAS_ENABLE1_LDO_ASSIGN1 0x0C 1696 #define PALMAS_ENABLE1_LDO_ASSIGN2 0x0D 1697 #define PALMAS_ENABLE2_RES_ASSIGN 0x0E 1698 #define PALMAS_ENABLE2_SMPS_ASSIGN 0x0F 1699 #define PALMAS_ENABLE2_LDO_ASSIGN1 0x10 1700 #define PALMAS_ENABLE2_LDO_ASSIGN2 0x11 1701 #define PALMAS_REGEN3_CTRL 0x12 1702 1703 /* Bit definitions for CLK32KG_CTRL */ 1704 #define PALMAS_CLK32KG_CTRL_STATUS 0x10 1705 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 0x04 1706 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04 1707 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 0x02 1708 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01 1709 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0x00 1710 1711 /* Bit definitions for CLK32KGAUDIO_CTRL */ 1712 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10 1713 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 0x04 1714 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08 1715 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 0x03 1716 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04 1717 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 0x02 1718 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01 1719 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0x00 1720 1721 /* Bit definitions for REGEN1_CTRL */ 1722 #define PALMAS_REGEN1_CTRL_STATUS 0x10 1723 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT 0x04 1724 #define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04 1725 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02 1726 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01 1727 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 1728 1729 /* Bit definitions for REGEN2_CTRL */ 1730 #define PALMAS_REGEN2_CTRL_STATUS 0x10 1731 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT 0x04 1732 #define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04 1733 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02 1734 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01 1735 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 1736 1737 /* Bit definitions for SYSEN1_CTRL */ 1738 #define PALMAS_SYSEN1_CTRL_STATUS 0x10 1739 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 0x04 1740 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04 1741 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 0x02 1742 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01 1743 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 1744 1745 /* Bit definitions for SYSEN2_CTRL */ 1746 #define PALMAS_SYSEN2_CTRL_STATUS 0x10 1747 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 0x04 1748 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04 1749 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 0x02 1750 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01 1751 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 1752 1753 /* Bit definitions for NSLEEP_RES_ASSIGN */ 1754 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40 1755 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x06 1756 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20 1757 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05 1758 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10 1759 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 0x04 1760 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08 1761 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 0x03 1762 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04 1763 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 0x02 1764 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02 1765 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01 1766 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01 1767 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00 1768 1769 /* Bit definitions for NSLEEP_SMPS_ASSIGN */ 1770 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80 1771 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 0x07 1772 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40 1773 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 0x06 1774 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20 1775 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 0x05 1776 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10 1777 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 0x04 1778 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08 1779 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 0x03 1780 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04 1781 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 0x02 1782 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02 1783 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x01 1784 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01 1785 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0x00 1786 1787 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */ 1788 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80 1789 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 0x07 1790 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40 1791 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 0x06 1792 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20 1793 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 0x05 1794 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10 1795 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 0x04 1796 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08 1797 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x03 1798 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04 1799 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 0x02 1800 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02 1801 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01 1802 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01 1803 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00 1804 1805 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */ 1806 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04 1807 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 0x02 1808 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02 1809 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 0x01 1810 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01 1811 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0x00 1812 1813 /* Bit definitions for ENABLE1_RES_ASSIGN */ 1814 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40 1815 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x06 1816 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20 1817 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05 1818 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10 1819 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 0x04 1820 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08 1821 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 0x03 1822 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04 1823 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 0x02 1824 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02 1825 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01 1826 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01 1827 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00 1828 1829 /* Bit definitions for ENABLE1_SMPS_ASSIGN */ 1830 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80 1831 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 0x07 1832 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40 1833 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 0x06 1834 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20 1835 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 0x05 1836 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10 1837 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 0x04 1838 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08 1839 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 0x03 1840 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04 1841 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 0x02 1842 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02 1843 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x01 1844 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01 1845 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0x00 1846 1847 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */ 1848 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80 1849 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 0x07 1850 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40 1851 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 0x06 1852 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20 1853 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 0x05 1854 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10 1855 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 0x04 1856 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08 1857 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x03 1858 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04 1859 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 0x02 1860 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02 1861 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01 1862 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01 1863 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00 1864 1865 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */ 1866 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04 1867 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 0x02 1868 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02 1869 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 0x01 1870 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01 1871 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0x00 1872 1873 /* Bit definitions for ENABLE2_RES_ASSIGN */ 1874 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40 1875 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x06 1876 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20 1877 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05 1878 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10 1879 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 0x04 1880 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08 1881 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 0x03 1882 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04 1883 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 0x02 1884 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02 1885 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01 1886 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01 1887 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00 1888 1889 /* Bit definitions for ENABLE2_SMPS_ASSIGN */ 1890 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80 1891 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 0x07 1892 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40 1893 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 0x06 1894 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20 1895 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 0x05 1896 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10 1897 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 0x04 1898 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08 1899 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 0x03 1900 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04 1901 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 0x02 1902 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02 1903 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x01 1904 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01 1905 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0x00 1906 1907 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */ 1908 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80 1909 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 0x07 1910 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40 1911 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 0x06 1912 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20 1913 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 0x05 1914 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10 1915 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 0x04 1916 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08 1917 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x03 1918 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04 1919 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 0x02 1920 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02 1921 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01 1922 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01 1923 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00 1924 1925 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */ 1926 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04 1927 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 0x02 1928 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02 1929 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 0x01 1930 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01 1931 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0x00 1932 1933 /* Bit definitions for REGEN3_CTRL */ 1934 #define PALMAS_REGEN3_CTRL_STATUS 0x10 1935 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT 0x04 1936 #define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04 1937 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02 1938 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01 1939 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00 1940 1941 /* Registers for function PAD_CONTROL */ 1942 #define PALMAS_OD_OUTPUT_CTRL2 0x02 1943 #define PALMAS_POLARITY_CTRL2 0x03 1944 #define PALMAS_PU_PD_INPUT_CTRL1 0x04 1945 #define PALMAS_PU_PD_INPUT_CTRL2 0x05 1946 #define PALMAS_PU_PD_INPUT_CTRL3 0x06 1947 #define PALMAS_PU_PD_INPUT_CTRL5 0x07 1948 #define PALMAS_OD_OUTPUT_CTRL 0x08 1949 #define PALMAS_POLARITY_CTRL 0x09 1950 #define PALMAS_PRIMARY_SECONDARY_PAD1 0x0A 1951 #define PALMAS_PRIMARY_SECONDARY_PAD2 0x0B 1952 #define PALMAS_I2C_SPI 0x0C 1953 #define PALMAS_PU_PD_INPUT_CTRL4 0x0D 1954 #define PALMAS_PRIMARY_SECONDARY_PAD3 0x0E 1955 #define PALMAS_PRIMARY_SECONDARY_PAD4 0x0F 1956 1957 /* Bit definitions for PU_PD_INPUT_CTRL1 */ 1958 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40 1959 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 0x06 1960 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20 1961 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 0x05 1962 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10 1963 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 0x04 1964 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04 1965 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 0x02 1966 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02 1967 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 0x01 1968 1969 /* Bit definitions for PU_PD_INPUT_CTRL2 */ 1970 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20 1971 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 0x05 1972 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10 1973 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 0x04 1974 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08 1975 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 0x03 1976 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04 1977 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 0x02 1978 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02 1979 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 0x01 1980 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01 1981 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0x00 1982 1983 /* Bit definitions for PU_PD_INPUT_CTRL3 */ 1984 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40 1985 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 0x06 1986 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10 1987 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 0x04 1988 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04 1989 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 0x02 1990 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01 1991 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0x00 1992 1993 /* Bit definitions for OD_OUTPUT_CTRL */ 1994 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80 1995 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 0x07 1996 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40 1997 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 0x06 1998 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20 1999 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 0x05 2000 #define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08 2001 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 0x03 2002 2003 /* Bit definitions for POLARITY_CTRL */ 2004 #define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80 2005 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 0x07 2006 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40 2007 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 0x06 2008 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20 2009 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 0x05 2010 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10 2011 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 0x04 2012 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08 2013 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 0x03 2014 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04 2015 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 0x02 2016 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02 2017 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 0x01 2018 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01 2019 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0x00 2020 2021 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */ 2022 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80 2023 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 0x07 2024 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60 2025 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 0x05 2026 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18 2027 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 0x03 2028 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04 2029 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 0x02 2030 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02 2031 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 0x01 2032 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01 2033 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0x00 2034 2035 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */ 2036 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30 2037 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 0x04 2038 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08 2039 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 0x03 2040 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06 2041 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 0x01 2042 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01 2043 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0x00 2044 2045 /* Bit definitions for I2C_SPI */ 2046 #define PALMAS_I2C_SPI_I2C2OTP_EN 0x80 2047 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 0x07 2048 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40 2049 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 0x06 2050 #define PALMAS_I2C_SPI_ID_I2C2 0x20 2051 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT 0x05 2052 #define PALMAS_I2C_SPI_I2C_SPI 0x10 2053 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT 0x04 2054 #define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0F 2055 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0x00 2056 2057 /* Bit definitions for PU_PD_INPUT_CTRL4 */ 2058 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40 2059 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 0x06 2060 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10 2061 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 0x04 2062 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04 2063 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 0x02 2064 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01 2065 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0x00 2066 2067 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */ 2068 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02 2069 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 0x01 2070 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01 2071 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0x00 2072 2073 /* Registers for function LED_PWM */ 2074 #define PALMAS_LED_PERIOD_CTRL 0x00 2075 #define PALMAS_LED_CTRL 0x01 2076 #define PALMAS_PWM_CTRL1 0x02 2077 #define PALMAS_PWM_CTRL2 0x03 2078 2079 /* Bit definitions for LED_PERIOD_CTRL */ 2080 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38 2081 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 0x03 2082 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07 2083 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0x00 2084 2085 /* Bit definitions for LED_CTRL */ 2086 #define PALMAS_LED_CTRL_LED_2_SEQ 0x20 2087 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 0x05 2088 #define PALMAS_LED_CTRL_LED_1_SEQ 0x10 2089 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 0x04 2090 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c 2091 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 0x02 2092 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03 2093 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0x00 2094 2095 /* Bit definitions for PWM_CTRL1 */ 2096 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02 2097 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 0x01 2098 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01 2099 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0x00 2100 2101 /* Bit definitions for PWM_CTRL2 */ 2102 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xFF 2103 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0x00 2104 2105 /* Registers for function INTERRUPT */ 2106 #define PALMAS_INT1_STATUS 0x00 2107 #define PALMAS_INT1_MASK 0x01 2108 #define PALMAS_INT1_LINE_STATE 0x02 2109 #define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x03 2110 #define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x04 2111 #define PALMAS_INT2_STATUS 0x05 2112 #define PALMAS_INT2_MASK 0x06 2113 #define PALMAS_INT2_LINE_STATE 0x07 2114 #define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x08 2115 #define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x09 2116 #define PALMAS_INT3_STATUS 0x0A 2117 #define PALMAS_INT3_MASK 0x0B 2118 #define PALMAS_INT3_LINE_STATE 0x0C 2119 #define PALMAS_INT3_EDGE_DETECT1_RESERVED 0x0D 2120 #define PALMAS_INT3_EDGE_DETECT2_RESERVED 0x0E 2121 #define PALMAS_INT4_STATUS 0x0F 2122 #define PALMAS_INT4_MASK 0x10 2123 #define PALMAS_INT4_LINE_STATE 0x11 2124 #define PALMAS_INT4_EDGE_DETECT1 0x12 2125 #define PALMAS_INT4_EDGE_DETECT2 0x13 2126 #define PALMAS_INT_CTRL 0x14 2127 2128 /* Bit definitions for INT1_STATUS */ 2129 #define PALMAS_INT1_STATUS_VBAT_MON 0x80 2130 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 0x07 2131 #define PALMAS_INT1_STATUS_VSYS_MON 0x40 2132 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 0x06 2133 #define PALMAS_INT1_STATUS_HOTDIE 0x20 2134 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT 0x05 2135 #define PALMAS_INT1_STATUS_PWRDOWN 0x10 2136 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 0x04 2137 #define PALMAS_INT1_STATUS_RPWRON 0x08 2138 #define PALMAS_INT1_STATUS_RPWRON_SHIFT 0x03 2139 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04 2140 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02 2141 #define PALMAS_INT1_STATUS_PWRON 0x02 2142 #define PALMAS_INT1_STATUS_PWRON_SHIFT 0x01 2143 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01 2144 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0x00 2145 2146 /* Bit definitions for INT1_MASK */ 2147 #define PALMAS_INT1_MASK_VBAT_MON 0x80 2148 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT 0x07 2149 #define PALMAS_INT1_MASK_VSYS_MON 0x40 2150 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT 0x06 2151 #define PALMAS_INT1_MASK_HOTDIE 0x20 2152 #define PALMAS_INT1_MASK_HOTDIE_SHIFT 0x05 2153 #define PALMAS_INT1_MASK_PWRDOWN 0x10 2154 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT 0x04 2155 #define PALMAS_INT1_MASK_RPWRON 0x08 2156 #define PALMAS_INT1_MASK_RPWRON_SHIFT 0x03 2157 #define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04 2158 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02 2159 #define PALMAS_INT1_MASK_PWRON 0x02 2160 #define PALMAS_INT1_MASK_PWRON_SHIFT 0x01 2161 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01 2162 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0x00 2163 2164 /* Bit definitions for INT1_LINE_STATE */ 2165 #define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80 2166 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 0x07 2167 #define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40 2168 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06 2169 #define PALMAS_INT1_LINE_STATE_HOTDIE 0x20 2170 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 0x05 2171 #define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10 2172 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04 2173 #define PALMAS_INT1_LINE_STATE_RPWRON 0x08 2174 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 0x03 2175 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 2176 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02 2177 #define PALMAS_INT1_LINE_STATE_PWRON 0x02 2178 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 0x01 2179 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01 2180 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0x00 2181 2182 /* Bit definitions for INT2_STATUS */ 2183 #define PALMAS_INT2_STATUS_VAC_ACOK 0x80 2184 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 0x07 2185 #define PALMAS_INT2_STATUS_SHORT 0x40 2186 #define PALMAS_INT2_STATUS_SHORT_SHIFT 0x06 2187 #define PALMAS_INT2_STATUS_FBI_BB 0x20 2188 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT 0x05 2189 #define PALMAS_INT2_STATUS_RESET_IN 0x10 2190 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT 0x04 2191 #define PALMAS_INT2_STATUS_BATREMOVAL 0x08 2192 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 0x03 2193 #define PALMAS_INT2_STATUS_WDT 0x04 2194 #define PALMAS_INT2_STATUS_WDT_SHIFT 0x02 2195 #define PALMAS_INT2_STATUS_RTC_TIMER 0x02 2196 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 0x01 2197 #define PALMAS_INT2_STATUS_RTC_ALARM 0x01 2198 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0x00 2199 2200 /* Bit definitions for INT2_MASK */ 2201 #define PALMAS_INT2_MASK_VAC_ACOK 0x80 2202 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 0x07 2203 #define PALMAS_INT2_MASK_SHORT 0x40 2204 #define PALMAS_INT2_MASK_SHORT_SHIFT 0x06 2205 #define PALMAS_INT2_MASK_FBI_BB 0x20 2206 #define PALMAS_INT2_MASK_FBI_BB_SHIFT 0x05 2207 #define PALMAS_INT2_MASK_RESET_IN 0x10 2208 #define PALMAS_INT2_MASK_RESET_IN_SHIFT 0x04 2209 #define PALMAS_INT2_MASK_BATREMOVAL 0x08 2210 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 0x03 2211 #define PALMAS_INT2_MASK_WDT 0x04 2212 #define PALMAS_INT2_MASK_WDT_SHIFT 0x02 2213 #define PALMAS_INT2_MASK_RTC_TIMER 0x02 2214 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 0x01 2215 #define PALMAS_INT2_MASK_RTC_ALARM 0x01 2216 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0x00 2217 2218 /* Bit definitions for INT2_LINE_STATE */ 2219 #define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80 2220 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 0x07 2221 #define PALMAS_INT2_LINE_STATE_SHORT 0x40 2222 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 0x06 2223 #define PALMAS_INT2_LINE_STATE_FBI_BB 0x20 2224 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 0x05 2225 #define PALMAS_INT2_LINE_STATE_RESET_IN 0x10 2226 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 0x04 2227 #define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08 2228 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 0x03 2229 #define PALMAS_INT2_LINE_STATE_WDT 0x04 2230 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT 0x02 2231 #define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02 2232 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 0x01 2233 #define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01 2234 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0x00 2235 2236 /* Bit definitions for INT3_STATUS */ 2237 #define PALMAS_INT3_STATUS_VBUS 0x80 2238 #define PALMAS_INT3_STATUS_VBUS_SHIFT 0x07 2239 #define PALMAS_INT3_STATUS_VBUS_OTG 0x40 2240 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 0x06 2241 #define PALMAS_INT3_STATUS_ID 0x20 2242 #define PALMAS_INT3_STATUS_ID_SHIFT 0x05 2243 #define PALMAS_INT3_STATUS_ID_OTG 0x10 2244 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT 0x04 2245 #define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08 2246 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 0x03 2247 #define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04 2248 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02 2249 #define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02 2250 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01 2251 #define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01 2252 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00 2253 2254 /* Bit definitions for INT3_MASK */ 2255 #define PALMAS_INT3_MASK_VBUS 0x80 2256 #define PALMAS_INT3_MASK_VBUS_SHIFT 0x07 2257 #define PALMAS_INT3_MASK_VBUS_OTG 0x40 2258 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 0x06 2259 #define PALMAS_INT3_MASK_ID 0x20 2260 #define PALMAS_INT3_MASK_ID_SHIFT 0x05 2261 #define PALMAS_INT3_MASK_ID_OTG 0x10 2262 #define PALMAS_INT3_MASK_ID_OTG_SHIFT 0x04 2263 #define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08 2264 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 0x03 2265 #define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04 2266 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02 2267 #define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02 2268 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01 2269 #define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01 2270 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00 2271 2272 /* Bit definitions for INT3_LINE_STATE */ 2273 #define PALMAS_INT3_LINE_STATE_VBUS 0x80 2274 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 0x07 2275 #define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40 2276 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 0x06 2277 #define PALMAS_INT3_LINE_STATE_ID 0x20 2278 #define PALMAS_INT3_LINE_STATE_ID_SHIFT 0x05 2279 #define PALMAS_INT3_LINE_STATE_ID_OTG 0x10 2280 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 0x04 2281 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08 2282 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 0x03 2283 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04 2284 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02 2285 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02 2286 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01 2287 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01 2288 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00 2289 2290 /* Bit definitions for INT4_STATUS */ 2291 #define PALMAS_INT4_STATUS_GPIO_7 0x80 2292 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT 0x07 2293 #define PALMAS_INT4_STATUS_GPIO_6 0x40 2294 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT 0x06 2295 #define PALMAS_INT4_STATUS_GPIO_5 0x20 2296 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT 0x05 2297 #define PALMAS_INT4_STATUS_GPIO_4 0x10 2298 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT 0x04 2299 #define PALMAS_INT4_STATUS_GPIO_3 0x08 2300 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT 0x03 2301 #define PALMAS_INT4_STATUS_GPIO_2 0x04 2302 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT 0x02 2303 #define PALMAS_INT4_STATUS_GPIO_1 0x02 2304 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT 0x01 2305 #define PALMAS_INT4_STATUS_GPIO_0 0x01 2306 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0x00 2307 2308 /* Bit definitions for INT4_MASK */ 2309 #define PALMAS_INT4_MASK_GPIO_7 0x80 2310 #define PALMAS_INT4_MASK_GPIO_7_SHIFT 0x07 2311 #define PALMAS_INT4_MASK_GPIO_6 0x40 2312 #define PALMAS_INT4_MASK_GPIO_6_SHIFT 0x06 2313 #define PALMAS_INT4_MASK_GPIO_5 0x20 2314 #define PALMAS_INT4_MASK_GPIO_5_SHIFT 0x05 2315 #define PALMAS_INT4_MASK_GPIO_4 0x10 2316 #define PALMAS_INT4_MASK_GPIO_4_SHIFT 0x04 2317 #define PALMAS_INT4_MASK_GPIO_3 0x08 2318 #define PALMAS_INT4_MASK_GPIO_3_SHIFT 0x03 2319 #define PALMAS_INT4_MASK_GPIO_2 0x04 2320 #define PALMAS_INT4_MASK_GPIO_2_SHIFT 0x02 2321 #define PALMAS_INT4_MASK_GPIO_1 0x02 2322 #define PALMAS_INT4_MASK_GPIO_1_SHIFT 0x01 2323 #define PALMAS_INT4_MASK_GPIO_0 0x01 2324 #define PALMAS_INT4_MASK_GPIO_0_SHIFT 0x00 2325 2326 /* Bit definitions for INT4_LINE_STATE */ 2327 #define PALMAS_INT4_LINE_STATE_GPIO_7 0x80 2328 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 0x07 2329 #define PALMAS_INT4_LINE_STATE_GPIO_6 0x40 2330 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 0x06 2331 #define PALMAS_INT4_LINE_STATE_GPIO_5 0x20 2332 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 0x05 2333 #define PALMAS_INT4_LINE_STATE_GPIO_4 0x10 2334 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 0x04 2335 #define PALMAS_INT4_LINE_STATE_GPIO_3 0x08 2336 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 0x03 2337 #define PALMAS_INT4_LINE_STATE_GPIO_2 0x04 2338 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 0x02 2339 #define PALMAS_INT4_LINE_STATE_GPIO_1 0x02 2340 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 0x01 2341 #define PALMAS_INT4_LINE_STATE_GPIO_0 0x01 2342 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0x00 2343 2344 /* Bit definitions for INT4_EDGE_DETECT1 */ 2345 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 2346 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07 2347 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 2348 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06 2349 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 2350 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05 2351 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 2352 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04 2353 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 2354 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03 2355 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 2356 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02 2357 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 2358 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01 2359 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 2360 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00 2361 2362 /* Bit definitions for INT4_EDGE_DETECT2 */ 2363 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80 2364 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 0x07 2365 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40 2366 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 0x06 2367 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 2368 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05 2369 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 2370 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04 2371 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 2372 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03 2373 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 2374 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02 2375 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 2376 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01 2377 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 2378 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00 2379 2380 /* Bit definitions for INT_CTRL */ 2381 #define PALMAS_INT_CTRL_INT_PENDING 0x04 2382 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT 0x02 2383 #define PALMAS_INT_CTRL_INT_CLEAR 0x01 2384 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0x00 2385 2386 /* Registers for function USB_OTG */ 2387 #define PALMAS_USB_WAKEUP 0x03 2388 #define PALMAS_USB_VBUS_CTRL_SET 0x04 2389 #define PALMAS_USB_VBUS_CTRL_CLR 0x05 2390 #define PALMAS_USB_ID_CTRL_SET 0x06 2391 #define PALMAS_USB_ID_CTRL_CLEAR 0x07 2392 #define PALMAS_USB_VBUS_INT_SRC 0x08 2393 #define PALMAS_USB_VBUS_INT_LATCH_SET 0x09 2394 #define PALMAS_USB_VBUS_INT_LATCH_CLR 0x0A 2395 #define PALMAS_USB_VBUS_INT_EN_LO_SET 0x0B 2396 #define PALMAS_USB_VBUS_INT_EN_LO_CLR 0x0C 2397 #define PALMAS_USB_VBUS_INT_EN_HI_SET 0x0D 2398 #define PALMAS_USB_VBUS_INT_EN_HI_CLR 0x0E 2399 #define PALMAS_USB_ID_INT_SRC 0x0F 2400 #define PALMAS_USB_ID_INT_LATCH_SET 0x10 2401 #define PALMAS_USB_ID_INT_LATCH_CLR 0x11 2402 #define PALMAS_USB_ID_INT_EN_LO_SET 0x12 2403 #define PALMAS_USB_ID_INT_EN_LO_CLR 0x13 2404 #define PALMAS_USB_ID_INT_EN_HI_SET 0x14 2405 #define PALMAS_USB_ID_INT_EN_HI_CLR 0x15 2406 #define PALMAS_USB_OTG_ADP_CTRL 0x16 2407 #define PALMAS_USB_OTG_ADP_HIGH 0x17 2408 #define PALMAS_USB_OTG_ADP_LOW 0x18 2409 #define PALMAS_USB_OTG_ADP_RISE 0x19 2410 #define PALMAS_USB_OTG_REVISION 0x1A 2411 2412 /* Bit definitions for USB_WAKEUP */ 2413 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01 2414 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0x00 2415 2416 /* Bit definitions for USB_VBUS_CTRL_SET */ 2417 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80 2418 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 0x07 2419 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20 2420 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 0x05 2421 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10 2422 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 0x04 2423 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08 2424 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 0x03 2425 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04 2426 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 0x02 2427 2428 /* Bit definitions for USB_VBUS_CTRL_CLR */ 2429 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80 2430 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 0x07 2431 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20 2432 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 0x05 2433 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10 2434 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 0x04 2435 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08 2436 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 0x03 2437 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04 2438 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 0x02 2439 2440 /* Bit definitions for USB_ID_CTRL_SET */ 2441 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80 2442 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 0x07 2443 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40 2444 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 0x06 2445 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20 2446 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 0x05 2447 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10 2448 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 0x04 2449 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08 2450 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 0x03 2451 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04 2452 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 0x02 2453 2454 /* Bit definitions for USB_ID_CTRL_CLEAR */ 2455 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80 2456 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 0x07 2457 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40 2458 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 0x06 2459 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20 2460 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 0x05 2461 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10 2462 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 0x04 2463 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08 2464 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 0x03 2465 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04 2466 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 0x02 2467 2468 /* Bit definitions for USB_VBUS_INT_SRC */ 2469 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80 2470 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 0x07 2471 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40 2472 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 0x06 2473 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20 2474 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 0x05 2475 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08 2476 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 0x03 2477 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04 2478 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 0x02 2479 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02 2480 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 0x01 2481 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01 2482 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0x00 2483 2484 /* Bit definitions for USB_VBUS_INT_LATCH_SET */ 2485 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80 2486 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 0x07 2487 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40 2488 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 0x06 2489 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20 2490 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 0x05 2491 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10 2492 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 0x04 2493 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08 2494 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 0x03 2495 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04 2496 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 0x02 2497 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02 2498 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 0x01 2499 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01 2500 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0x00 2501 2502 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */ 2503 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80 2504 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 0x07 2505 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40 2506 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 0x06 2507 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20 2508 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 0x05 2509 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10 2510 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 0x04 2511 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08 2512 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 0x03 2513 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04 2514 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 0x02 2515 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02 2516 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 0x01 2517 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01 2518 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0x00 2519 2520 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */ 2521 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80 2522 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 0x07 2523 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40 2524 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 0x06 2525 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20 2526 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 0x05 2527 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08 2528 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 0x03 2529 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04 2530 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 0x02 2531 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02 2532 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 0x01 2533 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01 2534 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0x00 2535 2536 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */ 2537 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80 2538 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 0x07 2539 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40 2540 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 0x06 2541 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20 2542 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 0x05 2543 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08 2544 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 0x03 2545 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04 2546 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 0x02 2547 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02 2548 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 0x01 2549 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01 2550 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0x00 2551 2552 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */ 2553 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80 2554 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 0x07 2555 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40 2556 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 0x06 2557 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20 2558 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 0x05 2559 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10 2560 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 0x04 2561 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08 2562 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 0x03 2563 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04 2564 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 0x02 2565 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02 2566 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 0x01 2567 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01 2568 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0x00 2569 2570 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */ 2571 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80 2572 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 0x07 2573 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40 2574 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 0x06 2575 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20 2576 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 0x05 2577 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10 2578 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 0x04 2579 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08 2580 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 0x03 2581 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04 2582 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 0x02 2583 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02 2584 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 0x01 2585 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01 2586 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0x00 2587 2588 /* Bit definitions for USB_ID_INT_SRC */ 2589 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10 2590 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 0x04 2591 #define PALMAS_USB_ID_INT_SRC_ID_A 0x08 2592 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 0x03 2593 #define PALMAS_USB_ID_INT_SRC_ID_B 0x04 2594 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 0x02 2595 #define PALMAS_USB_ID_INT_SRC_ID_C 0x02 2596 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 0x01 2597 #define PALMAS_USB_ID_INT_SRC_ID_GND 0x01 2598 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0x00 2599 2600 /* Bit definitions for USB_ID_INT_LATCH_SET */ 2601 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10 2602 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 0x04 2603 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08 2604 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 0x03 2605 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04 2606 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 0x02 2607 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02 2608 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 0x01 2609 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01 2610 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0x00 2611 2612 /* Bit definitions for USB_ID_INT_LATCH_CLR */ 2613 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10 2614 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 0x04 2615 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08 2616 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 0x03 2617 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04 2618 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 0x02 2619 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02 2620 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 0x01 2621 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01 2622 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0x00 2623 2624 /* Bit definitions for USB_ID_INT_EN_LO_SET */ 2625 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10 2626 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 0x04 2627 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08 2628 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 0x03 2629 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04 2630 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 0x02 2631 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02 2632 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 0x01 2633 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01 2634 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0x00 2635 2636 /* Bit definitions for USB_ID_INT_EN_LO_CLR */ 2637 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10 2638 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 0x04 2639 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08 2640 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 0x03 2641 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04 2642 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 0x02 2643 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02 2644 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 0x01 2645 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01 2646 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0x00 2647 2648 /* Bit definitions for USB_ID_INT_EN_HI_SET */ 2649 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10 2650 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 0x04 2651 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08 2652 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 0x03 2653 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04 2654 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 0x02 2655 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02 2656 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 0x01 2657 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01 2658 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0x00 2659 2660 /* Bit definitions for USB_ID_INT_EN_HI_CLR */ 2661 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10 2662 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 0x04 2663 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08 2664 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 0x03 2665 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04 2666 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 0x02 2667 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02 2668 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 0x01 2669 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01 2670 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0x00 2671 2672 /* Bit definitions for USB_OTG_ADP_CTRL */ 2673 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04 2674 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 0x02 2675 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03 2676 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0x00 2677 2678 /* Bit definitions for USB_OTG_ADP_HIGH */ 2679 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xFF 2680 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0x00 2681 2682 /* Bit definitions for USB_OTG_ADP_LOW */ 2683 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xFF 2684 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0x00 2685 2686 /* Bit definitions for USB_OTG_ADP_RISE */ 2687 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xFF 2688 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0x00 2689 2690 /* Bit definitions for USB_OTG_REVISION */ 2691 #define PALMAS_USB_OTG_REVISION_OTG_REV 0x01 2692 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0x00 2693 2694 /* Registers for function VIBRATOR */ 2695 #define PALMAS_VIBRA_CTRL 0x00 2696 2697 /* Bit definitions for VIBRA_CTRL */ 2698 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06 2699 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 0x01 2700 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01 2701 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0x00 2702 2703 /* Registers for function GPIO */ 2704 #define PALMAS_GPIO_DATA_IN 0x00 2705 #define PALMAS_GPIO_DATA_DIR 0x01 2706 #define PALMAS_GPIO_DATA_OUT 0x02 2707 #define PALMAS_GPIO_DEBOUNCE_EN 0x03 2708 #define PALMAS_GPIO_CLEAR_DATA_OUT 0x04 2709 #define PALMAS_GPIO_SET_DATA_OUT 0x05 2710 #define PALMAS_PU_PD_GPIO_CTRL1 0x06 2711 #define PALMAS_PU_PD_GPIO_CTRL2 0x07 2712 #define PALMAS_OD_OUTPUT_GPIO_CTRL 0x08 2713 #define PALMAS_GPIO_DATA_IN2 0x09 2714 #define PALMAS_GPIO_DATA_DIR2 0x0A 2715 #define PALMAS_GPIO_DATA_OUT2 0x0B 2716 #define PALMAS_GPIO_DEBOUNCE_EN2 0x0C 2717 #define PALMAS_GPIO_CLEAR_DATA_OUT2 0x0D 2718 #define PALMAS_GPIO_SET_DATA_OUT2 0x0E 2719 #define PALMAS_PU_PD_GPIO_CTRL3 0x0F 2720 #define PALMAS_PU_PD_GPIO_CTRL4 0x10 2721 #define PALMAS_OD_OUTPUT_GPIO_CTRL2 0x11 2722 2723 /* Bit definitions for GPIO_DATA_IN */ 2724 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80 2725 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 0x07 2726 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40 2727 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 0x06 2728 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20 2729 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 0x05 2730 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10 2731 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 0x04 2732 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08 2733 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 0x03 2734 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04 2735 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 0x02 2736 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02 2737 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 0x01 2738 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01 2739 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0x00 2740 2741 /* Bit definitions for GPIO_DATA_DIR */ 2742 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80 2743 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 0x07 2744 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40 2745 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 0x06 2746 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20 2747 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 0x05 2748 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10 2749 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 0x04 2750 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08 2751 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 0x03 2752 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04 2753 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 0x02 2754 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02 2755 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 0x01 2756 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01 2757 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0x00 2758 2759 /* Bit definitions for GPIO_DATA_OUT */ 2760 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80 2761 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 0x07 2762 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40 2763 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 0x06 2764 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20 2765 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 0x05 2766 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10 2767 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 0x04 2768 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08 2769 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 0x03 2770 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04 2771 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 0x02 2772 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02 2773 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 0x01 2774 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01 2775 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0x00 2776 2777 /* Bit definitions for GPIO_DEBOUNCE_EN */ 2778 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80 2779 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 0x07 2780 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40 2781 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 0x06 2782 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20 2783 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 0x05 2784 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10 2785 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 0x04 2786 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08 2787 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 0x03 2788 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04 2789 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 0x02 2790 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02 2791 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 0x01 2792 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01 2793 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0x00 2794 2795 /* Bit definitions for GPIO_CLEAR_DATA_OUT */ 2796 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80 2797 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 0x07 2798 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40 2799 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 0x06 2800 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20 2801 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 0x05 2802 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10 2803 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 0x04 2804 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08 2805 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 0x03 2806 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04 2807 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 0x02 2808 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02 2809 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 0x01 2810 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01 2811 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0x00 2812 2813 /* Bit definitions for GPIO_SET_DATA_OUT */ 2814 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80 2815 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 0x07 2816 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40 2817 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 0x06 2818 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20 2819 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 0x05 2820 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10 2821 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 0x04 2822 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08 2823 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 0x03 2824 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04 2825 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 0x02 2826 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02 2827 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 0x01 2828 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01 2829 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0x00 2830 2831 /* Bit definitions for PU_PD_GPIO_CTRL1 */ 2832 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40 2833 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 0x06 2834 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20 2835 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 0x05 2836 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10 2837 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 0x04 2838 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08 2839 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 0x03 2840 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04 2841 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 0x02 2842 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01 2843 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0x00 2844 2845 /* Bit definitions for PU_PD_GPIO_CTRL2 */ 2846 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40 2847 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 0x06 2848 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20 2849 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 0x05 2850 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10 2851 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 0x04 2852 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08 2853 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 0x03 2854 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04 2855 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 0x02 2856 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02 2857 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 0x01 2858 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01 2859 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0x00 2860 2861 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */ 2862 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20 2863 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 0x05 2864 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04 2865 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 0x02 2866 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02 2867 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 0x01 2868 2869 /* Registers for function GPADC */ 2870 #define PALMAS_GPADC_CTRL1 0x00 2871 #define PALMAS_GPADC_CTRL2 0x01 2872 #define PALMAS_GPADC_RT_CTRL 0x02 2873 #define PALMAS_GPADC_AUTO_CTRL 0x03 2874 #define PALMAS_GPADC_STATUS 0x04 2875 #define PALMAS_GPADC_RT_SELECT 0x05 2876 #define PALMAS_GPADC_RT_CONV0_LSB 0x06 2877 #define PALMAS_GPADC_RT_CONV0_MSB 0x07 2878 #define PALMAS_GPADC_AUTO_SELECT 0x08 2879 #define PALMAS_GPADC_AUTO_CONV0_LSB 0x09 2880 #define PALMAS_GPADC_AUTO_CONV0_MSB 0x0A 2881 #define PALMAS_GPADC_AUTO_CONV1_LSB 0x0B 2882 #define PALMAS_GPADC_AUTO_CONV1_MSB 0x0C 2883 #define PALMAS_GPADC_SW_SELECT 0x0D 2884 #define PALMAS_GPADC_SW_CONV0_LSB 0x0E 2885 #define PALMAS_GPADC_SW_CONV0_MSB 0x0F 2886 #define PALMAS_GPADC_THRES_CONV0_LSB 0x10 2887 #define PALMAS_GPADC_THRES_CONV0_MSB 0x11 2888 #define PALMAS_GPADC_THRES_CONV1_LSB 0x12 2889 #define PALMAS_GPADC_THRES_CONV1_MSB 0x13 2890 #define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14 2891 #define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15 2892 2893 /* Bit definitions for GPADC_CTRL1 */ 2894 #define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0 2895 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 0x06 2896 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30 2897 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 0x04 2898 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c 2899 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 0x02 2900 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02 2901 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 0x01 2902 #define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01 2903 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0x00 2904 2905 /* Bit definitions for GPADC_CTRL2 */ 2906 #define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06 2907 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 0x01 2908 2909 /* Bit definitions for GPADC_RT_CTRL */ 2910 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02 2911 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 0x01 2912 #define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01 2913 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0x00 2914 2915 /* Bit definitions for GPADC_AUTO_CTRL */ 2916 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80 2917 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 0x07 2918 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40 2919 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 0x06 2920 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20 2921 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 0x05 2922 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10 2923 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 0x04 2924 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0F 2925 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0x00 2926 2927 /* Bit definitions for GPADC_STATUS */ 2928 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10 2929 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 0x04 2930 2931 /* Bit definitions for GPADC_RT_SELECT */ 2932 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80 2933 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 0x07 2934 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0F 2935 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0x00 2936 2937 /* Bit definitions for GPADC_RT_CONV0_LSB */ 2938 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xFF 2939 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0x00 2940 2941 /* Bit definitions for GPADC_RT_CONV0_MSB */ 2942 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0F 2943 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0x00 2944 2945 /* Bit definitions for GPADC_AUTO_SELECT */ 2946 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xF0 2947 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 0x04 2948 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0F 2949 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0x00 2950 2951 /* Bit definitions for GPADC_AUTO_CONV0_LSB */ 2952 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xFF 2953 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0x00 2954 2955 /* Bit definitions for GPADC_AUTO_CONV0_MSB */ 2956 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0F 2957 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0x00 2958 2959 /* Bit definitions for GPADC_AUTO_CONV1_LSB */ 2960 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xFF 2961 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0x00 2962 2963 /* Bit definitions for GPADC_AUTO_CONV1_MSB */ 2964 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0F 2965 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0x00 2966 2967 /* Bit definitions for GPADC_SW_SELECT */ 2968 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80 2969 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 0x07 2970 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10 2971 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 0x04 2972 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0F 2973 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0x00 2974 2975 /* Bit definitions for GPADC_SW_CONV0_LSB */ 2976 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xFF 2977 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0x00 2978 2979 /* Bit definitions for GPADC_SW_CONV0_MSB */ 2980 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0F 2981 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0x00 2982 2983 /* Bit definitions for GPADC_THRES_CONV0_LSB */ 2984 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xFF 2985 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0x00 2986 2987 /* Bit definitions for GPADC_THRES_CONV0_MSB */ 2988 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80 2989 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 0x07 2990 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0F 2991 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0x00 2992 2993 /* Bit definitions for GPADC_THRES_CONV1_LSB */ 2994 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xFF 2995 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0x00 2996 2997 /* Bit definitions for GPADC_THRES_CONV1_MSB */ 2998 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80 2999 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 0x07 3000 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0F 3001 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0x00 3002 3003 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */ 3004 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20 3005 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 0x05 3006 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10 3007 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 0x04 3008 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0F 3009 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0x00 3010 3011 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */ 3012 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80 3013 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 0x07 3014 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7F 3015 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0x00 3016 3017 /* Registers for function GPADC */ 3018 #define PALMAS_GPADC_TRIM1 0x00 3019 #define PALMAS_GPADC_TRIM2 0x01 3020 #define PALMAS_GPADC_TRIM3 0x02 3021 #define PALMAS_GPADC_TRIM4 0x03 3022 #define PALMAS_GPADC_TRIM5 0x04 3023 #define PALMAS_GPADC_TRIM6 0x05 3024 #define PALMAS_GPADC_TRIM7 0x06 3025 #define PALMAS_GPADC_TRIM8 0x07 3026 #define PALMAS_GPADC_TRIM9 0x08 3027 #define PALMAS_GPADC_TRIM10 0x09 3028 #define PALMAS_GPADC_TRIM11 0x0A 3029 #define PALMAS_GPADC_TRIM12 0x0B 3030 #define PALMAS_GPADC_TRIM13 0x0C 3031 #define PALMAS_GPADC_TRIM14 0x0D 3032 #define PALMAS_GPADC_TRIM15 0x0E 3033 #define PALMAS_GPADC_TRIM16 0x0F 3034 3035 /* TPS659038 regen2_ctrl offset iss different from palmas */ 3036 #define TPS659038_REGEN2_CTRL 0x12 3037 3038 /* TPS65917 Interrupt registers */ 3039 3040 /* Registers for function INTERRUPT */ 3041 #define TPS65917_INT1_STATUS 0x00 3042 #define TPS65917_INT1_MASK 0x01 3043 #define TPS65917_INT1_LINE_STATE 0x02 3044 #define TPS65917_INT2_STATUS 0x05 3045 #define TPS65917_INT2_MASK 0x06 3046 #define TPS65917_INT2_LINE_STATE 0x07 3047 #define TPS65917_INT3_STATUS 0x0A 3048 #define TPS65917_INT3_MASK 0x0B 3049 #define TPS65917_INT3_LINE_STATE 0x0C 3050 #define TPS65917_INT4_STATUS 0x0F 3051 #define TPS65917_INT4_MASK 0x10 3052 #define TPS65917_INT4_LINE_STATE 0x11 3053 #define TPS65917_INT4_EDGE_DETECT1 0x12 3054 #define TPS65917_INT4_EDGE_DETECT2 0x13 3055 #define TPS65917_INT_CTRL 0x14 3056 3057 /* Bit definitions for INT1_STATUS */ 3058 #define TPS65917_INT1_STATUS_VSYS_MON 0x40 3059 #define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06 3060 #define TPS65917_INT1_STATUS_HOTDIE 0x20 3061 #define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05 3062 #define TPS65917_INT1_STATUS_PWRDOWN 0x10 3063 #define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04 3064 #define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04 3065 #define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02 3066 #define TPS65917_INT1_STATUS_PWRON 0x02 3067 #define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01 3068 3069 /* Bit definitions for INT1_MASK */ 3070 #define TPS65917_INT1_MASK_VSYS_MON 0x40 3071 #define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06 3072 #define TPS65917_INT1_MASK_HOTDIE 0x20 3073 #define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05 3074 #define TPS65917_INT1_MASK_PWRDOWN 0x10 3075 #define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04 3076 #define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04 3077 #define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02 3078 #define TPS65917_INT1_MASK_PWRON 0x02 3079 #define TPS65917_INT1_MASK_PWRON_SHIFT 0x01 3080 3081 /* Bit definitions for INT1_LINE_STATE */ 3082 #define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40 3083 #define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06 3084 #define TPS65917_INT1_LINE_STATE_HOTDIE 0x20 3085 #define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05 3086 #define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10 3087 #define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04 3088 #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 3089 #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02 3090 #define TPS65917_INT1_LINE_STATE_PWRON 0x02 3091 #define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01 3092 3093 /* Bit definitions for INT2_STATUS */ 3094 #define TPS65917_INT2_STATUS_SHORT 0x40 3095 #define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06 3096 #define TPS65917_INT2_STATUS_FSD 0x20 3097 #define TPS65917_INT2_STATUS_FSD_SHIFT 0x05 3098 #define TPS65917_INT2_STATUS_RESET_IN 0x10 3099 #define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04 3100 #define TPS65917_INT2_STATUS_WDT 0x04 3101 #define TPS65917_INT2_STATUS_WDT_SHIFT 0x02 3102 #define TPS65917_INT2_STATUS_OTP_ERROR 0x02 3103 #define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01 3104 3105 /* Bit definitions for INT2_MASK */ 3106 #define TPS65917_INT2_MASK_SHORT 0x40 3107 #define TPS65917_INT2_MASK_SHORT_SHIFT 0x06 3108 #define TPS65917_INT2_MASK_FSD 0x20 3109 #define TPS65917_INT2_MASK_FSD_SHIFT 0x05 3110 #define TPS65917_INT2_MASK_RESET_IN 0x10 3111 #define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04 3112 #define TPS65917_INT2_MASK_WDT 0x04 3113 #define TPS65917_INT2_MASK_WDT_SHIFT 0x02 3114 #define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02 3115 #define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01 3116 3117 /* Bit definitions for INT2_LINE_STATE */ 3118 #define TPS65917_INT2_LINE_STATE_SHORT 0x40 3119 #define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06 3120 #define TPS65917_INT2_LINE_STATE_FSD 0x20 3121 #define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05 3122 #define TPS65917_INT2_LINE_STATE_RESET_IN 0x10 3123 #define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04 3124 #define TPS65917_INT2_LINE_STATE_WDT 0x04 3125 #define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02 3126 #define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02 3127 #define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01 3128 3129 /* Bit definitions for INT3_STATUS */ 3130 #define TPS65917_INT3_STATUS_VBUS 0x80 3131 #define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07 3132 #define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04 3133 #define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02 3134 #define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02 3135 #define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01 3136 #define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01 3137 #define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00 3138 3139 /* Bit definitions for INT3_MASK */ 3140 #define TPS65917_INT3_MASK_VBUS 0x80 3141 #define TPS65917_INT3_MASK_VBUS_SHIFT 0x07 3142 #define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04 3143 #define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02 3144 #define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02 3145 #define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01 3146 #define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01 3147 #define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00 3148 3149 /* Bit definitions for INT3_LINE_STATE */ 3150 #define TPS65917_INT3_LINE_STATE_VBUS 0x80 3151 #define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07 3152 #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04 3153 #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02 3154 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02 3155 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01 3156 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01 3157 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00 3158 3159 /* Bit definitions for INT4_STATUS */ 3160 #define TPS65917_INT4_STATUS_GPIO_6 0x40 3161 #define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06 3162 #define TPS65917_INT4_STATUS_GPIO_5 0x20 3163 #define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05 3164 #define TPS65917_INT4_STATUS_GPIO_4 0x10 3165 #define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04 3166 #define TPS65917_INT4_STATUS_GPIO_3 0x08 3167 #define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03 3168 #define TPS65917_INT4_STATUS_GPIO_2 0x04 3169 #define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02 3170 #define TPS65917_INT4_STATUS_GPIO_1 0x02 3171 #define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01 3172 #define TPS65917_INT4_STATUS_GPIO_0 0x01 3173 #define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00 3174 3175 /* Bit definitions for INT4_MASK */ 3176 #define TPS65917_INT4_MASK_GPIO_6 0x40 3177 #define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06 3178 #define TPS65917_INT4_MASK_GPIO_5 0x20 3179 #define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05 3180 #define TPS65917_INT4_MASK_GPIO_4 0x10 3181 #define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04 3182 #define TPS65917_INT4_MASK_GPIO_3 0x08 3183 #define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03 3184 #define TPS65917_INT4_MASK_GPIO_2 0x04 3185 #define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02 3186 #define TPS65917_INT4_MASK_GPIO_1 0x02 3187 #define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01 3188 #define TPS65917_INT4_MASK_GPIO_0 0x01 3189 #define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00 3190 3191 /* Bit definitions for INT4_LINE_STATE */ 3192 #define TPS65917_INT4_LINE_STATE_GPIO_6 0x40 3193 #define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06 3194 #define TPS65917_INT4_LINE_STATE_GPIO_5 0x20 3195 #define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05 3196 #define TPS65917_INT4_LINE_STATE_GPIO_4 0x10 3197 #define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04 3198 #define TPS65917_INT4_LINE_STATE_GPIO_3 0x08 3199 #define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03 3200 #define TPS65917_INT4_LINE_STATE_GPIO_2 0x04 3201 #define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02 3202 #define TPS65917_INT4_LINE_STATE_GPIO_1 0x02 3203 #define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01 3204 #define TPS65917_INT4_LINE_STATE_GPIO_0 0x01 3205 #define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00 3206 3207 /* Bit definitions for INT4_EDGE_DETECT1 */ 3208 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 3209 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07 3210 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 3211 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06 3212 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 3213 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05 3214 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 3215 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04 3216 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 3217 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03 3218 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 3219 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02 3220 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 3221 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01 3222 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 3223 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00 3224 3225 /* Bit definitions for INT4_EDGE_DETECT2 */ 3226 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 3227 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05 3228 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 3229 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04 3230 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 3231 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03 3232 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 3233 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02 3234 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 3235 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01 3236 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 3237 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00 3238 3239 /* Bit definitions for INT_CTRL */ 3240 #define TPS65917_INT_CTRL_INT_PENDING 0x04 3241 #define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02 3242 #define TPS65917_INT_CTRL_INT_CLEAR 0x01 3243 #define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00 3244 3245 /* TPS65917 SMPS Registers */ 3246 3247 /* Registers for function SMPS */ 3248 #define TPS65917_SMPS1_CTRL 0x00 3249 #define TPS65917_SMPS1_FORCE 0x02 3250 #define TPS65917_SMPS1_VOLTAGE 0x03 3251 #define TPS65917_SMPS2_CTRL 0x04 3252 #define TPS65917_SMPS2_FORCE 0x06 3253 #define TPS65917_SMPS2_VOLTAGE 0x07 3254 #define TPS65917_SMPS3_CTRL 0x0C 3255 #define TPS65917_SMPS3_FORCE 0x0E 3256 #define TPS65917_SMPS3_VOLTAGE 0x0F 3257 #define TPS65917_SMPS4_CTRL 0x10 3258 #define TPS65917_SMPS4_VOLTAGE 0x13 3259 #define TPS65917_SMPS5_CTRL 0x18 3260 #define TPS65917_SMPS5_VOLTAGE 0x1B 3261 #define TPS65917_SMPS_CTRL 0x24 3262 #define TPS65917_SMPS_PD_CTRL 0x25 3263 #define TPS65917_SMPS_THERMAL_EN 0x27 3264 #define TPS65917_SMPS_THERMAL_STATUS 0x28 3265 #define TPS65917_SMPS_SHORT_STATUS 0x29 3266 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A 3267 #define TPS65917_SMPS_POWERGOOD_MASK1 0x2B 3268 #define TPS65917_SMPS_POWERGOOD_MASK2 0x2C 3269 3270 /* Bit definitions for SMPS1_CTRL */ 3271 #define TPS65917_SMPS1_CTRL_WR_S 0x80 3272 #define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07 3273 #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40 3274 #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 3275 #define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30 3276 #define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04 3277 #define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C 3278 #define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02 3279 #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03 3280 #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00 3281 3282 /* Bit definitions for SMPS1_FORCE */ 3283 #define TPS65917_SMPS1_FORCE_CMD 0x80 3284 #define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07 3285 #define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F 3286 #define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00 3287 3288 /* Bit definitions for SMPS1_VOLTAGE */ 3289 #define TPS65917_SMPS1_VOLTAGE_RANGE 0x80 3290 #define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07 3291 #define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F 3292 #define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00 3293 3294 /* Bit definitions for SMPS2_CTRL */ 3295 #define TPS65917_SMPS2_CTRL_WR_S 0x80 3296 #define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07 3297 #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40 3298 #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 3299 #define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30 3300 #define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04 3301 #define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C 3302 #define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02 3303 #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03 3304 #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00 3305 3306 /* Bit definitions for SMPS2_FORCE */ 3307 #define TPS65917_SMPS2_FORCE_CMD 0x80 3308 #define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07 3309 #define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F 3310 #define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00 3311 3312 /* Bit definitions for SMPS2_VOLTAGE */ 3313 #define TPS65917_SMPS2_VOLTAGE_RANGE 0x80 3314 #define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07 3315 #define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F 3316 #define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00 3317 3318 /* Bit definitions for SMPS3_CTRL */ 3319 #define TPS65917_SMPS3_CTRL_WR_S 0x80 3320 #define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07 3321 #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40 3322 #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 3323 #define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30 3324 #define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04 3325 #define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C 3326 #define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02 3327 #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 3328 #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00 3329 3330 /* Bit definitions for SMPS3_FORCE */ 3331 #define TPS65917_SMPS3_FORCE_CMD 0x80 3332 #define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07 3333 #define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F 3334 #define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00 3335 3336 /* Bit definitions for SMPS3_VOLTAGE */ 3337 #define TPS65917_SMPS3_VOLTAGE_RANGE 0x80 3338 #define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07 3339 #define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F 3340 #define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00 3341 3342 /* Bit definitions for SMPS4_CTRL */ 3343 #define TPS65917_SMPS4_CTRL_WR_S 0x80 3344 #define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07 3345 #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40 3346 #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 3347 #define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30 3348 #define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04 3349 #define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C 3350 #define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02 3351 #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03 3352 #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00 3353 3354 /* Bit definitions for SMPS4_VOLTAGE */ 3355 #define TPS65917_SMPS4_VOLTAGE_RANGE 0x80 3356 #define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07 3357 #define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F 3358 #define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00 3359 3360 /* Bit definitions for SMPS5_CTRL */ 3361 #define TPS65917_SMPS5_CTRL_WR_S 0x80 3362 #define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07 3363 #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40 3364 #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 3365 #define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30 3366 #define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04 3367 #define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C 3368 #define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02 3369 #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03 3370 #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00 3371 3372 /* Bit definitions for SMPS5_VOLTAGE */ 3373 #define TPS65917_SMPS5_VOLTAGE_RANGE 0x80 3374 #define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07 3375 #define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F 3376 #define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00 3377 3378 /* Bit definitions for SMPS_CTRL */ 3379 #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10 3380 #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04 3381 #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03 3382 #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00 3383 3384 /* Bit definitions for SMPS_PD_CTRL */ 3385 #define TPS65917_SMPS_PD_CTRL_SMPS5 0x40 3386 #define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06 3387 #define TPS65917_SMPS_PD_CTRL_SMPS4 0x10 3388 #define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04 3389 #define TPS65917_SMPS_PD_CTRL_SMPS3 0x08 3390 #define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03 3391 #define TPS65917_SMPS_PD_CTRL_SMPS2 0x02 3392 #define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01 3393 #define TPS65917_SMPS_PD_CTRL_SMPS1 0x01 3394 #define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00 3395 3396 /* Bit definitions for SMPS_THERMAL_EN */ 3397 #define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40 3398 #define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06 3399 #define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08 3400 #define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03 3401 #define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01 3402 #define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00 3403 3404 /* Bit definitions for SMPS_THERMAL_STATUS */ 3405 #define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40 3406 #define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06 3407 #define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08 3408 #define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03 3409 #define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01 3410 #define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00 3411 3412 /* Bit definitions for SMPS_SHORT_STATUS */ 3413 #define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40 3414 #define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06 3415 #define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10 3416 #define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04 3417 #define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08 3418 #define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03 3419 #define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02 3420 #define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01 3421 #define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01 3422 #define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00 3423 3424 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ 3425 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40 3426 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06 3427 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10 3428 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04 3429 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08 3430 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03 3431 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02 3432 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01 3433 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01 3434 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00 3435 3436 /* Bit definitions for SMPS_POWERGOOD_MASK1 */ 3437 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40 3438 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06 3439 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10 3440 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04 3441 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08 3442 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03 3443 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02 3444 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01 3445 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01 3446 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00 3447 3448 /* Bit definitions for SMPS_POWERGOOD_MASK2 */ 3449 #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 3450 #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07 3451 #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10 3452 #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04 3453 3454 /* Bit definitions for SMPS_PLL_CTRL */ 3455 3456 #define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08 3457 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03 3458 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04 3459 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02 3460 3461 /* Registers for function LDO */ 3462 #define TPS65917_LDO1_CTRL 0x00 3463 #define TPS65917_LDO1_VOLTAGE 0x01 3464 #define TPS65917_LDO2_CTRL 0x02 3465 #define TPS65917_LDO2_VOLTAGE 0x03 3466 #define TPS65917_LDO3_CTRL 0x04 3467 #define TPS65917_LDO3_VOLTAGE 0x05 3468 #define TPS65917_LDO4_CTRL 0x0E 3469 #define TPS65917_LDO4_VOLTAGE 0x0F 3470 #define TPS65917_LDO5_CTRL 0x12 3471 #define TPS65917_LDO5_VOLTAGE 0x13 3472 #define TPS65917_LDO_PD_CTRL1 0x1B 3473 #define TPS65917_LDO_PD_CTRL2 0x1C 3474 #define TPS65917_LDO_SHORT_STATUS1 0x1D 3475 #define TPS65917_LDO_SHORT_STATUS2 0x1E 3476 #define TPS65917_LDO_PD_CTRL3 0x2D 3477 #define TPS65917_LDO_SHORT_STATUS3 0x2E 3478 3479 /* Bit definitions for LDO1_CTRL */ 3480 #define TPS65917_LDO1_CTRL_WR_S 0x80 3481 #define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07 3482 #define TPS65917_LDO1_CTRL_BYPASS_EN 0x40 3483 #define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06 3484 #define TPS65917_LDO1_CTRL_STATUS 0x10 3485 #define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04 3486 #define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04 3487 #define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02 3488 #define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01 3489 #define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00 3490 3491 /* Bit definitions for LDO1_VOLTAGE */ 3492 #define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F 3493 #define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00 3494 3495 /* Bit definitions for LDO2_CTRL */ 3496 #define TPS65917_LDO2_CTRL_WR_S 0x80 3497 #define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07 3498 #define TPS65917_LDO2_CTRL_BYPASS_EN 0x40 3499 #define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06 3500 #define TPS65917_LDO2_CTRL_STATUS 0x10 3501 #define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04 3502 #define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04 3503 #define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02 3504 #define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01 3505 #define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00 3506 3507 /* Bit definitions for LDO2_VOLTAGE */ 3508 #define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F 3509 #define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00 3510 3511 /* Bit definitions for LDO3_CTRL */ 3512 #define TPS65917_LDO3_CTRL_WR_S 0x80 3513 #define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07 3514 #define TPS65917_LDO3_CTRL_STATUS 0x10 3515 #define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04 3516 #define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04 3517 #define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02 3518 #define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01 3519 #define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00 3520 3521 /* Bit definitions for LDO3_VOLTAGE */ 3522 #define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F 3523 #define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00 3524 3525 /* Bit definitions for LDO4_CTRL */ 3526 #define TPS65917_LDO4_CTRL_WR_S 0x80 3527 #define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07 3528 #define TPS65917_LDO4_CTRL_STATUS 0x10 3529 #define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04 3530 #define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04 3531 #define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02 3532 #define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01 3533 #define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00 3534 3535 /* Bit definitions for LDO4_VOLTAGE */ 3536 #define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F 3537 #define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00 3538 3539 /* Bit definitions for LDO5_CTRL */ 3540 #define TPS65917_LDO5_CTRL_WR_S 0x80 3541 #define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07 3542 #define TPS65917_LDO5_CTRL_STATUS 0x10 3543 #define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04 3544 #define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04 3545 #define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02 3546 #define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01 3547 #define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00 3548 3549 /* Bit definitions for LDO5_VOLTAGE */ 3550 #define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F 3551 #define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00 3552 3553 /* Bit definitions for LDO_PD_CTRL1 */ 3554 #define TPS65917_LDO_PD_CTRL1_LDO4 0x80 3555 #define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07 3556 #define TPS65917_LDO_PD_CTRL1_LDO2 0x02 3557 #define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01 3558 #define TPS65917_LDO_PD_CTRL1_LDO1 0x01 3559 #define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00 3560 3561 /* Bit definitions for LDO_PD_CTRL2 */ 3562 #define TPS65917_LDO_PD_CTRL2_LDO3 0x04 3563 #define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02 3564 #define TPS65917_LDO_PD_CTRL2_LDO5 0x02 3565 #define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01 3566 3567 /* Bit definitions for LDO_PD_CTRL3 */ 3568 #define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80 3569 #define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07 3570 3571 /* Bit definitions for LDO_SHORT_STATUS1 */ 3572 #define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80 3573 #define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07 3574 #define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02 3575 #define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01 3576 #define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01 3577 #define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00 3578 3579 /* Bit definitions for LDO_SHORT_STATUS2 */ 3580 #define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04 3581 #define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02 3582 #define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02 3583 #define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01 3584 3585 /* Bit definitions for LDO_SHORT_STATUS2 */ 3586 #define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80 3587 #define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07 3588 3589 /* Bit definitions for REGEN1_CTRL */ 3590 #define TPS65917_REGEN1_CTRL_STATUS 0x10 3591 #define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04 3592 #define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04 3593 #define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02 3594 #define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01 3595 #define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 3596 3597 /* Bit definitions for PLLEN_CTRL */ 3598 #define TPS65917_PLLEN_CTRL_STATUS 0x10 3599 #define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04 3600 #define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04 3601 #define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02 3602 #define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01 3603 #define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00 3604 3605 /* Bit definitions for REGEN2_CTRL */ 3606 #define TPS65917_REGEN2_CTRL_STATUS 0x10 3607 #define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04 3608 #define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04 3609 #define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02 3610 #define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01 3611 #define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 3612 3613 /* Bit definitions for NSLEEP_RES_ASSIGN */ 3614 #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08 3615 #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03 3616 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04 3617 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02 3618 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02 3619 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01 3620 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01 3621 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00 3622 3623 /* Bit definitions for NSLEEP_SMPS_ASSIGN */ 3624 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40 3625 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06 3626 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10 3627 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04 3628 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08 3629 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03 3630 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02 3631 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01 3632 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01 3633 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00 3634 3635 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */ 3636 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80 3637 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07 3638 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02 3639 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01 3640 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01 3641 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00 3642 3643 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */ 3644 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04 3645 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02 3646 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02 3647 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01 3648 3649 /* Bit definitions for ENABLE1_RES_ASSIGN */ 3650 #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08 3651 #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03 3652 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04 3653 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02 3654 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02 3655 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01 3656 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01 3657 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00 3658 3659 /* Bit definitions for ENABLE1_SMPS_ASSIGN */ 3660 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40 3661 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06 3662 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10 3663 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04 3664 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08 3665 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03 3666 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02 3667 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01 3668 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01 3669 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00 3670 3671 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */ 3672 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80 3673 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07 3674 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02 3675 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01 3676 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01 3677 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00 3678 3679 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */ 3680 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04 3681 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02 3682 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02 3683 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01 3684 3685 /* Bit definitions for ENABLE2_RES_ASSIGN */ 3686 #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08 3687 #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03 3688 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04 3689 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02 3690 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02 3691 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01 3692 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01 3693 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00 3694 3695 /* Bit definitions for ENABLE2_SMPS_ASSIGN */ 3696 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40 3697 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06 3698 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10 3699 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04 3700 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08 3701 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03 3702 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02 3703 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01 3704 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01 3705 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00 3706 3707 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */ 3708 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80 3709 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07 3710 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02 3711 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01 3712 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01 3713 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00 3714 3715 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */ 3716 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04 3717 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02 3718 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02 3719 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01 3720 3721 /* Bit definitions for REGEN3_CTRL */ 3722 #define TPS65917_REGEN3_CTRL_STATUS 0x10 3723 #define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04 3724 #define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04 3725 #define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02 3726 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01 3727 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00 3728 3729 /* POWERHOLD Mask field for PRIMARY_SECONDARY_PAD2 register */ 3730 #define TPS65917_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0xC 3731 3732 /* Registers for function RESOURCE */ 3733 #define TPS65917_REGEN1_CTRL 0x2 3734 #define TPS65917_PLLEN_CTRL 0x3 3735 #define TPS65917_NSLEEP_RES_ASSIGN 0x6 3736 #define TPS65917_NSLEEP_SMPS_ASSIGN 0x7 3737 #define TPS65917_NSLEEP_LDO_ASSIGN1 0x8 3738 #define TPS65917_NSLEEP_LDO_ASSIGN2 0x9 3739 #define TPS65917_ENABLE1_RES_ASSIGN 0xA 3740 #define TPS65917_ENABLE1_SMPS_ASSIGN 0xB 3741 #define TPS65917_ENABLE1_LDO_ASSIGN1 0xC 3742 #define TPS65917_ENABLE1_LDO_ASSIGN2 0xD 3743 #define TPS65917_ENABLE2_RES_ASSIGN 0xE 3744 #define TPS65917_ENABLE2_SMPS_ASSIGN 0xF 3745 #define TPS65917_ENABLE2_LDO_ASSIGN1 0x10 3746 #define TPS65917_ENABLE2_LDO_ASSIGN2 0x11 3747 #define TPS65917_REGEN2_CTRL 0x12 3748 #define TPS65917_REGEN3_CTRL 0x13 3749 3750 static inline int palmas_read(struct palmas *palmas, unsigned int base, 3751 unsigned int reg, unsigned int *val) 3752 { 3753 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 3754 int slave_id = PALMAS_BASE_TO_SLAVE(base); 3755 3756 return regmap_read(palmas->regmap[slave_id], addr, val); 3757 } 3758 3759 static inline int palmas_write(struct palmas *palmas, unsigned int base, 3760 unsigned int reg, unsigned int value) 3761 { 3762 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 3763 int slave_id = PALMAS_BASE_TO_SLAVE(base); 3764 3765 return regmap_write(palmas->regmap[slave_id], addr, value); 3766 } 3767 3768 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base, 3769 unsigned int reg, const void *val, size_t val_count) 3770 { 3771 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 3772 int slave_id = PALMAS_BASE_TO_SLAVE(base); 3773 3774 return regmap_bulk_write(palmas->regmap[slave_id], addr, 3775 val, val_count); 3776 } 3777 3778 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base, 3779 unsigned int reg, void *val, size_t val_count) 3780 { 3781 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 3782 int slave_id = PALMAS_BASE_TO_SLAVE(base); 3783 3784 return regmap_bulk_read(palmas->regmap[slave_id], addr, 3785 val, val_count); 3786 } 3787 3788 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base, 3789 unsigned int reg, unsigned int mask, unsigned int val) 3790 { 3791 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 3792 int slave_id = PALMAS_BASE_TO_SLAVE(base); 3793 3794 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val); 3795 } 3796 3797 static inline int palmas_irq_get_virq(struct palmas *palmas, int irq) 3798 { 3799 return regmap_irq_get_virq(palmas->irq_data, irq); 3800 } 3801 3802 3803 int palmas_ext_control_req_config(struct palmas *palmas, 3804 enum palmas_external_requestor_id ext_control_req_id, 3805 int ext_ctrl, bool enable); 3806 3807 #endif /* __LINUX_MFD_PALMAS_H */ 3808