1 /* 2 * TI Palmas 3 * 4 * Copyright 2011-2013 Texas Instruments Inc. 5 * 6 * Author: Graeme Gregory <[email protected]> 7 * Author: Ian Lartey <[email protected]> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 */ 15 16 #ifndef __LINUX_MFD_PALMAS_H 17 #define __LINUX_MFD_PALMAS_H 18 19 #include <linux/usb/otg.h> 20 #include <linux/leds.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/driver.h> 23 #include <linux/extcon.h> 24 #include <linux/of_gpio.h> 25 #include <linux/usb/phy_companion.h> 26 27 #define PALMAS_NUM_CLIENTS 3 28 29 /* The ID_REVISION NUMBERS */ 30 #define PALMAS_CHIP_OLD_ID 0x0000 31 #define PALMAS_CHIP_ID 0xC035 32 #define PALMAS_CHIP_CHARGER_ID 0xC036 33 34 #define TPS65917_RESERVED -1 35 36 #define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \ 37 ((a) == PALMAS_CHIP_ID)) 38 #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID) 39 40 /** 41 * Palmas PMIC feature types 42 * 43 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST 44 * regulator. 45 * 46 * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a 47 * specific feature (above) or not. Return non-zero, if yes. 48 */ 49 #define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0) 50 #define PALMAS_PMIC_HAS(b, f) \ 51 ((b)->features & PALMAS_PMIC_FEATURE_ ## f) 52 53 struct palmas_pmic; 54 struct palmas_gpadc; 55 struct palmas_resource; 56 struct palmas_usb; 57 struct palmas_pmic_driver_data; 58 struct palmas_pmic_platform_data; 59 60 enum palmas_usb_state { 61 PALMAS_USB_STATE_DISCONNECT, 62 PALMAS_USB_STATE_VBUS, 63 PALMAS_USB_STATE_ID, 64 }; 65 66 struct palmas { 67 struct device *dev; 68 69 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS]; 70 struct regmap *regmap[PALMAS_NUM_CLIENTS]; 71 72 /* Stored chip id */ 73 int id; 74 75 unsigned int features; 76 /* IRQ Data */ 77 int irq; 78 u32 irq_mask; 79 struct mutex irq_lock; 80 struct regmap_irq_chip_data *irq_data; 81 82 struct palmas_pmic_driver_data *pmic_ddata; 83 84 /* Child Devices */ 85 struct palmas_pmic *pmic; 86 struct palmas_gpadc *gpadc; 87 struct palmas_resource *resource; 88 struct palmas_usb *usb; 89 90 /* GPIO MUXing */ 91 u8 gpio_muxed; 92 u8 led_muxed; 93 u8 pwm_muxed; 94 }; 95 96 #define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \ 97 PALMAS_EXT_CONTROL_ENABLE2 | \ 98 PALMAS_EXT_CONTROL_NSLEEP) 99 100 struct palmas_sleep_requestor_info { 101 int id; 102 int reg_offset; 103 int bit_pos; 104 }; 105 106 struct palmas_regs_info { 107 char *name; 108 char *sname; 109 u8 vsel_addr; 110 u8 ctrl_addr; 111 u8 tstep_addr; 112 int sleep_id; 113 }; 114 115 struct palmas_pmic_driver_data { 116 int smps_start; 117 int smps_end; 118 int ldo_begin; 119 int ldo_end; 120 int max_reg; 121 bool has_regen3; 122 struct palmas_regs_info *palmas_regs_info; 123 struct of_regulator_match *palmas_matches; 124 struct palmas_sleep_requestor_info *sleep_req_info; 125 int (*smps_register)(struct palmas_pmic *pmic, 126 struct palmas_pmic_driver_data *ddata, 127 struct palmas_pmic_platform_data *pdata, 128 const char *pdev_name, 129 struct regulator_config config); 130 int (*ldo_register)(struct palmas_pmic *pmic, 131 struct palmas_pmic_driver_data *ddata, 132 struct palmas_pmic_platform_data *pdata, 133 const char *pdev_name, 134 struct regulator_config config); 135 }; 136 137 struct palmas_adc_wakeup_property { 138 int adc_channel_number; 139 int adc_high_threshold; 140 int adc_low_threshold; 141 }; 142 143 struct palmas_gpadc_platform_data { 144 /* Channel 3 current source is only enabled during conversion */ 145 int ch3_current; /* 0: off; 1: 10uA; 2: 400uA; 3: 800 uA */ 146 147 /* Channel 0 current source can be used for battery detection. 148 * If used for battery detection this will cause a permanent current 149 * consumption depending on current level set here. 150 */ 151 int ch0_current; /* 0: off; 1: 5uA; 2: 15uA; 3: 20 uA */ 152 bool extended_delay; /* use extended delay for conversion */ 153 154 /* default BAT_REMOVAL_DAT setting on device probe */ 155 int bat_removal; 156 157 /* Sets the START_POLARITY bit in the RT_CTRL register */ 158 int start_polarity; 159 160 int auto_conversion_period_ms; 161 struct palmas_adc_wakeup_property *adc_wakeup1_data; 162 struct palmas_adc_wakeup_property *adc_wakeup2_data; 163 }; 164 165 struct palmas_reg_init { 166 /* warm_rest controls the voltage levels after a warm reset 167 * 168 * 0: reload default values from OTP on warm reset 169 * 1: maintain voltage from VSEL on warm reset 170 */ 171 int warm_reset; 172 173 /* roof_floor controls whether the regulator uses the i2c style 174 * of DVS or uses the method where a GPIO or other control method is 175 * attached to the NSLEEP/ENABLE1/ENABLE2 pins 176 * 177 * For SMPS 178 * 179 * 0: i2c selection of voltage 180 * 1: pin selection of voltage. 181 * 182 * For LDO unused 183 */ 184 int roof_floor; 185 186 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in 187 * the data sheet. 188 * 189 * For SMPS 190 * 191 * 0: Off 192 * 1: AUTO 193 * 2: ECO 194 * 3: Forced PWM 195 * 196 * For LDO 197 * 198 * 0: Off 199 * 1: On 200 */ 201 int mode_sleep; 202 203 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE 204 * register. Set this is the default voltage set in OTP needs 205 * to be overridden. 206 */ 207 u8 vsel; 208 209 }; 210 211 enum palmas_regulators { 212 /* SMPS regulators */ 213 PALMAS_REG_SMPS12, 214 PALMAS_REG_SMPS123, 215 PALMAS_REG_SMPS3, 216 PALMAS_REG_SMPS45, 217 PALMAS_REG_SMPS457, 218 PALMAS_REG_SMPS6, 219 PALMAS_REG_SMPS7, 220 PALMAS_REG_SMPS8, 221 PALMAS_REG_SMPS9, 222 PALMAS_REG_SMPS10_OUT2, 223 PALMAS_REG_SMPS10_OUT1, 224 /* LDO regulators */ 225 PALMAS_REG_LDO1, 226 PALMAS_REG_LDO2, 227 PALMAS_REG_LDO3, 228 PALMAS_REG_LDO4, 229 PALMAS_REG_LDO5, 230 PALMAS_REG_LDO6, 231 PALMAS_REG_LDO7, 232 PALMAS_REG_LDO8, 233 PALMAS_REG_LDO9, 234 PALMAS_REG_LDOLN, 235 PALMAS_REG_LDOUSB, 236 /* External regulators */ 237 PALMAS_REG_REGEN1, 238 PALMAS_REG_REGEN2, 239 PALMAS_REG_REGEN3, 240 PALMAS_REG_SYSEN1, 241 PALMAS_REG_SYSEN2, 242 /* Total number of regulators */ 243 PALMAS_NUM_REGS, 244 }; 245 246 enum tps65917_regulators { 247 /* SMPS regulators */ 248 TPS65917_REG_SMPS1, 249 TPS65917_REG_SMPS2, 250 TPS65917_REG_SMPS3, 251 TPS65917_REG_SMPS4, 252 TPS65917_REG_SMPS5, 253 /* LDO regulators */ 254 TPS65917_REG_LDO1, 255 TPS65917_REG_LDO2, 256 TPS65917_REG_LDO3, 257 TPS65917_REG_LDO4, 258 TPS65917_REG_LDO5, 259 TPS65917_REG_REGEN1, 260 TPS65917_REG_REGEN2, 261 TPS65917_REG_REGEN3, 262 263 /* Total number of regulators */ 264 TPS65917_NUM_REGS, 265 }; 266 267 /* External controll signal name */ 268 enum { 269 PALMAS_EXT_CONTROL_ENABLE1 = 0x1, 270 PALMAS_EXT_CONTROL_ENABLE2 = 0x2, 271 PALMAS_EXT_CONTROL_NSLEEP = 0x4, 272 }; 273 274 /* 275 * Palmas device resources can be controlled externally for 276 * enabling/disabling it rather than register write through i2c. 277 * Add the external controlled requestor ID for different resources. 278 */ 279 enum palmas_external_requestor_id { 280 PALMAS_EXTERNAL_REQSTR_ID_REGEN1, 281 PALMAS_EXTERNAL_REQSTR_ID_REGEN2, 282 PALMAS_EXTERNAL_REQSTR_ID_SYSEN1, 283 PALMAS_EXTERNAL_REQSTR_ID_SYSEN2, 284 PALMAS_EXTERNAL_REQSTR_ID_CLK32KG, 285 PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO, 286 PALMAS_EXTERNAL_REQSTR_ID_REGEN3, 287 PALMAS_EXTERNAL_REQSTR_ID_SMPS12, 288 PALMAS_EXTERNAL_REQSTR_ID_SMPS3, 289 PALMAS_EXTERNAL_REQSTR_ID_SMPS45, 290 PALMAS_EXTERNAL_REQSTR_ID_SMPS6, 291 PALMAS_EXTERNAL_REQSTR_ID_SMPS7, 292 PALMAS_EXTERNAL_REQSTR_ID_SMPS8, 293 PALMAS_EXTERNAL_REQSTR_ID_SMPS9, 294 PALMAS_EXTERNAL_REQSTR_ID_SMPS10, 295 PALMAS_EXTERNAL_REQSTR_ID_LDO1, 296 PALMAS_EXTERNAL_REQSTR_ID_LDO2, 297 PALMAS_EXTERNAL_REQSTR_ID_LDO3, 298 PALMAS_EXTERNAL_REQSTR_ID_LDO4, 299 PALMAS_EXTERNAL_REQSTR_ID_LDO5, 300 PALMAS_EXTERNAL_REQSTR_ID_LDO6, 301 PALMAS_EXTERNAL_REQSTR_ID_LDO7, 302 PALMAS_EXTERNAL_REQSTR_ID_LDO8, 303 PALMAS_EXTERNAL_REQSTR_ID_LDO9, 304 PALMAS_EXTERNAL_REQSTR_ID_LDOLN, 305 PALMAS_EXTERNAL_REQSTR_ID_LDOUSB, 306 307 /* Last entry */ 308 PALMAS_EXTERNAL_REQSTR_ID_MAX, 309 }; 310 311 enum tps65917_external_requestor_id { 312 TPS65917_EXTERNAL_REQSTR_ID_REGEN1, 313 TPS65917_EXTERNAL_REQSTR_ID_REGEN2, 314 TPS65917_EXTERNAL_REQSTR_ID_REGEN3, 315 TPS65917_EXTERNAL_REQSTR_ID_SMPS1, 316 TPS65917_EXTERNAL_REQSTR_ID_SMPS2, 317 TPS65917_EXTERNAL_REQSTR_ID_SMPS3, 318 TPS65917_EXTERNAL_REQSTR_ID_SMPS4, 319 TPS65917_EXTERNAL_REQSTR_ID_SMPS5, 320 TPS65917_EXTERNAL_REQSTR_ID_LDO1, 321 TPS65917_EXTERNAL_REQSTR_ID_LDO2, 322 TPS65917_EXTERNAL_REQSTR_ID_LDO3, 323 TPS65917_EXTERNAL_REQSTR_ID_LDO4, 324 TPS65917_EXTERNAL_REQSTR_ID_LDO5, 325 /* Last entry */ 326 TPS65917_EXTERNAL_REQSTR_ID_MAX, 327 }; 328 329 struct palmas_pmic_platform_data { 330 /* An array of pointers to regulator init data indexed by regulator 331 * ID 332 */ 333 struct regulator_init_data *reg_data[PALMAS_NUM_REGS]; 334 335 /* An array of pointers to structures containing sleep mode and DVS 336 * configuration for regulators indexed by ID 337 */ 338 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS]; 339 340 /* use LDO6 for vibrator control */ 341 int ldo6_vibrator; 342 343 /* Enable tracking mode of LDO8 */ 344 bool enable_ldo8_tracking; 345 }; 346 347 struct palmas_usb_platform_data { 348 /* Do we enable the wakeup comparator on probe */ 349 int wakeup; 350 }; 351 352 struct palmas_resource_platform_data { 353 int regen1_mode_sleep; 354 int regen2_mode_sleep; 355 int sysen1_mode_sleep; 356 int sysen2_mode_sleep; 357 358 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */ 359 u8 nsleep_res; 360 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */ 361 u8 nsleep_smps; 362 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */ 363 u8 nsleep_ldo1; 364 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */ 365 u8 nsleep_ldo2; 366 367 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */ 368 u8 enable1_res; 369 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */ 370 u8 enable1_smps; 371 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */ 372 u8 enable1_ldo1; 373 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */ 374 u8 enable1_ldo2; 375 376 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */ 377 u8 enable2_res; 378 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */ 379 u8 enable2_smps; 380 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */ 381 u8 enable2_ldo1; 382 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */ 383 u8 enable2_ldo2; 384 }; 385 386 struct palmas_clk_platform_data { 387 int clk32kg_mode_sleep; 388 int clk32kgaudio_mode_sleep; 389 }; 390 391 struct palmas_platform_data { 392 int irq_flags; 393 int gpio_base; 394 395 /* bit value to be loaded to the POWER_CTRL register */ 396 u8 power_ctrl; 397 398 /* 399 * boolean to select if we want to configure muxing here 400 * then the two value to load into the registers if true 401 */ 402 int mux_from_pdata; 403 u8 pad1, pad2; 404 bool pm_off; 405 406 struct palmas_pmic_platform_data *pmic_pdata; 407 struct palmas_gpadc_platform_data *gpadc_pdata; 408 struct palmas_usb_platform_data *usb_pdata; 409 struct palmas_resource_platform_data *resource_pdata; 410 struct palmas_clk_platform_data *clk_pdata; 411 }; 412 413 struct palmas_gpadc_calibration { 414 s32 gain; 415 s32 gain_error; 416 s32 offset_error; 417 }; 418 419 #define PALMAS_DATASHEET_NAME(_name) "palmas-gpadc-chan-"#_name 420 421 struct palmas_gpadc_result { 422 s32 raw_code; 423 s32 corrected_code; 424 s32 result; 425 }; 426 427 #define PALMAS_MAX_CHANNELS 16 428 429 /* Define the tps65917 IRQ numbers */ 430 enum tps65917_irqs { 431 /* INT1 registers */ 432 TPS65917_RESERVED1, 433 TPS65917_PWRON_IRQ, 434 TPS65917_LONG_PRESS_KEY_IRQ, 435 TPS65917_RESERVED2, 436 TPS65917_PWRDOWN_IRQ, 437 TPS65917_HOTDIE_IRQ, 438 TPS65917_VSYS_MON_IRQ, 439 TPS65917_RESERVED3, 440 /* INT2 registers */ 441 TPS65917_RESERVED4, 442 TPS65917_OTP_ERROR_IRQ, 443 TPS65917_WDT_IRQ, 444 TPS65917_RESERVED5, 445 TPS65917_RESET_IN_IRQ, 446 TPS65917_FSD_IRQ, 447 TPS65917_SHORT_IRQ, 448 TPS65917_RESERVED6, 449 /* INT3 registers */ 450 TPS65917_GPADC_AUTO_0_IRQ, 451 TPS65917_GPADC_AUTO_1_IRQ, 452 TPS65917_GPADC_EOC_SW_IRQ, 453 TPS65917_RESREVED6, 454 TPS65917_RESERVED7, 455 TPS65917_RESERVED8, 456 TPS65917_RESERVED9, 457 TPS65917_VBUS_IRQ, 458 /* INT4 registers */ 459 TPS65917_GPIO_0_IRQ, 460 TPS65917_GPIO_1_IRQ, 461 TPS65917_GPIO_2_IRQ, 462 TPS65917_GPIO_3_IRQ, 463 TPS65917_GPIO_4_IRQ, 464 TPS65917_GPIO_5_IRQ, 465 TPS65917_GPIO_6_IRQ, 466 TPS65917_RESERVED10, 467 /* Total Number IRQs */ 468 TPS65917_NUM_IRQ, 469 }; 470 471 /* Define the palmas IRQ numbers */ 472 enum palmas_irqs { 473 /* INT1 registers */ 474 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ, 475 PALMAS_PWRON_IRQ, 476 PALMAS_LONG_PRESS_KEY_IRQ, 477 PALMAS_RPWRON_IRQ, 478 PALMAS_PWRDOWN_IRQ, 479 PALMAS_HOTDIE_IRQ, 480 PALMAS_VSYS_MON_IRQ, 481 PALMAS_VBAT_MON_IRQ, 482 /* INT2 registers */ 483 PALMAS_RTC_ALARM_IRQ, 484 PALMAS_RTC_TIMER_IRQ, 485 PALMAS_WDT_IRQ, 486 PALMAS_BATREMOVAL_IRQ, 487 PALMAS_RESET_IN_IRQ, 488 PALMAS_FBI_BB_IRQ, 489 PALMAS_SHORT_IRQ, 490 PALMAS_VAC_ACOK_IRQ, 491 /* INT3 registers */ 492 PALMAS_GPADC_AUTO_0_IRQ, 493 PALMAS_GPADC_AUTO_1_IRQ, 494 PALMAS_GPADC_EOC_SW_IRQ, 495 PALMAS_GPADC_EOC_RT_IRQ, 496 PALMAS_ID_OTG_IRQ, 497 PALMAS_ID_IRQ, 498 PALMAS_VBUS_OTG_IRQ, 499 PALMAS_VBUS_IRQ, 500 /* INT4 registers */ 501 PALMAS_GPIO_0_IRQ, 502 PALMAS_GPIO_1_IRQ, 503 PALMAS_GPIO_2_IRQ, 504 PALMAS_GPIO_3_IRQ, 505 PALMAS_GPIO_4_IRQ, 506 PALMAS_GPIO_5_IRQ, 507 PALMAS_GPIO_6_IRQ, 508 PALMAS_GPIO_7_IRQ, 509 /* Total Number IRQs */ 510 PALMAS_NUM_IRQ, 511 }; 512 513 /* Palmas GPADC Channels */ 514 enum { 515 PALMAS_ADC_CH_IN0, 516 PALMAS_ADC_CH_IN1, 517 PALMAS_ADC_CH_IN2, 518 PALMAS_ADC_CH_IN3, 519 PALMAS_ADC_CH_IN4, 520 PALMAS_ADC_CH_IN5, 521 PALMAS_ADC_CH_IN6, 522 PALMAS_ADC_CH_IN7, 523 PALMAS_ADC_CH_IN8, 524 PALMAS_ADC_CH_IN9, 525 PALMAS_ADC_CH_IN10, 526 PALMAS_ADC_CH_IN11, 527 PALMAS_ADC_CH_IN12, 528 PALMAS_ADC_CH_IN13, 529 PALMAS_ADC_CH_IN14, 530 PALMAS_ADC_CH_IN15, 531 PALMAS_ADC_CH_MAX, 532 }; 533 534 /* Palmas GPADC Channel0 Current Source */ 535 enum { 536 PALMAS_ADC_CH0_CURRENT_SRC_0, 537 PALMAS_ADC_CH0_CURRENT_SRC_5, 538 PALMAS_ADC_CH0_CURRENT_SRC_15, 539 PALMAS_ADC_CH0_CURRENT_SRC_20, 540 }; 541 542 /* Palmas GPADC Channel3 Current Source */ 543 enum { 544 PALMAS_ADC_CH3_CURRENT_SRC_0, 545 PALMAS_ADC_CH3_CURRENT_SRC_10, 546 PALMAS_ADC_CH3_CURRENT_SRC_400, 547 PALMAS_ADC_CH3_CURRENT_SRC_800, 548 }; 549 550 struct palmas_pmic { 551 struct palmas *palmas; 552 struct device *dev; 553 struct regulator_desc desc[PALMAS_NUM_REGS]; 554 struct regulator_dev *rdev[PALMAS_NUM_REGS]; 555 struct mutex mutex; 556 557 int smps123; 558 int smps457; 559 int smps12; 560 561 int range[PALMAS_REG_SMPS10_OUT1]; 562 unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1]; 563 unsigned int current_reg_mode[PALMAS_REG_SMPS10_OUT1]; 564 }; 565 566 struct palmas_resource { 567 struct palmas *palmas; 568 struct device *dev; 569 }; 570 571 struct palmas_usb { 572 struct palmas *palmas; 573 struct device *dev; 574 575 struct extcon_dev *edev; 576 577 int id_otg_irq; 578 int id_irq; 579 int vbus_otg_irq; 580 int vbus_irq; 581 582 int gpio_id_irq; 583 struct gpio_desc *id_gpiod; 584 unsigned long sw_debounce_jiffies; 585 struct delayed_work wq_detectid; 586 587 enum palmas_usb_state linkstat; 588 int wakeup; 589 bool enable_vbus_detection; 590 bool enable_id_detection; 591 bool enable_gpio_id_detection; 592 }; 593 594 #define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator) 595 596 enum usb_irq_events { 597 /* Wakeup events from INT3 */ 598 PALMAS_USB_ID_WAKEPUP, 599 PALMAS_USB_VBUS_WAKEUP, 600 601 /* ID_OTG_EVENTS */ 602 PALMAS_USB_ID_GND, 603 N_PALMAS_USB_ID_GND, 604 PALMAS_USB_ID_C, 605 N_PALMAS_USB_ID_C, 606 PALMAS_USB_ID_B, 607 N_PALMAS_USB_ID_B, 608 PALMAS_USB_ID_A, 609 N_PALMAS_USB_ID_A, 610 PALMAS_USB_ID_FLOAT, 611 N_PALMAS_USB_ID_FLOAT, 612 613 /* VBUS_OTG_EVENTS */ 614 PALMAS_USB_VB_SESS_END, 615 N_PALMAS_USB_VB_SESS_END, 616 PALMAS_USB_VB_SESS_VLD, 617 N_PALMAS_USB_VB_SESS_VLD, 618 PALMAS_USB_VA_SESS_VLD, 619 N_PALMAS_USB_VA_SESS_VLD, 620 PALMAS_USB_VA_VBUS_VLD, 621 N_PALMAS_USB_VA_VBUS_VLD, 622 PALMAS_USB_VADP_SNS, 623 N_PALMAS_USB_VADP_SNS, 624 PALMAS_USB_VADP_PRB, 625 N_PALMAS_USB_VADP_PRB, 626 PALMAS_USB_VOTG_SESS_VLD, 627 N_PALMAS_USB_VOTG_SESS_VLD, 628 }; 629 630 /* defines so we can store the mux settings */ 631 #define PALMAS_GPIO_0_MUXED (1 << 0) 632 #define PALMAS_GPIO_1_MUXED (1 << 1) 633 #define PALMAS_GPIO_2_MUXED (1 << 2) 634 #define PALMAS_GPIO_3_MUXED (1 << 3) 635 #define PALMAS_GPIO_4_MUXED (1 << 4) 636 #define PALMAS_GPIO_5_MUXED (1 << 5) 637 #define PALMAS_GPIO_6_MUXED (1 << 6) 638 #define PALMAS_GPIO_7_MUXED (1 << 7) 639 640 #define PALMAS_LED1_MUXED (1 << 0) 641 #define PALMAS_LED2_MUXED (1 << 1) 642 643 #define PALMAS_PWM1_MUXED (1 << 0) 644 #define PALMAS_PWM2_MUXED (1 << 1) 645 646 /* helper macro to get correct slave number */ 647 #define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1) 648 #define PALMAS_BASE_TO_REG(x, y) ((x & 0xFF) + y) 649 650 /* Base addresses of IP blocks in Palmas */ 651 #define PALMAS_SMPS_DVS_BASE 0x020 652 #define PALMAS_RTC_BASE 0x100 653 #define PALMAS_VALIDITY_BASE 0x118 654 #define PALMAS_SMPS_BASE 0x120 655 #define PALMAS_LDO_BASE 0x150 656 #define PALMAS_DVFS_BASE 0x180 657 #define PALMAS_PMU_CONTROL_BASE 0x1A0 658 #define PALMAS_RESOURCE_BASE 0x1D4 659 #define PALMAS_PU_PD_OD_BASE 0x1F0 660 #define PALMAS_LED_BASE 0x200 661 #define PALMAS_INTERRUPT_BASE 0x210 662 #define PALMAS_USB_OTG_BASE 0x250 663 #define PALMAS_VIBRATOR_BASE 0x270 664 #define PALMAS_GPIO_BASE 0x280 665 #define PALMAS_USB_BASE 0x290 666 #define PALMAS_GPADC_BASE 0x2C0 667 #define PALMAS_TRIM_GPADC_BASE 0x3CD 668 669 /* Registers for function RTC */ 670 #define PALMAS_SECONDS_REG 0x00 671 #define PALMAS_MINUTES_REG 0x01 672 #define PALMAS_HOURS_REG 0x02 673 #define PALMAS_DAYS_REG 0x03 674 #define PALMAS_MONTHS_REG 0x04 675 #define PALMAS_YEARS_REG 0x05 676 #define PALMAS_WEEKS_REG 0x06 677 #define PALMAS_ALARM_SECONDS_REG 0x08 678 #define PALMAS_ALARM_MINUTES_REG 0x09 679 #define PALMAS_ALARM_HOURS_REG 0x0A 680 #define PALMAS_ALARM_DAYS_REG 0x0B 681 #define PALMAS_ALARM_MONTHS_REG 0x0C 682 #define PALMAS_ALARM_YEARS_REG 0x0D 683 #define PALMAS_RTC_CTRL_REG 0x10 684 #define PALMAS_RTC_STATUS_REG 0x11 685 #define PALMAS_RTC_INTERRUPTS_REG 0x12 686 #define PALMAS_RTC_COMP_LSB_REG 0x13 687 #define PALMAS_RTC_COMP_MSB_REG 0x14 688 #define PALMAS_RTC_RES_PROG_REG 0x15 689 #define PALMAS_RTC_RESET_STATUS_REG 0x16 690 691 /* Bit definitions for SECONDS_REG */ 692 #define PALMAS_SECONDS_REG_SEC1_MASK 0x70 693 #define PALMAS_SECONDS_REG_SEC1_SHIFT 0x04 694 #define PALMAS_SECONDS_REG_SEC0_MASK 0x0F 695 #define PALMAS_SECONDS_REG_SEC0_SHIFT 0x00 696 697 /* Bit definitions for MINUTES_REG */ 698 #define PALMAS_MINUTES_REG_MIN1_MASK 0x70 699 #define PALMAS_MINUTES_REG_MIN1_SHIFT 0x04 700 #define PALMAS_MINUTES_REG_MIN0_MASK 0x0F 701 #define PALMAS_MINUTES_REG_MIN0_SHIFT 0x00 702 703 /* Bit definitions for HOURS_REG */ 704 #define PALMAS_HOURS_REG_PM_NAM 0x80 705 #define PALMAS_HOURS_REG_PM_NAM_SHIFT 0x07 706 #define PALMAS_HOURS_REG_HOUR1_MASK 0x30 707 #define PALMAS_HOURS_REG_HOUR1_SHIFT 0x04 708 #define PALMAS_HOURS_REG_HOUR0_MASK 0x0F 709 #define PALMAS_HOURS_REG_HOUR0_SHIFT 0x00 710 711 /* Bit definitions for DAYS_REG */ 712 #define PALMAS_DAYS_REG_DAY1_MASK 0x30 713 #define PALMAS_DAYS_REG_DAY1_SHIFT 0x04 714 #define PALMAS_DAYS_REG_DAY0_MASK 0x0F 715 #define PALMAS_DAYS_REG_DAY0_SHIFT 0x00 716 717 /* Bit definitions for MONTHS_REG */ 718 #define PALMAS_MONTHS_REG_MONTH1 0x10 719 #define PALMAS_MONTHS_REG_MONTH1_SHIFT 0x04 720 #define PALMAS_MONTHS_REG_MONTH0_MASK 0x0F 721 #define PALMAS_MONTHS_REG_MONTH0_SHIFT 0x00 722 723 /* Bit definitions for YEARS_REG */ 724 #define PALMAS_YEARS_REG_YEAR1_MASK 0xf0 725 #define PALMAS_YEARS_REG_YEAR1_SHIFT 0x04 726 #define PALMAS_YEARS_REG_YEAR0_MASK 0x0F 727 #define PALMAS_YEARS_REG_YEAR0_SHIFT 0x00 728 729 /* Bit definitions for WEEKS_REG */ 730 #define PALMAS_WEEKS_REG_WEEK_MASK 0x07 731 #define PALMAS_WEEKS_REG_WEEK_SHIFT 0x00 732 733 /* Bit definitions for ALARM_SECONDS_REG */ 734 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70 735 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 0x04 736 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0F 737 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0x00 738 739 /* Bit definitions for ALARM_MINUTES_REG */ 740 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70 741 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 0x04 742 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0F 743 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0x00 744 745 /* Bit definitions for ALARM_HOURS_REG */ 746 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80 747 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 0x07 748 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30 749 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 0x04 750 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0F 751 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0x00 752 753 /* Bit definitions for ALARM_DAYS_REG */ 754 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30 755 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 0x04 756 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0F 757 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0x00 758 759 /* Bit definitions for ALARM_MONTHS_REG */ 760 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10 761 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 0x04 762 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0F 763 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0x00 764 765 /* Bit definitions for ALARM_YEARS_REG */ 766 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0 767 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 0x04 768 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0F 769 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0x00 770 771 /* Bit definitions for RTC_CTRL_REG */ 772 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80 773 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 0x07 774 #define PALMAS_RTC_CTRL_REG_GET_TIME 0x40 775 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 0x06 776 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20 777 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 0x05 778 #define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10 779 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 0x04 780 #define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08 781 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 0x03 782 #define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04 783 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 0x02 784 #define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02 785 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 0x01 786 #define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01 787 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0x00 788 789 /* Bit definitions for RTC_STATUS_REG */ 790 #define PALMAS_RTC_STATUS_REG_POWER_UP 0x80 791 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 0x07 792 #define PALMAS_RTC_STATUS_REG_ALARM 0x40 793 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 0x06 794 #define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20 795 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 0x05 796 #define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10 797 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 0x04 798 #define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08 799 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 0x03 800 #define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04 801 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 0x02 802 #define PALMAS_RTC_STATUS_REG_RUN 0x02 803 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT 0x01 804 805 /* Bit definitions for RTC_INTERRUPTS_REG */ 806 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10 807 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 0x04 808 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08 809 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 0x03 810 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04 811 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 0x02 812 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03 813 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0x00 814 815 /* Bit definitions for RTC_COMP_LSB_REG */ 816 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xFF 817 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0x00 818 819 /* Bit definitions for RTC_COMP_MSB_REG */ 820 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xFF 821 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0x00 822 823 /* Bit definitions for RTC_RES_PROG_REG */ 824 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3F 825 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0x00 826 827 /* Bit definitions for RTC_RESET_STATUS_REG */ 828 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01 829 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0x00 830 831 /* Registers for function BACKUP */ 832 #define PALMAS_BACKUP0 0x00 833 #define PALMAS_BACKUP1 0x01 834 #define PALMAS_BACKUP2 0x02 835 #define PALMAS_BACKUP3 0x03 836 #define PALMAS_BACKUP4 0x04 837 #define PALMAS_BACKUP5 0x05 838 #define PALMAS_BACKUP6 0x06 839 #define PALMAS_BACKUP7 0x07 840 841 /* Bit definitions for BACKUP0 */ 842 #define PALMAS_BACKUP0_BACKUP_MASK 0xFF 843 #define PALMAS_BACKUP0_BACKUP_SHIFT 0x00 844 845 /* Bit definitions for BACKUP1 */ 846 #define PALMAS_BACKUP1_BACKUP_MASK 0xFF 847 #define PALMAS_BACKUP1_BACKUP_SHIFT 0x00 848 849 /* Bit definitions for BACKUP2 */ 850 #define PALMAS_BACKUP2_BACKUP_MASK 0xFF 851 #define PALMAS_BACKUP2_BACKUP_SHIFT 0x00 852 853 /* Bit definitions for BACKUP3 */ 854 #define PALMAS_BACKUP3_BACKUP_MASK 0xFF 855 #define PALMAS_BACKUP3_BACKUP_SHIFT 0x00 856 857 /* Bit definitions for BACKUP4 */ 858 #define PALMAS_BACKUP4_BACKUP_MASK 0xFF 859 #define PALMAS_BACKUP4_BACKUP_SHIFT 0x00 860 861 /* Bit definitions for BACKUP5 */ 862 #define PALMAS_BACKUP5_BACKUP_MASK 0xFF 863 #define PALMAS_BACKUP5_BACKUP_SHIFT 0x00 864 865 /* Bit definitions for BACKUP6 */ 866 #define PALMAS_BACKUP6_BACKUP_MASK 0xFF 867 #define PALMAS_BACKUP6_BACKUP_SHIFT 0x00 868 869 /* Bit definitions for BACKUP7 */ 870 #define PALMAS_BACKUP7_BACKUP_MASK 0xFF 871 #define PALMAS_BACKUP7_BACKUP_SHIFT 0x00 872 873 /* Registers for function SMPS */ 874 #define PALMAS_SMPS12_CTRL 0x00 875 #define PALMAS_SMPS12_TSTEP 0x01 876 #define PALMAS_SMPS12_FORCE 0x02 877 #define PALMAS_SMPS12_VOLTAGE 0x03 878 #define PALMAS_SMPS3_CTRL 0x04 879 #define PALMAS_SMPS3_VOLTAGE 0x07 880 #define PALMAS_SMPS45_CTRL 0x08 881 #define PALMAS_SMPS45_TSTEP 0x09 882 #define PALMAS_SMPS45_FORCE 0x0A 883 #define PALMAS_SMPS45_VOLTAGE 0x0B 884 #define PALMAS_SMPS6_CTRL 0x0C 885 #define PALMAS_SMPS6_TSTEP 0x0D 886 #define PALMAS_SMPS6_FORCE 0x0E 887 #define PALMAS_SMPS6_VOLTAGE 0x0F 888 #define PALMAS_SMPS7_CTRL 0x10 889 #define PALMAS_SMPS7_VOLTAGE 0x13 890 #define PALMAS_SMPS8_CTRL 0x14 891 #define PALMAS_SMPS8_TSTEP 0x15 892 #define PALMAS_SMPS8_FORCE 0x16 893 #define PALMAS_SMPS8_VOLTAGE 0x17 894 #define PALMAS_SMPS9_CTRL 0x18 895 #define PALMAS_SMPS9_VOLTAGE 0x1B 896 #define PALMAS_SMPS10_CTRL 0x1C 897 #define PALMAS_SMPS10_STATUS 0x1F 898 #define PALMAS_SMPS_CTRL 0x24 899 #define PALMAS_SMPS_PD_CTRL 0x25 900 #define PALMAS_SMPS_DITHER_EN 0x26 901 #define PALMAS_SMPS_THERMAL_EN 0x27 902 #define PALMAS_SMPS_THERMAL_STATUS 0x28 903 #define PALMAS_SMPS_SHORT_STATUS 0x29 904 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A 905 #define PALMAS_SMPS_POWERGOOD_MASK1 0x2B 906 #define PALMAS_SMPS_POWERGOOD_MASK2 0x2C 907 908 /* Bit definitions for SMPS12_CTRL */ 909 #define PALMAS_SMPS12_CTRL_WR_S 0x80 910 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT 0x07 911 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40 912 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 913 #define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30 914 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT 0x04 915 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c 916 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 0x02 917 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03 918 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0x00 919 920 /* Bit definitions for SMPS12_TSTEP */ 921 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03 922 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0x00 923 924 /* Bit definitions for SMPS12_FORCE */ 925 #define PALMAS_SMPS12_FORCE_CMD 0x80 926 #define PALMAS_SMPS12_FORCE_CMD_SHIFT 0x07 927 #define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7F 928 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0x00 929 930 /* Bit definitions for SMPS12_VOLTAGE */ 931 #define PALMAS_SMPS12_VOLTAGE_RANGE 0x80 932 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 0x07 933 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7F 934 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0x00 935 936 /* Bit definitions for SMPS3_CTRL */ 937 #define PALMAS_SMPS3_CTRL_WR_S 0x80 938 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT 0x07 939 #define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30 940 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT 0x04 941 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c 942 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02 943 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 944 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00 945 946 /* Bit definitions for SMPS3_VOLTAGE */ 947 #define PALMAS_SMPS3_VOLTAGE_RANGE 0x80 948 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 0x07 949 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7F 950 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0x00 951 952 /* Bit definitions for SMPS45_CTRL */ 953 #define PALMAS_SMPS45_CTRL_WR_S 0x80 954 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT 0x07 955 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40 956 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 957 #define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30 958 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT 0x04 959 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c 960 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 0x02 961 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03 962 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0x00 963 964 /* Bit definitions for SMPS45_TSTEP */ 965 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03 966 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0x00 967 968 /* Bit definitions for SMPS45_FORCE */ 969 #define PALMAS_SMPS45_FORCE_CMD 0x80 970 #define PALMAS_SMPS45_FORCE_CMD_SHIFT 0x07 971 #define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7F 972 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0x00 973 974 /* Bit definitions for SMPS45_VOLTAGE */ 975 #define PALMAS_SMPS45_VOLTAGE_RANGE 0x80 976 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 0x07 977 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7F 978 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0x00 979 980 /* Bit definitions for SMPS6_CTRL */ 981 #define PALMAS_SMPS6_CTRL_WR_S 0x80 982 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT 0x07 983 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40 984 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 985 #define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30 986 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT 0x04 987 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c 988 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 0x02 989 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03 990 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0x00 991 992 /* Bit definitions for SMPS6_TSTEP */ 993 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03 994 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0x00 995 996 /* Bit definitions for SMPS6_FORCE */ 997 #define PALMAS_SMPS6_FORCE_CMD 0x80 998 #define PALMAS_SMPS6_FORCE_CMD_SHIFT 0x07 999 #define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7F 1000 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0x00 1001 1002 /* Bit definitions for SMPS6_VOLTAGE */ 1003 #define PALMAS_SMPS6_VOLTAGE_RANGE 0x80 1004 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 0x07 1005 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7F 1006 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0x00 1007 1008 /* Bit definitions for SMPS7_CTRL */ 1009 #define PALMAS_SMPS7_CTRL_WR_S 0x80 1010 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT 0x07 1011 #define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30 1012 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT 0x04 1013 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c 1014 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 0x02 1015 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03 1016 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0x00 1017 1018 /* Bit definitions for SMPS7_VOLTAGE */ 1019 #define PALMAS_SMPS7_VOLTAGE_RANGE 0x80 1020 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 0x07 1021 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7F 1022 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0x00 1023 1024 /* Bit definitions for SMPS8_CTRL */ 1025 #define PALMAS_SMPS8_CTRL_WR_S 0x80 1026 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT 0x07 1027 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40 1028 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 1029 #define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30 1030 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT 0x04 1031 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c 1032 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 0x02 1033 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03 1034 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0x00 1035 1036 /* Bit definitions for SMPS8_TSTEP */ 1037 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03 1038 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0x00 1039 1040 /* Bit definitions for SMPS8_FORCE */ 1041 #define PALMAS_SMPS8_FORCE_CMD 0x80 1042 #define PALMAS_SMPS8_FORCE_CMD_SHIFT 0x07 1043 #define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7F 1044 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0x00 1045 1046 /* Bit definitions for SMPS8_VOLTAGE */ 1047 #define PALMAS_SMPS8_VOLTAGE_RANGE 0x80 1048 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 0x07 1049 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7F 1050 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0x00 1051 1052 /* Bit definitions for SMPS9_CTRL */ 1053 #define PALMAS_SMPS9_CTRL_WR_S 0x80 1054 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT 0x07 1055 #define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30 1056 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT 0x04 1057 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c 1058 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 0x02 1059 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03 1060 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0x00 1061 1062 /* Bit definitions for SMPS9_VOLTAGE */ 1063 #define PALMAS_SMPS9_VOLTAGE_RANGE 0x80 1064 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 0x07 1065 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7F 1066 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0x00 1067 1068 /* Bit definitions for SMPS10_CTRL */ 1069 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0 1070 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 0x04 1071 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0F 1072 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0x00 1073 1074 /* Bit definitions for SMPS10_STATUS */ 1075 #define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0F 1076 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0x00 1077 1078 /* Bit definitions for SMPS_CTRL */ 1079 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20 1080 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 0x05 1081 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10 1082 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 0x04 1083 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c 1084 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 0x02 1085 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03 1086 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0x00 1087 1088 /* Bit definitions for SMPS_PD_CTRL */ 1089 #define PALMAS_SMPS_PD_CTRL_SMPS9 0x40 1090 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 0x06 1091 #define PALMAS_SMPS_PD_CTRL_SMPS8 0x20 1092 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 0x05 1093 #define PALMAS_SMPS_PD_CTRL_SMPS7 0x10 1094 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 0x04 1095 #define PALMAS_SMPS_PD_CTRL_SMPS6 0x08 1096 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 0x03 1097 #define PALMAS_SMPS_PD_CTRL_SMPS45 0x04 1098 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 0x02 1099 #define PALMAS_SMPS_PD_CTRL_SMPS3 0x02 1100 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 0x01 1101 #define PALMAS_SMPS_PD_CTRL_SMPS12 0x01 1102 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0x00 1103 1104 /* Bit definitions for SMPS_THERMAL_EN */ 1105 #define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40 1106 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 0x06 1107 #define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20 1108 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 0x05 1109 #define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08 1110 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 0x03 1111 #define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04 1112 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 0x02 1113 #define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01 1114 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0x00 1115 1116 /* Bit definitions for SMPS_THERMAL_STATUS */ 1117 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40 1118 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 0x06 1119 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20 1120 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 0x05 1121 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08 1122 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 0x03 1123 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04 1124 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 0x02 1125 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01 1126 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0x00 1127 1128 /* Bit definitions for SMPS_SHORT_STATUS */ 1129 #define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80 1130 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 0x07 1131 #define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40 1132 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 0x06 1133 #define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20 1134 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 0x05 1135 #define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10 1136 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 0x04 1137 #define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08 1138 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 0x03 1139 #define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04 1140 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 0x02 1141 #define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02 1142 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x01 1143 #define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01 1144 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0x00 1145 1146 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ 1147 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40 1148 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 0x06 1149 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20 1150 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 0x05 1151 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10 1152 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 0x04 1153 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08 1154 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 0x03 1155 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04 1156 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 0x02 1157 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02 1158 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x01 1159 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01 1160 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0x00 1161 1162 /* Bit definitions for SMPS_POWERGOOD_MASK1 */ 1163 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80 1164 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 0x07 1165 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40 1166 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 0x06 1167 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20 1168 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 0x05 1169 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10 1170 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 0x04 1171 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08 1172 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 0x03 1173 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04 1174 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 0x02 1175 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02 1176 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x01 1177 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01 1178 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0x00 1179 1180 /* Bit definitions for SMPS_POWERGOOD_MASK2 */ 1181 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 1182 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07 1183 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04 1184 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 0x02 1185 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02 1186 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 0x01 1187 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01 1188 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0x00 1189 1190 /* Registers for function LDO */ 1191 #define PALMAS_LDO1_CTRL 0x00 1192 #define PALMAS_LDO1_VOLTAGE 0x01 1193 #define PALMAS_LDO2_CTRL 0x02 1194 #define PALMAS_LDO2_VOLTAGE 0x03 1195 #define PALMAS_LDO3_CTRL 0x04 1196 #define PALMAS_LDO3_VOLTAGE 0x05 1197 #define PALMAS_LDO4_CTRL 0x06 1198 #define PALMAS_LDO4_VOLTAGE 0x07 1199 #define PALMAS_LDO5_CTRL 0x08 1200 #define PALMAS_LDO5_VOLTAGE 0x09 1201 #define PALMAS_LDO6_CTRL 0x0A 1202 #define PALMAS_LDO6_VOLTAGE 0x0B 1203 #define PALMAS_LDO7_CTRL 0x0C 1204 #define PALMAS_LDO7_VOLTAGE 0x0D 1205 #define PALMAS_LDO8_CTRL 0x0E 1206 #define PALMAS_LDO8_VOLTAGE 0x0F 1207 #define PALMAS_LDO9_CTRL 0x10 1208 #define PALMAS_LDO9_VOLTAGE 0x11 1209 #define PALMAS_LDOLN_CTRL 0x12 1210 #define PALMAS_LDOLN_VOLTAGE 0x13 1211 #define PALMAS_LDOUSB_CTRL 0x14 1212 #define PALMAS_LDOUSB_VOLTAGE 0x15 1213 #define PALMAS_LDO_CTRL 0x1A 1214 #define PALMAS_LDO_PD_CTRL1 0x1B 1215 #define PALMAS_LDO_PD_CTRL2 0x1C 1216 #define PALMAS_LDO_SHORT_STATUS1 0x1D 1217 #define PALMAS_LDO_SHORT_STATUS2 0x1E 1218 1219 /* Bit definitions for LDO1_CTRL */ 1220 #define PALMAS_LDO1_CTRL_WR_S 0x80 1221 #define PALMAS_LDO1_CTRL_WR_S_SHIFT 0x07 1222 #define PALMAS_LDO1_CTRL_STATUS 0x10 1223 #define PALMAS_LDO1_CTRL_STATUS_SHIFT 0x04 1224 #define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04 1225 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02 1226 #define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01 1227 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00 1228 1229 /* Bit definitions for LDO1_VOLTAGE */ 1230 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3F 1231 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0x00 1232 1233 /* Bit definitions for LDO2_CTRL */ 1234 #define PALMAS_LDO2_CTRL_WR_S 0x80 1235 #define PALMAS_LDO2_CTRL_WR_S_SHIFT 0x07 1236 #define PALMAS_LDO2_CTRL_STATUS 0x10 1237 #define PALMAS_LDO2_CTRL_STATUS_SHIFT 0x04 1238 #define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04 1239 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02 1240 #define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01 1241 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00 1242 1243 /* Bit definitions for LDO2_VOLTAGE */ 1244 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3F 1245 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0x00 1246 1247 /* Bit definitions for LDO3_CTRL */ 1248 #define PALMAS_LDO3_CTRL_WR_S 0x80 1249 #define PALMAS_LDO3_CTRL_WR_S_SHIFT 0x07 1250 #define PALMAS_LDO3_CTRL_STATUS 0x10 1251 #define PALMAS_LDO3_CTRL_STATUS_SHIFT 0x04 1252 #define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04 1253 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02 1254 #define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01 1255 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00 1256 1257 /* Bit definitions for LDO3_VOLTAGE */ 1258 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3F 1259 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0x00 1260 1261 /* Bit definitions for LDO4_CTRL */ 1262 #define PALMAS_LDO4_CTRL_WR_S 0x80 1263 #define PALMAS_LDO4_CTRL_WR_S_SHIFT 0x07 1264 #define PALMAS_LDO4_CTRL_STATUS 0x10 1265 #define PALMAS_LDO4_CTRL_STATUS_SHIFT 0x04 1266 #define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04 1267 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02 1268 #define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01 1269 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00 1270 1271 /* Bit definitions for LDO4_VOLTAGE */ 1272 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3F 1273 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0x00 1274 1275 /* Bit definitions for LDO5_CTRL */ 1276 #define PALMAS_LDO5_CTRL_WR_S 0x80 1277 #define PALMAS_LDO5_CTRL_WR_S_SHIFT 0x07 1278 #define PALMAS_LDO5_CTRL_STATUS 0x10 1279 #define PALMAS_LDO5_CTRL_STATUS_SHIFT 0x04 1280 #define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04 1281 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02 1282 #define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01 1283 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00 1284 1285 /* Bit definitions for LDO5_VOLTAGE */ 1286 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3F 1287 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0x00 1288 1289 /* Bit definitions for LDO6_CTRL */ 1290 #define PALMAS_LDO6_CTRL_WR_S 0x80 1291 #define PALMAS_LDO6_CTRL_WR_S_SHIFT 0x07 1292 #define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40 1293 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 0x06 1294 #define PALMAS_LDO6_CTRL_STATUS 0x10 1295 #define PALMAS_LDO6_CTRL_STATUS_SHIFT 0x04 1296 #define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04 1297 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 0x02 1298 #define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01 1299 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0x00 1300 1301 /* Bit definitions for LDO6_VOLTAGE */ 1302 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3F 1303 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0x00 1304 1305 /* Bit definitions for LDO7_CTRL */ 1306 #define PALMAS_LDO7_CTRL_WR_S 0x80 1307 #define PALMAS_LDO7_CTRL_WR_S_SHIFT 0x07 1308 #define PALMAS_LDO7_CTRL_STATUS 0x10 1309 #define PALMAS_LDO7_CTRL_STATUS_SHIFT 0x04 1310 #define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04 1311 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 0x02 1312 #define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01 1313 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0x00 1314 1315 /* Bit definitions for LDO7_VOLTAGE */ 1316 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3F 1317 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0x00 1318 1319 /* Bit definitions for LDO8_CTRL */ 1320 #define PALMAS_LDO8_CTRL_WR_S 0x80 1321 #define PALMAS_LDO8_CTRL_WR_S_SHIFT 0x07 1322 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40 1323 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 0x06 1324 #define PALMAS_LDO8_CTRL_STATUS 0x10 1325 #define PALMAS_LDO8_CTRL_STATUS_SHIFT 0x04 1326 #define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04 1327 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 0x02 1328 #define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01 1329 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0x00 1330 1331 /* Bit definitions for LDO8_VOLTAGE */ 1332 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3F 1333 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0x00 1334 1335 /* Bit definitions for LDO9_CTRL */ 1336 #define PALMAS_LDO9_CTRL_WR_S 0x80 1337 #define PALMAS_LDO9_CTRL_WR_S_SHIFT 0x07 1338 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40 1339 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 0x06 1340 #define PALMAS_LDO9_CTRL_STATUS 0x10 1341 #define PALMAS_LDO9_CTRL_STATUS_SHIFT 0x04 1342 #define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04 1343 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 0x02 1344 #define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01 1345 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0x00 1346 1347 /* Bit definitions for LDO9_VOLTAGE */ 1348 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3F 1349 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0x00 1350 1351 /* Bit definitions for LDOLN_CTRL */ 1352 #define PALMAS_LDOLN_CTRL_WR_S 0x80 1353 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT 0x07 1354 #define PALMAS_LDOLN_CTRL_STATUS 0x10 1355 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT 0x04 1356 #define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04 1357 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 0x02 1358 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01 1359 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0x00 1360 1361 /* Bit definitions for LDOLN_VOLTAGE */ 1362 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3F 1363 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0x00 1364 1365 /* Bit definitions for LDOUSB_CTRL */ 1366 #define PALMAS_LDOUSB_CTRL_WR_S 0x80 1367 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 0x07 1368 #define PALMAS_LDOUSB_CTRL_STATUS 0x10 1369 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 0x04 1370 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04 1371 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 0x02 1372 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01 1373 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0x00 1374 1375 /* Bit definitions for LDOUSB_VOLTAGE */ 1376 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3F 1377 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0x00 1378 1379 /* Bit definitions for LDO_CTRL */ 1380 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01 1381 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0x00 1382 1383 /* Bit definitions for LDO_PD_CTRL1 */ 1384 #define PALMAS_LDO_PD_CTRL1_LDO8 0x80 1385 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 0x07 1386 #define PALMAS_LDO_PD_CTRL1_LDO7 0x40 1387 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 0x06 1388 #define PALMAS_LDO_PD_CTRL1_LDO6 0x20 1389 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 0x05 1390 #define PALMAS_LDO_PD_CTRL1_LDO5 0x10 1391 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 0x04 1392 #define PALMAS_LDO_PD_CTRL1_LDO4 0x08 1393 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 0x03 1394 #define PALMAS_LDO_PD_CTRL1_LDO3 0x04 1395 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 0x02 1396 #define PALMAS_LDO_PD_CTRL1_LDO2 0x02 1397 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 0x01 1398 #define PALMAS_LDO_PD_CTRL1_LDO1 0x01 1399 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0x00 1400 1401 /* Bit definitions for LDO_PD_CTRL2 */ 1402 #define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04 1403 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 0x02 1404 #define PALMAS_LDO_PD_CTRL2_LDOLN 0x02 1405 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 0x01 1406 #define PALMAS_LDO_PD_CTRL2_LDO9 0x01 1407 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0x00 1408 1409 /* Bit definitions for LDO_SHORT_STATUS1 */ 1410 #define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80 1411 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 0x07 1412 #define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40 1413 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 0x06 1414 #define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20 1415 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 0x05 1416 #define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10 1417 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 0x04 1418 #define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08 1419 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 0x03 1420 #define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04 1421 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 0x02 1422 #define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02 1423 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01 1424 #define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01 1425 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00 1426 1427 /* Bit definitions for LDO_SHORT_STATUS2 */ 1428 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08 1429 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x03 1430 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04 1431 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 0x02 1432 #define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02 1433 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 0x01 1434 #define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01 1435 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0x00 1436 1437 /* Registers for function PMU_CONTROL */ 1438 #define PALMAS_DEV_CTRL 0x00 1439 #define PALMAS_POWER_CTRL 0x01 1440 #define PALMAS_VSYS_LO 0x02 1441 #define PALMAS_VSYS_MON 0x03 1442 #define PALMAS_VBAT_MON 0x04 1443 #define PALMAS_WATCHDOG 0x05 1444 #define PALMAS_BOOT_STATUS 0x06 1445 #define PALMAS_BATTERY_BOUNCE 0x07 1446 #define PALMAS_BACKUP_BATTERY_CTRL 0x08 1447 #define PALMAS_LONG_PRESS_KEY 0x09 1448 #define PALMAS_OSC_THERM_CTRL 0x0A 1449 #define PALMAS_BATDEBOUNCING 0x0B 1450 #define PALMAS_SWOFF_HWRST 0x0F 1451 #define PALMAS_SWOFF_COLDRST 0x10 1452 #define PALMAS_SWOFF_STATUS 0x11 1453 #define PALMAS_PMU_CONFIG 0x12 1454 #define PALMAS_SPARE 0x14 1455 #define PALMAS_PMU_SECONDARY_INT 0x15 1456 #define PALMAS_SW_REVISION 0x17 1457 #define PALMAS_EXT_CHRG_CTRL 0x18 1458 #define PALMAS_PMU_SECONDARY_INT2 0x19 1459 1460 /* Bit definitions for DEV_CTRL */ 1461 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c 1462 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 0x02 1463 #define PALMAS_DEV_CTRL_SW_RST 0x02 1464 #define PALMAS_DEV_CTRL_SW_RST_SHIFT 0x01 1465 #define PALMAS_DEV_CTRL_DEV_ON 0x01 1466 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0x00 1467 1468 /* Bit definitions for POWER_CTRL */ 1469 #define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04 1470 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 0x02 1471 #define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02 1472 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 0x01 1473 #define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01 1474 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0x00 1475 1476 /* Bit definitions for VSYS_LO */ 1477 #define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1F 1478 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0x00 1479 1480 /* Bit definitions for VSYS_MON */ 1481 #define PALMAS_VSYS_MON_ENABLE 0x80 1482 #define PALMAS_VSYS_MON_ENABLE_SHIFT 0x07 1483 #define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3F 1484 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0x00 1485 1486 /* Bit definitions for VBAT_MON */ 1487 #define PALMAS_VBAT_MON_ENABLE 0x80 1488 #define PALMAS_VBAT_MON_ENABLE_SHIFT 0x07 1489 #define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3F 1490 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0x00 1491 1492 /* Bit definitions for WATCHDOG */ 1493 #define PALMAS_WATCHDOG_LOCK 0x20 1494 #define PALMAS_WATCHDOG_LOCK_SHIFT 0x05 1495 #define PALMAS_WATCHDOG_ENABLE 0x10 1496 #define PALMAS_WATCHDOG_ENABLE_SHIFT 0x04 1497 #define PALMAS_WATCHDOG_MODE 0x08 1498 #define PALMAS_WATCHDOG_MODE_SHIFT 0x03 1499 #define PALMAS_WATCHDOG_TIMER_MASK 0x07 1500 #define PALMAS_WATCHDOG_TIMER_SHIFT 0x00 1501 1502 /* Bit definitions for BOOT_STATUS */ 1503 #define PALMAS_BOOT_STATUS_BOOT1 0x02 1504 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT 0x01 1505 #define PALMAS_BOOT_STATUS_BOOT0 0x01 1506 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0x00 1507 1508 /* Bit definitions for BATTERY_BOUNCE */ 1509 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3F 1510 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0x00 1511 1512 /* Bit definitions for BACKUP_BATTERY_CTRL */ 1513 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80 1514 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 0x07 1515 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40 1516 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 0x06 1517 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20 1518 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 0x05 1519 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10 1520 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 0x04 1521 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08 1522 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 0x03 1523 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06 1524 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 0x01 1525 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01 1526 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0x00 1527 1528 /* Bit definitions for LONG_PRESS_KEY */ 1529 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80 1530 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 0x07 1531 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10 1532 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 0x04 1533 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c 1534 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 0x02 1535 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03 1536 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0x00 1537 1538 /* Bit definitions for OSC_THERM_CTRL */ 1539 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80 1540 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 0x07 1541 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40 1542 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 0x06 1543 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20 1544 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 0x05 1545 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10 1546 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 0x04 1547 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c 1548 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 0x02 1549 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02 1550 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 0x01 1551 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01 1552 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0x00 1553 1554 /* Bit definitions for BATDEBOUNCING */ 1555 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80 1556 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 0x07 1557 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78 1558 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 0x03 1559 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07 1560 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0x00 1561 1562 /* Bit definitions for SWOFF_HWRST */ 1563 #define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80 1564 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 0x07 1565 #define PALMAS_SWOFF_HWRST_PWRDOWN 0x40 1566 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 0x06 1567 #define PALMAS_SWOFF_HWRST_WTD 0x20 1568 #define PALMAS_SWOFF_HWRST_WTD_SHIFT 0x05 1569 #define PALMAS_SWOFF_HWRST_TSHUT 0x10 1570 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 0x04 1571 #define PALMAS_SWOFF_HWRST_RESET_IN 0x08 1572 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 0x03 1573 #define PALMAS_SWOFF_HWRST_SW_RST 0x04 1574 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 0x02 1575 #define PALMAS_SWOFF_HWRST_VSYS_LO 0x02 1576 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 0x01 1577 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01 1578 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0x00 1579 1580 /* Bit definitions for SWOFF_COLDRST */ 1581 #define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80 1582 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 0x07 1583 #define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40 1584 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 0x06 1585 #define PALMAS_SWOFF_COLDRST_WTD 0x20 1586 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT 0x05 1587 #define PALMAS_SWOFF_COLDRST_TSHUT 0x10 1588 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 0x04 1589 #define PALMAS_SWOFF_COLDRST_RESET_IN 0x08 1590 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 0x03 1591 #define PALMAS_SWOFF_COLDRST_SW_RST 0x04 1592 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 0x02 1593 #define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02 1594 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 0x01 1595 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01 1596 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0x00 1597 1598 /* Bit definitions for SWOFF_STATUS */ 1599 #define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80 1600 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 0x07 1601 #define PALMAS_SWOFF_STATUS_PWRDOWN 0x40 1602 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 0x06 1603 #define PALMAS_SWOFF_STATUS_WTD 0x20 1604 #define PALMAS_SWOFF_STATUS_WTD_SHIFT 0x05 1605 #define PALMAS_SWOFF_STATUS_TSHUT 0x10 1606 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 0x04 1607 #define PALMAS_SWOFF_STATUS_RESET_IN 0x08 1608 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 0x03 1609 #define PALMAS_SWOFF_STATUS_SW_RST 0x04 1610 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 0x02 1611 #define PALMAS_SWOFF_STATUS_VSYS_LO 0x02 1612 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 0x01 1613 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01 1614 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0x00 1615 1616 /* Bit definitions for PMU_CONFIG */ 1617 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40 1618 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 0x06 1619 #define PALMAS_PMU_CONFIG_SPARE_MASK 0x30 1620 #define PALMAS_PMU_CONFIG_SPARE_SHIFT 0x04 1621 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c 1622 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 0x02 1623 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02 1624 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 0x01 1625 #define PALMAS_PMU_CONFIG_AUTODEVON 0x01 1626 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0x00 1627 1628 /* Bit definitions for SPARE */ 1629 #define PALMAS_SPARE_SPARE_MASK 0xf8 1630 #define PALMAS_SPARE_SPARE_SHIFT 0x03 1631 #define PALMAS_SPARE_REGEN3_OD 0x04 1632 #define PALMAS_SPARE_REGEN3_OD_SHIFT 0x02 1633 #define PALMAS_SPARE_REGEN2_OD 0x02 1634 #define PALMAS_SPARE_REGEN2_OD_SHIFT 0x01 1635 #define PALMAS_SPARE_REGEN1_OD 0x01 1636 #define PALMAS_SPARE_REGEN1_OD_SHIFT 0x00 1637 1638 /* Bit definitions for PMU_SECONDARY_INT */ 1639 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80 1640 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 0x07 1641 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40 1642 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 0x06 1643 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20 1644 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 0x05 1645 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10 1646 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 0x04 1647 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08 1648 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 0x03 1649 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04 1650 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 0x02 1651 #define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02 1652 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 0x01 1653 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01 1654 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0x00 1655 1656 /* Bit definitions for SW_REVISION */ 1657 #define PALMAS_SW_REVISION_SW_REVISION_MASK 0xFF 1658 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0x00 1659 1660 /* Bit definitions for EXT_CHRG_CTRL */ 1661 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80 1662 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 0x07 1663 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40 1664 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 0x06 1665 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08 1666 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 0x03 1667 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04 1668 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 0x02 1669 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02 1670 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 0x01 1671 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01 1672 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0x00 1673 1674 /* Bit definitions for PMU_SECONDARY_INT2 */ 1675 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20 1676 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 0x05 1677 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10 1678 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 0x04 1679 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02 1680 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 0x01 1681 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01 1682 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0x00 1683 1684 /* Registers for function RESOURCE */ 1685 #define PALMAS_CLK32KG_CTRL 0x00 1686 #define PALMAS_CLK32KGAUDIO_CTRL 0x01 1687 #define PALMAS_REGEN1_CTRL 0x02 1688 #define PALMAS_REGEN2_CTRL 0x03 1689 #define PALMAS_SYSEN1_CTRL 0x04 1690 #define PALMAS_SYSEN2_CTRL 0x05 1691 #define PALMAS_NSLEEP_RES_ASSIGN 0x06 1692 #define PALMAS_NSLEEP_SMPS_ASSIGN 0x07 1693 #define PALMAS_NSLEEP_LDO_ASSIGN1 0x08 1694 #define PALMAS_NSLEEP_LDO_ASSIGN2 0x09 1695 #define PALMAS_ENABLE1_RES_ASSIGN 0x0A 1696 #define PALMAS_ENABLE1_SMPS_ASSIGN 0x0B 1697 #define PALMAS_ENABLE1_LDO_ASSIGN1 0x0C 1698 #define PALMAS_ENABLE1_LDO_ASSIGN2 0x0D 1699 #define PALMAS_ENABLE2_RES_ASSIGN 0x0E 1700 #define PALMAS_ENABLE2_SMPS_ASSIGN 0x0F 1701 #define PALMAS_ENABLE2_LDO_ASSIGN1 0x10 1702 #define PALMAS_ENABLE2_LDO_ASSIGN2 0x11 1703 #define PALMAS_REGEN3_CTRL 0x12 1704 1705 /* Bit definitions for CLK32KG_CTRL */ 1706 #define PALMAS_CLK32KG_CTRL_STATUS 0x10 1707 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 0x04 1708 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04 1709 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 0x02 1710 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01 1711 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0x00 1712 1713 /* Bit definitions for CLK32KGAUDIO_CTRL */ 1714 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10 1715 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 0x04 1716 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08 1717 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 0x03 1718 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04 1719 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 0x02 1720 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01 1721 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0x00 1722 1723 /* Bit definitions for REGEN1_CTRL */ 1724 #define PALMAS_REGEN1_CTRL_STATUS 0x10 1725 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT 0x04 1726 #define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04 1727 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02 1728 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01 1729 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 1730 1731 /* Bit definitions for REGEN2_CTRL */ 1732 #define PALMAS_REGEN2_CTRL_STATUS 0x10 1733 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT 0x04 1734 #define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04 1735 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02 1736 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01 1737 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 1738 1739 /* Bit definitions for SYSEN1_CTRL */ 1740 #define PALMAS_SYSEN1_CTRL_STATUS 0x10 1741 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 0x04 1742 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04 1743 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 0x02 1744 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01 1745 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 1746 1747 /* Bit definitions for SYSEN2_CTRL */ 1748 #define PALMAS_SYSEN2_CTRL_STATUS 0x10 1749 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 0x04 1750 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04 1751 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 0x02 1752 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01 1753 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 1754 1755 /* Bit definitions for NSLEEP_RES_ASSIGN */ 1756 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40 1757 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x06 1758 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20 1759 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05 1760 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10 1761 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 0x04 1762 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08 1763 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 0x03 1764 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04 1765 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 0x02 1766 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02 1767 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01 1768 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01 1769 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00 1770 1771 /* Bit definitions for NSLEEP_SMPS_ASSIGN */ 1772 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80 1773 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 0x07 1774 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40 1775 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 0x06 1776 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20 1777 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 0x05 1778 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10 1779 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 0x04 1780 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08 1781 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 0x03 1782 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04 1783 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 0x02 1784 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02 1785 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x01 1786 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01 1787 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0x00 1788 1789 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */ 1790 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80 1791 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 0x07 1792 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40 1793 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 0x06 1794 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20 1795 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 0x05 1796 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10 1797 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 0x04 1798 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08 1799 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x03 1800 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04 1801 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 0x02 1802 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02 1803 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01 1804 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01 1805 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00 1806 1807 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */ 1808 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04 1809 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 0x02 1810 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02 1811 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 0x01 1812 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01 1813 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0x00 1814 1815 /* Bit definitions for ENABLE1_RES_ASSIGN */ 1816 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40 1817 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x06 1818 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20 1819 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05 1820 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10 1821 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 0x04 1822 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08 1823 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 0x03 1824 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04 1825 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 0x02 1826 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02 1827 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01 1828 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01 1829 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00 1830 1831 /* Bit definitions for ENABLE1_SMPS_ASSIGN */ 1832 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80 1833 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 0x07 1834 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40 1835 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 0x06 1836 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20 1837 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 0x05 1838 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10 1839 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 0x04 1840 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08 1841 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 0x03 1842 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04 1843 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 0x02 1844 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02 1845 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x01 1846 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01 1847 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0x00 1848 1849 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */ 1850 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80 1851 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 0x07 1852 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40 1853 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 0x06 1854 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20 1855 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 0x05 1856 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10 1857 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 0x04 1858 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08 1859 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x03 1860 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04 1861 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 0x02 1862 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02 1863 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01 1864 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01 1865 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00 1866 1867 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */ 1868 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04 1869 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 0x02 1870 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02 1871 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 0x01 1872 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01 1873 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0x00 1874 1875 /* Bit definitions for ENABLE2_RES_ASSIGN */ 1876 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40 1877 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x06 1878 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20 1879 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05 1880 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10 1881 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 0x04 1882 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08 1883 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 0x03 1884 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04 1885 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 0x02 1886 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02 1887 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01 1888 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01 1889 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00 1890 1891 /* Bit definitions for ENABLE2_SMPS_ASSIGN */ 1892 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80 1893 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 0x07 1894 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40 1895 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 0x06 1896 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20 1897 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 0x05 1898 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10 1899 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 0x04 1900 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08 1901 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 0x03 1902 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04 1903 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 0x02 1904 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02 1905 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x01 1906 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01 1907 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0x00 1908 1909 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */ 1910 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80 1911 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 0x07 1912 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40 1913 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 0x06 1914 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20 1915 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 0x05 1916 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10 1917 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 0x04 1918 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08 1919 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x03 1920 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04 1921 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 0x02 1922 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02 1923 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01 1924 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01 1925 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00 1926 1927 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */ 1928 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04 1929 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 0x02 1930 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02 1931 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 0x01 1932 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01 1933 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0x00 1934 1935 /* Bit definitions for REGEN3_CTRL */ 1936 #define PALMAS_REGEN3_CTRL_STATUS 0x10 1937 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT 0x04 1938 #define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04 1939 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02 1940 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01 1941 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00 1942 1943 /* Registers for function PAD_CONTROL */ 1944 #define PALMAS_OD_OUTPUT_CTRL2 0x02 1945 #define PALMAS_POLARITY_CTRL2 0x03 1946 #define PALMAS_PU_PD_INPUT_CTRL1 0x04 1947 #define PALMAS_PU_PD_INPUT_CTRL2 0x05 1948 #define PALMAS_PU_PD_INPUT_CTRL3 0x06 1949 #define PALMAS_PU_PD_INPUT_CTRL5 0x07 1950 #define PALMAS_OD_OUTPUT_CTRL 0x08 1951 #define PALMAS_POLARITY_CTRL 0x09 1952 #define PALMAS_PRIMARY_SECONDARY_PAD1 0x0A 1953 #define PALMAS_PRIMARY_SECONDARY_PAD2 0x0B 1954 #define PALMAS_I2C_SPI 0x0C 1955 #define PALMAS_PU_PD_INPUT_CTRL4 0x0D 1956 #define PALMAS_PRIMARY_SECONDARY_PAD3 0x0E 1957 #define PALMAS_PRIMARY_SECONDARY_PAD4 0x0F 1958 1959 /* Bit definitions for PU_PD_INPUT_CTRL1 */ 1960 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40 1961 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 0x06 1962 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20 1963 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 0x05 1964 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10 1965 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 0x04 1966 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04 1967 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 0x02 1968 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02 1969 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 0x01 1970 1971 /* Bit definitions for PU_PD_INPUT_CTRL2 */ 1972 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20 1973 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 0x05 1974 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10 1975 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 0x04 1976 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08 1977 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 0x03 1978 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04 1979 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 0x02 1980 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02 1981 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 0x01 1982 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01 1983 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0x00 1984 1985 /* Bit definitions for PU_PD_INPUT_CTRL3 */ 1986 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40 1987 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 0x06 1988 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10 1989 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 0x04 1990 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04 1991 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 0x02 1992 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01 1993 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0x00 1994 1995 /* Bit definitions for OD_OUTPUT_CTRL */ 1996 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80 1997 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 0x07 1998 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40 1999 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 0x06 2000 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20 2001 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 0x05 2002 #define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08 2003 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 0x03 2004 2005 /* Bit definitions for POLARITY_CTRL */ 2006 #define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80 2007 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 0x07 2008 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40 2009 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 0x06 2010 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20 2011 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 0x05 2012 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10 2013 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 0x04 2014 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08 2015 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 0x03 2016 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04 2017 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 0x02 2018 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02 2019 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 0x01 2020 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01 2021 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0x00 2022 2023 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */ 2024 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80 2025 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 0x07 2026 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60 2027 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 0x05 2028 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18 2029 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 0x03 2030 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04 2031 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 0x02 2032 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02 2033 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 0x01 2034 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01 2035 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0x00 2036 2037 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */ 2038 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30 2039 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 0x04 2040 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08 2041 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 0x03 2042 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06 2043 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 0x01 2044 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01 2045 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0x00 2046 2047 /* Bit definitions for I2C_SPI */ 2048 #define PALMAS_I2C_SPI_I2C2OTP_EN 0x80 2049 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 0x07 2050 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40 2051 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 0x06 2052 #define PALMAS_I2C_SPI_ID_I2C2 0x20 2053 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT 0x05 2054 #define PALMAS_I2C_SPI_I2C_SPI 0x10 2055 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT 0x04 2056 #define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0F 2057 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0x00 2058 2059 /* Bit definitions for PU_PD_INPUT_CTRL4 */ 2060 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40 2061 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 0x06 2062 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10 2063 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 0x04 2064 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04 2065 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 0x02 2066 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01 2067 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0x00 2068 2069 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */ 2070 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02 2071 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 0x01 2072 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01 2073 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0x00 2074 2075 /* Registers for function LED_PWM */ 2076 #define PALMAS_LED_PERIOD_CTRL 0x00 2077 #define PALMAS_LED_CTRL 0x01 2078 #define PALMAS_PWM_CTRL1 0x02 2079 #define PALMAS_PWM_CTRL2 0x03 2080 2081 /* Bit definitions for LED_PERIOD_CTRL */ 2082 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38 2083 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 0x03 2084 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07 2085 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0x00 2086 2087 /* Bit definitions for LED_CTRL */ 2088 #define PALMAS_LED_CTRL_LED_2_SEQ 0x20 2089 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 0x05 2090 #define PALMAS_LED_CTRL_LED_1_SEQ 0x10 2091 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 0x04 2092 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c 2093 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 0x02 2094 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03 2095 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0x00 2096 2097 /* Bit definitions for PWM_CTRL1 */ 2098 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02 2099 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 0x01 2100 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01 2101 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0x00 2102 2103 /* Bit definitions for PWM_CTRL2 */ 2104 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xFF 2105 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0x00 2106 2107 /* Registers for function INTERRUPT */ 2108 #define PALMAS_INT1_STATUS 0x00 2109 #define PALMAS_INT1_MASK 0x01 2110 #define PALMAS_INT1_LINE_STATE 0x02 2111 #define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x03 2112 #define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x04 2113 #define PALMAS_INT2_STATUS 0x05 2114 #define PALMAS_INT2_MASK 0x06 2115 #define PALMAS_INT2_LINE_STATE 0x07 2116 #define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x08 2117 #define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x09 2118 #define PALMAS_INT3_STATUS 0x0A 2119 #define PALMAS_INT3_MASK 0x0B 2120 #define PALMAS_INT3_LINE_STATE 0x0C 2121 #define PALMAS_INT3_EDGE_DETECT1_RESERVED 0x0D 2122 #define PALMAS_INT3_EDGE_DETECT2_RESERVED 0x0E 2123 #define PALMAS_INT4_STATUS 0x0F 2124 #define PALMAS_INT4_MASK 0x10 2125 #define PALMAS_INT4_LINE_STATE 0x11 2126 #define PALMAS_INT4_EDGE_DETECT1 0x12 2127 #define PALMAS_INT4_EDGE_DETECT2 0x13 2128 #define PALMAS_INT_CTRL 0x14 2129 2130 /* Bit definitions for INT1_STATUS */ 2131 #define PALMAS_INT1_STATUS_VBAT_MON 0x80 2132 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 0x07 2133 #define PALMAS_INT1_STATUS_VSYS_MON 0x40 2134 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 0x06 2135 #define PALMAS_INT1_STATUS_HOTDIE 0x20 2136 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT 0x05 2137 #define PALMAS_INT1_STATUS_PWRDOWN 0x10 2138 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 0x04 2139 #define PALMAS_INT1_STATUS_RPWRON 0x08 2140 #define PALMAS_INT1_STATUS_RPWRON_SHIFT 0x03 2141 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04 2142 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02 2143 #define PALMAS_INT1_STATUS_PWRON 0x02 2144 #define PALMAS_INT1_STATUS_PWRON_SHIFT 0x01 2145 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01 2146 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0x00 2147 2148 /* Bit definitions for INT1_MASK */ 2149 #define PALMAS_INT1_MASK_VBAT_MON 0x80 2150 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT 0x07 2151 #define PALMAS_INT1_MASK_VSYS_MON 0x40 2152 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT 0x06 2153 #define PALMAS_INT1_MASK_HOTDIE 0x20 2154 #define PALMAS_INT1_MASK_HOTDIE_SHIFT 0x05 2155 #define PALMAS_INT1_MASK_PWRDOWN 0x10 2156 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT 0x04 2157 #define PALMAS_INT1_MASK_RPWRON 0x08 2158 #define PALMAS_INT1_MASK_RPWRON_SHIFT 0x03 2159 #define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04 2160 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02 2161 #define PALMAS_INT1_MASK_PWRON 0x02 2162 #define PALMAS_INT1_MASK_PWRON_SHIFT 0x01 2163 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01 2164 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0x00 2165 2166 /* Bit definitions for INT1_LINE_STATE */ 2167 #define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80 2168 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 0x07 2169 #define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40 2170 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06 2171 #define PALMAS_INT1_LINE_STATE_HOTDIE 0x20 2172 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 0x05 2173 #define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10 2174 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04 2175 #define PALMAS_INT1_LINE_STATE_RPWRON 0x08 2176 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 0x03 2177 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 2178 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02 2179 #define PALMAS_INT1_LINE_STATE_PWRON 0x02 2180 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 0x01 2181 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01 2182 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0x00 2183 2184 /* Bit definitions for INT2_STATUS */ 2185 #define PALMAS_INT2_STATUS_VAC_ACOK 0x80 2186 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 0x07 2187 #define PALMAS_INT2_STATUS_SHORT 0x40 2188 #define PALMAS_INT2_STATUS_SHORT_SHIFT 0x06 2189 #define PALMAS_INT2_STATUS_FBI_BB 0x20 2190 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT 0x05 2191 #define PALMAS_INT2_STATUS_RESET_IN 0x10 2192 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT 0x04 2193 #define PALMAS_INT2_STATUS_BATREMOVAL 0x08 2194 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 0x03 2195 #define PALMAS_INT2_STATUS_WDT 0x04 2196 #define PALMAS_INT2_STATUS_WDT_SHIFT 0x02 2197 #define PALMAS_INT2_STATUS_RTC_TIMER 0x02 2198 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 0x01 2199 #define PALMAS_INT2_STATUS_RTC_ALARM 0x01 2200 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0x00 2201 2202 /* Bit definitions for INT2_MASK */ 2203 #define PALMAS_INT2_MASK_VAC_ACOK 0x80 2204 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 0x07 2205 #define PALMAS_INT2_MASK_SHORT 0x40 2206 #define PALMAS_INT2_MASK_SHORT_SHIFT 0x06 2207 #define PALMAS_INT2_MASK_FBI_BB 0x20 2208 #define PALMAS_INT2_MASK_FBI_BB_SHIFT 0x05 2209 #define PALMAS_INT2_MASK_RESET_IN 0x10 2210 #define PALMAS_INT2_MASK_RESET_IN_SHIFT 0x04 2211 #define PALMAS_INT2_MASK_BATREMOVAL 0x08 2212 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 0x03 2213 #define PALMAS_INT2_MASK_WDT 0x04 2214 #define PALMAS_INT2_MASK_WDT_SHIFT 0x02 2215 #define PALMAS_INT2_MASK_RTC_TIMER 0x02 2216 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 0x01 2217 #define PALMAS_INT2_MASK_RTC_ALARM 0x01 2218 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0x00 2219 2220 /* Bit definitions for INT2_LINE_STATE */ 2221 #define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80 2222 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 0x07 2223 #define PALMAS_INT2_LINE_STATE_SHORT 0x40 2224 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 0x06 2225 #define PALMAS_INT2_LINE_STATE_FBI_BB 0x20 2226 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 0x05 2227 #define PALMAS_INT2_LINE_STATE_RESET_IN 0x10 2228 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 0x04 2229 #define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08 2230 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 0x03 2231 #define PALMAS_INT2_LINE_STATE_WDT 0x04 2232 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT 0x02 2233 #define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02 2234 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 0x01 2235 #define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01 2236 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0x00 2237 2238 /* Bit definitions for INT3_STATUS */ 2239 #define PALMAS_INT3_STATUS_VBUS 0x80 2240 #define PALMAS_INT3_STATUS_VBUS_SHIFT 0x07 2241 #define PALMAS_INT3_STATUS_VBUS_OTG 0x40 2242 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 0x06 2243 #define PALMAS_INT3_STATUS_ID 0x20 2244 #define PALMAS_INT3_STATUS_ID_SHIFT 0x05 2245 #define PALMAS_INT3_STATUS_ID_OTG 0x10 2246 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT 0x04 2247 #define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08 2248 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 0x03 2249 #define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04 2250 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02 2251 #define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02 2252 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01 2253 #define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01 2254 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00 2255 2256 /* Bit definitions for INT3_MASK */ 2257 #define PALMAS_INT3_MASK_VBUS 0x80 2258 #define PALMAS_INT3_MASK_VBUS_SHIFT 0x07 2259 #define PALMAS_INT3_MASK_VBUS_OTG 0x40 2260 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 0x06 2261 #define PALMAS_INT3_MASK_ID 0x20 2262 #define PALMAS_INT3_MASK_ID_SHIFT 0x05 2263 #define PALMAS_INT3_MASK_ID_OTG 0x10 2264 #define PALMAS_INT3_MASK_ID_OTG_SHIFT 0x04 2265 #define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08 2266 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 0x03 2267 #define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04 2268 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02 2269 #define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02 2270 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01 2271 #define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01 2272 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00 2273 2274 /* Bit definitions for INT3_LINE_STATE */ 2275 #define PALMAS_INT3_LINE_STATE_VBUS 0x80 2276 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 0x07 2277 #define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40 2278 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 0x06 2279 #define PALMAS_INT3_LINE_STATE_ID 0x20 2280 #define PALMAS_INT3_LINE_STATE_ID_SHIFT 0x05 2281 #define PALMAS_INT3_LINE_STATE_ID_OTG 0x10 2282 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 0x04 2283 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08 2284 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 0x03 2285 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04 2286 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02 2287 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02 2288 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01 2289 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01 2290 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00 2291 2292 /* Bit definitions for INT4_STATUS */ 2293 #define PALMAS_INT4_STATUS_GPIO_7 0x80 2294 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT 0x07 2295 #define PALMAS_INT4_STATUS_GPIO_6 0x40 2296 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT 0x06 2297 #define PALMAS_INT4_STATUS_GPIO_5 0x20 2298 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT 0x05 2299 #define PALMAS_INT4_STATUS_GPIO_4 0x10 2300 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT 0x04 2301 #define PALMAS_INT4_STATUS_GPIO_3 0x08 2302 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT 0x03 2303 #define PALMAS_INT4_STATUS_GPIO_2 0x04 2304 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT 0x02 2305 #define PALMAS_INT4_STATUS_GPIO_1 0x02 2306 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT 0x01 2307 #define PALMAS_INT4_STATUS_GPIO_0 0x01 2308 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0x00 2309 2310 /* Bit definitions for INT4_MASK */ 2311 #define PALMAS_INT4_MASK_GPIO_7 0x80 2312 #define PALMAS_INT4_MASK_GPIO_7_SHIFT 0x07 2313 #define PALMAS_INT4_MASK_GPIO_6 0x40 2314 #define PALMAS_INT4_MASK_GPIO_6_SHIFT 0x06 2315 #define PALMAS_INT4_MASK_GPIO_5 0x20 2316 #define PALMAS_INT4_MASK_GPIO_5_SHIFT 0x05 2317 #define PALMAS_INT4_MASK_GPIO_4 0x10 2318 #define PALMAS_INT4_MASK_GPIO_4_SHIFT 0x04 2319 #define PALMAS_INT4_MASK_GPIO_3 0x08 2320 #define PALMAS_INT4_MASK_GPIO_3_SHIFT 0x03 2321 #define PALMAS_INT4_MASK_GPIO_2 0x04 2322 #define PALMAS_INT4_MASK_GPIO_2_SHIFT 0x02 2323 #define PALMAS_INT4_MASK_GPIO_1 0x02 2324 #define PALMAS_INT4_MASK_GPIO_1_SHIFT 0x01 2325 #define PALMAS_INT4_MASK_GPIO_0 0x01 2326 #define PALMAS_INT4_MASK_GPIO_0_SHIFT 0x00 2327 2328 /* Bit definitions for INT4_LINE_STATE */ 2329 #define PALMAS_INT4_LINE_STATE_GPIO_7 0x80 2330 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 0x07 2331 #define PALMAS_INT4_LINE_STATE_GPIO_6 0x40 2332 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 0x06 2333 #define PALMAS_INT4_LINE_STATE_GPIO_5 0x20 2334 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 0x05 2335 #define PALMAS_INT4_LINE_STATE_GPIO_4 0x10 2336 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 0x04 2337 #define PALMAS_INT4_LINE_STATE_GPIO_3 0x08 2338 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 0x03 2339 #define PALMAS_INT4_LINE_STATE_GPIO_2 0x04 2340 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 0x02 2341 #define PALMAS_INT4_LINE_STATE_GPIO_1 0x02 2342 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 0x01 2343 #define PALMAS_INT4_LINE_STATE_GPIO_0 0x01 2344 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0x00 2345 2346 /* Bit definitions for INT4_EDGE_DETECT1 */ 2347 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 2348 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07 2349 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 2350 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06 2351 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 2352 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05 2353 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 2354 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04 2355 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 2356 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03 2357 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 2358 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02 2359 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 2360 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01 2361 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 2362 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00 2363 2364 /* Bit definitions for INT4_EDGE_DETECT2 */ 2365 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80 2366 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 0x07 2367 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40 2368 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 0x06 2369 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 2370 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05 2371 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 2372 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04 2373 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 2374 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03 2375 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 2376 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02 2377 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 2378 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01 2379 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 2380 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00 2381 2382 /* Bit definitions for INT_CTRL */ 2383 #define PALMAS_INT_CTRL_INT_PENDING 0x04 2384 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT 0x02 2385 #define PALMAS_INT_CTRL_INT_CLEAR 0x01 2386 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0x00 2387 2388 /* Registers for function USB_OTG */ 2389 #define PALMAS_USB_WAKEUP 0x03 2390 #define PALMAS_USB_VBUS_CTRL_SET 0x04 2391 #define PALMAS_USB_VBUS_CTRL_CLR 0x05 2392 #define PALMAS_USB_ID_CTRL_SET 0x06 2393 #define PALMAS_USB_ID_CTRL_CLEAR 0x07 2394 #define PALMAS_USB_VBUS_INT_SRC 0x08 2395 #define PALMAS_USB_VBUS_INT_LATCH_SET 0x09 2396 #define PALMAS_USB_VBUS_INT_LATCH_CLR 0x0A 2397 #define PALMAS_USB_VBUS_INT_EN_LO_SET 0x0B 2398 #define PALMAS_USB_VBUS_INT_EN_LO_CLR 0x0C 2399 #define PALMAS_USB_VBUS_INT_EN_HI_SET 0x0D 2400 #define PALMAS_USB_VBUS_INT_EN_HI_CLR 0x0E 2401 #define PALMAS_USB_ID_INT_SRC 0x0F 2402 #define PALMAS_USB_ID_INT_LATCH_SET 0x10 2403 #define PALMAS_USB_ID_INT_LATCH_CLR 0x11 2404 #define PALMAS_USB_ID_INT_EN_LO_SET 0x12 2405 #define PALMAS_USB_ID_INT_EN_LO_CLR 0x13 2406 #define PALMAS_USB_ID_INT_EN_HI_SET 0x14 2407 #define PALMAS_USB_ID_INT_EN_HI_CLR 0x15 2408 #define PALMAS_USB_OTG_ADP_CTRL 0x16 2409 #define PALMAS_USB_OTG_ADP_HIGH 0x17 2410 #define PALMAS_USB_OTG_ADP_LOW 0x18 2411 #define PALMAS_USB_OTG_ADP_RISE 0x19 2412 #define PALMAS_USB_OTG_REVISION 0x1A 2413 2414 /* Bit definitions for USB_WAKEUP */ 2415 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01 2416 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0x00 2417 2418 /* Bit definitions for USB_VBUS_CTRL_SET */ 2419 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80 2420 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 0x07 2421 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20 2422 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 0x05 2423 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10 2424 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 0x04 2425 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08 2426 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 0x03 2427 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04 2428 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 0x02 2429 2430 /* Bit definitions for USB_VBUS_CTRL_CLR */ 2431 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80 2432 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 0x07 2433 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20 2434 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 0x05 2435 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10 2436 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 0x04 2437 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08 2438 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 0x03 2439 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04 2440 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 0x02 2441 2442 /* Bit definitions for USB_ID_CTRL_SET */ 2443 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80 2444 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 0x07 2445 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40 2446 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 0x06 2447 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20 2448 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 0x05 2449 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10 2450 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 0x04 2451 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08 2452 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 0x03 2453 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04 2454 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 0x02 2455 2456 /* Bit definitions for USB_ID_CTRL_CLEAR */ 2457 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80 2458 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 0x07 2459 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40 2460 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 0x06 2461 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20 2462 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 0x05 2463 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10 2464 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 0x04 2465 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08 2466 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 0x03 2467 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04 2468 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 0x02 2469 2470 /* Bit definitions for USB_VBUS_INT_SRC */ 2471 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80 2472 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 0x07 2473 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40 2474 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 0x06 2475 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20 2476 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 0x05 2477 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08 2478 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 0x03 2479 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04 2480 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 0x02 2481 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02 2482 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 0x01 2483 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01 2484 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0x00 2485 2486 /* Bit definitions for USB_VBUS_INT_LATCH_SET */ 2487 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80 2488 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 0x07 2489 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40 2490 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 0x06 2491 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20 2492 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 0x05 2493 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10 2494 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 0x04 2495 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08 2496 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 0x03 2497 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04 2498 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 0x02 2499 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02 2500 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 0x01 2501 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01 2502 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0x00 2503 2504 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */ 2505 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80 2506 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 0x07 2507 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40 2508 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 0x06 2509 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20 2510 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 0x05 2511 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10 2512 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 0x04 2513 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08 2514 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 0x03 2515 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04 2516 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 0x02 2517 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02 2518 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 0x01 2519 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01 2520 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0x00 2521 2522 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */ 2523 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80 2524 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 0x07 2525 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40 2526 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 0x06 2527 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20 2528 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 0x05 2529 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08 2530 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 0x03 2531 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04 2532 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 0x02 2533 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02 2534 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 0x01 2535 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01 2536 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0x00 2537 2538 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */ 2539 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80 2540 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 0x07 2541 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40 2542 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 0x06 2543 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20 2544 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 0x05 2545 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08 2546 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 0x03 2547 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04 2548 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 0x02 2549 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02 2550 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 0x01 2551 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01 2552 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0x00 2553 2554 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */ 2555 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80 2556 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 0x07 2557 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40 2558 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 0x06 2559 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20 2560 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 0x05 2561 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10 2562 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 0x04 2563 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08 2564 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 0x03 2565 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04 2566 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 0x02 2567 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02 2568 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 0x01 2569 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01 2570 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0x00 2571 2572 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */ 2573 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80 2574 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 0x07 2575 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40 2576 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 0x06 2577 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20 2578 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 0x05 2579 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10 2580 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 0x04 2581 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08 2582 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 0x03 2583 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04 2584 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 0x02 2585 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02 2586 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 0x01 2587 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01 2588 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0x00 2589 2590 /* Bit definitions for USB_ID_INT_SRC */ 2591 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10 2592 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 0x04 2593 #define PALMAS_USB_ID_INT_SRC_ID_A 0x08 2594 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 0x03 2595 #define PALMAS_USB_ID_INT_SRC_ID_B 0x04 2596 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 0x02 2597 #define PALMAS_USB_ID_INT_SRC_ID_C 0x02 2598 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 0x01 2599 #define PALMAS_USB_ID_INT_SRC_ID_GND 0x01 2600 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0x00 2601 2602 /* Bit definitions for USB_ID_INT_LATCH_SET */ 2603 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10 2604 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 0x04 2605 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08 2606 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 0x03 2607 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04 2608 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 0x02 2609 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02 2610 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 0x01 2611 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01 2612 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0x00 2613 2614 /* Bit definitions for USB_ID_INT_LATCH_CLR */ 2615 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10 2616 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 0x04 2617 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08 2618 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 0x03 2619 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04 2620 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 0x02 2621 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02 2622 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 0x01 2623 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01 2624 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0x00 2625 2626 /* Bit definitions for USB_ID_INT_EN_LO_SET */ 2627 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10 2628 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 0x04 2629 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08 2630 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 0x03 2631 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04 2632 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 0x02 2633 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02 2634 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 0x01 2635 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01 2636 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0x00 2637 2638 /* Bit definitions for USB_ID_INT_EN_LO_CLR */ 2639 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10 2640 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 0x04 2641 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08 2642 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 0x03 2643 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04 2644 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 0x02 2645 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02 2646 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 0x01 2647 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01 2648 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0x00 2649 2650 /* Bit definitions for USB_ID_INT_EN_HI_SET */ 2651 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10 2652 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 0x04 2653 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08 2654 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 0x03 2655 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04 2656 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 0x02 2657 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02 2658 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 0x01 2659 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01 2660 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0x00 2661 2662 /* Bit definitions for USB_ID_INT_EN_HI_CLR */ 2663 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10 2664 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 0x04 2665 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08 2666 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 0x03 2667 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04 2668 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 0x02 2669 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02 2670 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 0x01 2671 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01 2672 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0x00 2673 2674 /* Bit definitions for USB_OTG_ADP_CTRL */ 2675 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04 2676 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 0x02 2677 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03 2678 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0x00 2679 2680 /* Bit definitions for USB_OTG_ADP_HIGH */ 2681 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xFF 2682 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0x00 2683 2684 /* Bit definitions for USB_OTG_ADP_LOW */ 2685 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xFF 2686 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0x00 2687 2688 /* Bit definitions for USB_OTG_ADP_RISE */ 2689 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xFF 2690 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0x00 2691 2692 /* Bit definitions for USB_OTG_REVISION */ 2693 #define PALMAS_USB_OTG_REVISION_OTG_REV 0x01 2694 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0x00 2695 2696 /* Registers for function VIBRATOR */ 2697 #define PALMAS_VIBRA_CTRL 0x00 2698 2699 /* Bit definitions for VIBRA_CTRL */ 2700 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06 2701 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 0x01 2702 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01 2703 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0x00 2704 2705 /* Registers for function GPIO */ 2706 #define PALMAS_GPIO_DATA_IN 0x00 2707 #define PALMAS_GPIO_DATA_DIR 0x01 2708 #define PALMAS_GPIO_DATA_OUT 0x02 2709 #define PALMAS_GPIO_DEBOUNCE_EN 0x03 2710 #define PALMAS_GPIO_CLEAR_DATA_OUT 0x04 2711 #define PALMAS_GPIO_SET_DATA_OUT 0x05 2712 #define PALMAS_PU_PD_GPIO_CTRL1 0x06 2713 #define PALMAS_PU_PD_GPIO_CTRL2 0x07 2714 #define PALMAS_OD_OUTPUT_GPIO_CTRL 0x08 2715 #define PALMAS_GPIO_DATA_IN2 0x09 2716 #define PALMAS_GPIO_DATA_DIR2 0x0A 2717 #define PALMAS_GPIO_DATA_OUT2 0x0B 2718 #define PALMAS_GPIO_DEBOUNCE_EN2 0x0C 2719 #define PALMAS_GPIO_CLEAR_DATA_OUT2 0x0D 2720 #define PALMAS_GPIO_SET_DATA_OUT2 0x0E 2721 #define PALMAS_PU_PD_GPIO_CTRL3 0x0F 2722 #define PALMAS_PU_PD_GPIO_CTRL4 0x10 2723 #define PALMAS_OD_OUTPUT_GPIO_CTRL2 0x11 2724 2725 /* Bit definitions for GPIO_DATA_IN */ 2726 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80 2727 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 0x07 2728 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40 2729 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 0x06 2730 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20 2731 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 0x05 2732 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10 2733 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 0x04 2734 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08 2735 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 0x03 2736 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04 2737 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 0x02 2738 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02 2739 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 0x01 2740 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01 2741 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0x00 2742 2743 /* Bit definitions for GPIO_DATA_DIR */ 2744 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80 2745 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 0x07 2746 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40 2747 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 0x06 2748 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20 2749 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 0x05 2750 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10 2751 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 0x04 2752 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08 2753 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 0x03 2754 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04 2755 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 0x02 2756 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02 2757 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 0x01 2758 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01 2759 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0x00 2760 2761 /* Bit definitions for GPIO_DATA_OUT */ 2762 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80 2763 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 0x07 2764 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40 2765 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 0x06 2766 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20 2767 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 0x05 2768 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10 2769 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 0x04 2770 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08 2771 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 0x03 2772 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04 2773 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 0x02 2774 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02 2775 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 0x01 2776 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01 2777 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0x00 2778 2779 /* Bit definitions for GPIO_DEBOUNCE_EN */ 2780 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80 2781 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 0x07 2782 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40 2783 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 0x06 2784 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20 2785 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 0x05 2786 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10 2787 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 0x04 2788 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08 2789 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 0x03 2790 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04 2791 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 0x02 2792 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02 2793 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 0x01 2794 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01 2795 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0x00 2796 2797 /* Bit definitions for GPIO_CLEAR_DATA_OUT */ 2798 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80 2799 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 0x07 2800 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40 2801 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 0x06 2802 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20 2803 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 0x05 2804 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10 2805 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 0x04 2806 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08 2807 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 0x03 2808 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04 2809 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 0x02 2810 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02 2811 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 0x01 2812 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01 2813 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0x00 2814 2815 /* Bit definitions for GPIO_SET_DATA_OUT */ 2816 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80 2817 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 0x07 2818 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40 2819 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 0x06 2820 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20 2821 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 0x05 2822 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10 2823 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 0x04 2824 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08 2825 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 0x03 2826 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04 2827 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 0x02 2828 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02 2829 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 0x01 2830 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01 2831 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0x00 2832 2833 /* Bit definitions for PU_PD_GPIO_CTRL1 */ 2834 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40 2835 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 0x06 2836 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20 2837 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 0x05 2838 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10 2839 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 0x04 2840 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08 2841 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 0x03 2842 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04 2843 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 0x02 2844 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01 2845 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0x00 2846 2847 /* Bit definitions for PU_PD_GPIO_CTRL2 */ 2848 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40 2849 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 0x06 2850 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20 2851 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 0x05 2852 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10 2853 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 0x04 2854 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08 2855 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 0x03 2856 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04 2857 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 0x02 2858 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02 2859 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 0x01 2860 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01 2861 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0x00 2862 2863 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */ 2864 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20 2865 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 0x05 2866 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04 2867 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 0x02 2868 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02 2869 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 0x01 2870 2871 /* Registers for function GPADC */ 2872 #define PALMAS_GPADC_CTRL1 0x00 2873 #define PALMAS_GPADC_CTRL2 0x01 2874 #define PALMAS_GPADC_RT_CTRL 0x02 2875 #define PALMAS_GPADC_AUTO_CTRL 0x03 2876 #define PALMAS_GPADC_STATUS 0x04 2877 #define PALMAS_GPADC_RT_SELECT 0x05 2878 #define PALMAS_GPADC_RT_CONV0_LSB 0x06 2879 #define PALMAS_GPADC_RT_CONV0_MSB 0x07 2880 #define PALMAS_GPADC_AUTO_SELECT 0x08 2881 #define PALMAS_GPADC_AUTO_CONV0_LSB 0x09 2882 #define PALMAS_GPADC_AUTO_CONV0_MSB 0x0A 2883 #define PALMAS_GPADC_AUTO_CONV1_LSB 0x0B 2884 #define PALMAS_GPADC_AUTO_CONV1_MSB 0x0C 2885 #define PALMAS_GPADC_SW_SELECT 0x0D 2886 #define PALMAS_GPADC_SW_CONV0_LSB 0x0E 2887 #define PALMAS_GPADC_SW_CONV0_MSB 0x0F 2888 #define PALMAS_GPADC_THRES_CONV0_LSB 0x10 2889 #define PALMAS_GPADC_THRES_CONV0_MSB 0x11 2890 #define PALMAS_GPADC_THRES_CONV1_LSB 0x12 2891 #define PALMAS_GPADC_THRES_CONV1_MSB 0x13 2892 #define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14 2893 #define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15 2894 2895 /* Bit definitions for GPADC_CTRL1 */ 2896 #define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0 2897 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 0x06 2898 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30 2899 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 0x04 2900 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c 2901 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 0x02 2902 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02 2903 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 0x01 2904 #define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01 2905 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0x00 2906 2907 /* Bit definitions for GPADC_CTRL2 */ 2908 #define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06 2909 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 0x01 2910 2911 /* Bit definitions for GPADC_RT_CTRL */ 2912 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02 2913 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 0x01 2914 #define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01 2915 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0x00 2916 2917 /* Bit definitions for GPADC_AUTO_CTRL */ 2918 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80 2919 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 0x07 2920 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40 2921 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 0x06 2922 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20 2923 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 0x05 2924 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10 2925 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 0x04 2926 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0F 2927 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0x00 2928 2929 /* Bit definitions for GPADC_STATUS */ 2930 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10 2931 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 0x04 2932 2933 /* Bit definitions for GPADC_RT_SELECT */ 2934 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80 2935 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 0x07 2936 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0F 2937 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0x00 2938 2939 /* Bit definitions for GPADC_RT_CONV0_LSB */ 2940 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xFF 2941 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0x00 2942 2943 /* Bit definitions for GPADC_RT_CONV0_MSB */ 2944 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0F 2945 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0x00 2946 2947 /* Bit definitions for GPADC_AUTO_SELECT */ 2948 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xF0 2949 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 0x04 2950 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0F 2951 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0x00 2952 2953 /* Bit definitions for GPADC_AUTO_CONV0_LSB */ 2954 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xFF 2955 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0x00 2956 2957 /* Bit definitions for GPADC_AUTO_CONV0_MSB */ 2958 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0F 2959 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0x00 2960 2961 /* Bit definitions for GPADC_AUTO_CONV1_LSB */ 2962 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xFF 2963 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0x00 2964 2965 /* Bit definitions for GPADC_AUTO_CONV1_MSB */ 2966 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0F 2967 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0x00 2968 2969 /* Bit definitions for GPADC_SW_SELECT */ 2970 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80 2971 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 0x07 2972 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10 2973 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 0x04 2974 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0F 2975 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0x00 2976 2977 /* Bit definitions for GPADC_SW_CONV0_LSB */ 2978 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xFF 2979 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0x00 2980 2981 /* Bit definitions for GPADC_SW_CONV0_MSB */ 2982 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0F 2983 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0x00 2984 2985 /* Bit definitions for GPADC_THRES_CONV0_LSB */ 2986 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xFF 2987 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0x00 2988 2989 /* Bit definitions for GPADC_THRES_CONV0_MSB */ 2990 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80 2991 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 0x07 2992 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0F 2993 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0x00 2994 2995 /* Bit definitions for GPADC_THRES_CONV1_LSB */ 2996 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xFF 2997 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0x00 2998 2999 /* Bit definitions for GPADC_THRES_CONV1_MSB */ 3000 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80 3001 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 0x07 3002 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0F 3003 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0x00 3004 3005 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */ 3006 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20 3007 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 0x05 3008 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10 3009 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 0x04 3010 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0F 3011 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0x00 3012 3013 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */ 3014 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80 3015 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 0x07 3016 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7F 3017 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0x00 3018 3019 /* Registers for function GPADC */ 3020 #define PALMAS_GPADC_TRIM1 0x00 3021 #define PALMAS_GPADC_TRIM2 0x01 3022 #define PALMAS_GPADC_TRIM3 0x02 3023 #define PALMAS_GPADC_TRIM4 0x03 3024 #define PALMAS_GPADC_TRIM5 0x04 3025 #define PALMAS_GPADC_TRIM6 0x05 3026 #define PALMAS_GPADC_TRIM7 0x06 3027 #define PALMAS_GPADC_TRIM8 0x07 3028 #define PALMAS_GPADC_TRIM9 0x08 3029 #define PALMAS_GPADC_TRIM10 0x09 3030 #define PALMAS_GPADC_TRIM11 0x0A 3031 #define PALMAS_GPADC_TRIM12 0x0B 3032 #define PALMAS_GPADC_TRIM13 0x0C 3033 #define PALMAS_GPADC_TRIM14 0x0D 3034 #define PALMAS_GPADC_TRIM15 0x0E 3035 #define PALMAS_GPADC_TRIM16 0x0F 3036 3037 /* TPS659038 regen2_ctrl offset iss different from palmas */ 3038 #define TPS659038_REGEN2_CTRL 0x12 3039 3040 /* TPS65917 Interrupt registers */ 3041 3042 /* Registers for function INTERRUPT */ 3043 #define TPS65917_INT1_STATUS 0x00 3044 #define TPS65917_INT1_MASK 0x01 3045 #define TPS65917_INT1_LINE_STATE 0x02 3046 #define TPS65917_INT2_STATUS 0x05 3047 #define TPS65917_INT2_MASK 0x06 3048 #define TPS65917_INT2_LINE_STATE 0x07 3049 #define TPS65917_INT3_STATUS 0x0A 3050 #define TPS65917_INT3_MASK 0x0B 3051 #define TPS65917_INT3_LINE_STATE 0x0C 3052 #define TPS65917_INT4_STATUS 0x0F 3053 #define TPS65917_INT4_MASK 0x10 3054 #define TPS65917_INT4_LINE_STATE 0x11 3055 #define TPS65917_INT4_EDGE_DETECT1 0x12 3056 #define TPS65917_INT4_EDGE_DETECT2 0x13 3057 #define TPS65917_INT_CTRL 0x14 3058 3059 /* Bit definitions for INT1_STATUS */ 3060 #define TPS65917_INT1_STATUS_VSYS_MON 0x40 3061 #define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06 3062 #define TPS65917_INT1_STATUS_HOTDIE 0x20 3063 #define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05 3064 #define TPS65917_INT1_STATUS_PWRDOWN 0x10 3065 #define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04 3066 #define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04 3067 #define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02 3068 #define TPS65917_INT1_STATUS_PWRON 0x02 3069 #define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01 3070 3071 /* Bit definitions for INT1_MASK */ 3072 #define TPS65917_INT1_MASK_VSYS_MON 0x40 3073 #define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06 3074 #define TPS65917_INT1_MASK_HOTDIE 0x20 3075 #define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05 3076 #define TPS65917_INT1_MASK_PWRDOWN 0x10 3077 #define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04 3078 #define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04 3079 #define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02 3080 #define TPS65917_INT1_MASK_PWRON 0x02 3081 #define TPS65917_INT1_MASK_PWRON_SHIFT 0x01 3082 3083 /* Bit definitions for INT1_LINE_STATE */ 3084 #define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40 3085 #define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06 3086 #define TPS65917_INT1_LINE_STATE_HOTDIE 0x20 3087 #define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05 3088 #define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10 3089 #define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04 3090 #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 3091 #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02 3092 #define TPS65917_INT1_LINE_STATE_PWRON 0x02 3093 #define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01 3094 3095 /* Bit definitions for INT2_STATUS */ 3096 #define TPS65917_INT2_STATUS_SHORT 0x40 3097 #define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06 3098 #define TPS65917_INT2_STATUS_FSD 0x20 3099 #define TPS65917_INT2_STATUS_FSD_SHIFT 0x05 3100 #define TPS65917_INT2_STATUS_RESET_IN 0x10 3101 #define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04 3102 #define TPS65917_INT2_STATUS_WDT 0x04 3103 #define TPS65917_INT2_STATUS_WDT_SHIFT 0x02 3104 #define TPS65917_INT2_STATUS_OTP_ERROR 0x02 3105 #define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01 3106 3107 /* Bit definitions for INT2_MASK */ 3108 #define TPS65917_INT2_MASK_SHORT 0x40 3109 #define TPS65917_INT2_MASK_SHORT_SHIFT 0x06 3110 #define TPS65917_INT2_MASK_FSD 0x20 3111 #define TPS65917_INT2_MASK_FSD_SHIFT 0x05 3112 #define TPS65917_INT2_MASK_RESET_IN 0x10 3113 #define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04 3114 #define TPS65917_INT2_MASK_WDT 0x04 3115 #define TPS65917_INT2_MASK_WDT_SHIFT 0x02 3116 #define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02 3117 #define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01 3118 3119 /* Bit definitions for INT2_LINE_STATE */ 3120 #define TPS65917_INT2_LINE_STATE_SHORT 0x40 3121 #define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06 3122 #define TPS65917_INT2_LINE_STATE_FSD 0x20 3123 #define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05 3124 #define TPS65917_INT2_LINE_STATE_RESET_IN 0x10 3125 #define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04 3126 #define TPS65917_INT2_LINE_STATE_WDT 0x04 3127 #define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02 3128 #define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02 3129 #define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01 3130 3131 /* Bit definitions for INT3_STATUS */ 3132 #define TPS65917_INT3_STATUS_VBUS 0x80 3133 #define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07 3134 #define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04 3135 #define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02 3136 #define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02 3137 #define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01 3138 #define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01 3139 #define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00 3140 3141 /* Bit definitions for INT3_MASK */ 3142 #define TPS65917_INT3_MASK_VBUS 0x80 3143 #define TPS65917_INT3_MASK_VBUS_SHIFT 0x07 3144 #define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04 3145 #define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02 3146 #define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02 3147 #define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01 3148 #define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01 3149 #define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00 3150 3151 /* Bit definitions for INT3_LINE_STATE */ 3152 #define TPS65917_INT3_LINE_STATE_VBUS 0x80 3153 #define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07 3154 #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04 3155 #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02 3156 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02 3157 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01 3158 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01 3159 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00 3160 3161 /* Bit definitions for INT4_STATUS */ 3162 #define TPS65917_INT4_STATUS_GPIO_6 0x40 3163 #define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06 3164 #define TPS65917_INT4_STATUS_GPIO_5 0x20 3165 #define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05 3166 #define TPS65917_INT4_STATUS_GPIO_4 0x10 3167 #define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04 3168 #define TPS65917_INT4_STATUS_GPIO_3 0x08 3169 #define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03 3170 #define TPS65917_INT4_STATUS_GPIO_2 0x04 3171 #define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02 3172 #define TPS65917_INT4_STATUS_GPIO_1 0x02 3173 #define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01 3174 #define TPS65917_INT4_STATUS_GPIO_0 0x01 3175 #define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00 3176 3177 /* Bit definitions for INT4_MASK */ 3178 #define TPS65917_INT4_MASK_GPIO_6 0x40 3179 #define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06 3180 #define TPS65917_INT4_MASK_GPIO_5 0x20 3181 #define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05 3182 #define TPS65917_INT4_MASK_GPIO_4 0x10 3183 #define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04 3184 #define TPS65917_INT4_MASK_GPIO_3 0x08 3185 #define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03 3186 #define TPS65917_INT4_MASK_GPIO_2 0x04 3187 #define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02 3188 #define TPS65917_INT4_MASK_GPIO_1 0x02 3189 #define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01 3190 #define TPS65917_INT4_MASK_GPIO_0 0x01 3191 #define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00 3192 3193 /* Bit definitions for INT4_LINE_STATE */ 3194 #define TPS65917_INT4_LINE_STATE_GPIO_6 0x40 3195 #define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06 3196 #define TPS65917_INT4_LINE_STATE_GPIO_5 0x20 3197 #define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05 3198 #define TPS65917_INT4_LINE_STATE_GPIO_4 0x10 3199 #define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04 3200 #define TPS65917_INT4_LINE_STATE_GPIO_3 0x08 3201 #define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03 3202 #define TPS65917_INT4_LINE_STATE_GPIO_2 0x04 3203 #define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02 3204 #define TPS65917_INT4_LINE_STATE_GPIO_1 0x02 3205 #define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01 3206 #define TPS65917_INT4_LINE_STATE_GPIO_0 0x01 3207 #define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00 3208 3209 /* Bit definitions for INT4_EDGE_DETECT1 */ 3210 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 3211 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07 3212 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 3213 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06 3214 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 3215 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05 3216 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 3217 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04 3218 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 3219 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03 3220 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 3221 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02 3222 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 3223 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01 3224 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 3225 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00 3226 3227 /* Bit definitions for INT4_EDGE_DETECT2 */ 3228 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 3229 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05 3230 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 3231 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04 3232 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 3233 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03 3234 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 3235 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02 3236 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 3237 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01 3238 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 3239 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00 3240 3241 /* Bit definitions for INT_CTRL */ 3242 #define TPS65917_INT_CTRL_INT_PENDING 0x04 3243 #define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02 3244 #define TPS65917_INT_CTRL_INT_CLEAR 0x01 3245 #define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00 3246 3247 /* TPS65917 SMPS Registers */ 3248 3249 /* Registers for function SMPS */ 3250 #define TPS65917_SMPS1_CTRL 0x00 3251 #define TPS65917_SMPS1_FORCE 0x02 3252 #define TPS65917_SMPS1_VOLTAGE 0x03 3253 #define TPS65917_SMPS2_CTRL 0x04 3254 #define TPS65917_SMPS2_FORCE 0x06 3255 #define TPS65917_SMPS2_VOLTAGE 0x07 3256 #define TPS65917_SMPS3_CTRL 0x0C 3257 #define TPS65917_SMPS3_FORCE 0x0E 3258 #define TPS65917_SMPS3_VOLTAGE 0x0F 3259 #define TPS65917_SMPS4_CTRL 0x10 3260 #define TPS65917_SMPS4_VOLTAGE 0x13 3261 #define TPS65917_SMPS5_CTRL 0x18 3262 #define TPS65917_SMPS5_VOLTAGE 0x1B 3263 #define TPS65917_SMPS_CTRL 0x24 3264 #define TPS65917_SMPS_PD_CTRL 0x25 3265 #define TPS65917_SMPS_THERMAL_EN 0x27 3266 #define TPS65917_SMPS_THERMAL_STATUS 0x28 3267 #define TPS65917_SMPS_SHORT_STATUS 0x29 3268 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A 3269 #define TPS65917_SMPS_POWERGOOD_MASK1 0x2B 3270 #define TPS65917_SMPS_POWERGOOD_MASK2 0x2C 3271 3272 /* Bit definitions for SMPS1_CTRL */ 3273 #define TPS65917_SMPS1_CTRL_WR_S 0x80 3274 #define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07 3275 #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40 3276 #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 3277 #define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30 3278 #define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04 3279 #define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C 3280 #define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02 3281 #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03 3282 #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00 3283 3284 /* Bit definitions for SMPS1_FORCE */ 3285 #define TPS65917_SMPS1_FORCE_CMD 0x80 3286 #define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07 3287 #define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F 3288 #define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00 3289 3290 /* Bit definitions for SMPS1_VOLTAGE */ 3291 #define TPS65917_SMPS1_VOLTAGE_RANGE 0x80 3292 #define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07 3293 #define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F 3294 #define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00 3295 3296 /* Bit definitions for SMPS2_CTRL */ 3297 #define TPS65917_SMPS2_CTRL_WR_S 0x80 3298 #define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07 3299 #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40 3300 #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 3301 #define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30 3302 #define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04 3303 #define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C 3304 #define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02 3305 #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03 3306 #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00 3307 3308 /* Bit definitions for SMPS2_FORCE */ 3309 #define TPS65917_SMPS2_FORCE_CMD 0x80 3310 #define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07 3311 #define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F 3312 #define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00 3313 3314 /* Bit definitions for SMPS2_VOLTAGE */ 3315 #define TPS65917_SMPS2_VOLTAGE_RANGE 0x80 3316 #define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07 3317 #define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F 3318 #define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00 3319 3320 /* Bit definitions for SMPS3_CTRL */ 3321 #define TPS65917_SMPS3_CTRL_WR_S 0x80 3322 #define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07 3323 #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40 3324 #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 3325 #define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30 3326 #define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04 3327 #define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C 3328 #define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02 3329 #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 3330 #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00 3331 3332 /* Bit definitions for SMPS3_FORCE */ 3333 #define TPS65917_SMPS3_FORCE_CMD 0x80 3334 #define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07 3335 #define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F 3336 #define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00 3337 3338 /* Bit definitions for SMPS3_VOLTAGE */ 3339 #define TPS65917_SMPS3_VOLTAGE_RANGE 0x80 3340 #define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07 3341 #define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F 3342 #define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00 3343 3344 /* Bit definitions for SMPS4_CTRL */ 3345 #define TPS65917_SMPS4_CTRL_WR_S 0x80 3346 #define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07 3347 #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40 3348 #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 3349 #define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30 3350 #define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04 3351 #define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C 3352 #define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02 3353 #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03 3354 #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00 3355 3356 /* Bit definitions for SMPS4_VOLTAGE */ 3357 #define TPS65917_SMPS4_VOLTAGE_RANGE 0x80 3358 #define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07 3359 #define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F 3360 #define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00 3361 3362 /* Bit definitions for SMPS5_CTRL */ 3363 #define TPS65917_SMPS5_CTRL_WR_S 0x80 3364 #define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07 3365 #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40 3366 #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 3367 #define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30 3368 #define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04 3369 #define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C 3370 #define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02 3371 #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03 3372 #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00 3373 3374 /* Bit definitions for SMPS5_VOLTAGE */ 3375 #define TPS65917_SMPS5_VOLTAGE_RANGE 0x80 3376 #define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07 3377 #define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F 3378 #define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00 3379 3380 /* Bit definitions for SMPS_CTRL */ 3381 #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10 3382 #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04 3383 #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03 3384 #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00 3385 3386 /* Bit definitions for SMPS_PD_CTRL */ 3387 #define TPS65917_SMPS_PD_CTRL_SMPS5 0x40 3388 #define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06 3389 #define TPS65917_SMPS_PD_CTRL_SMPS4 0x10 3390 #define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04 3391 #define TPS65917_SMPS_PD_CTRL_SMPS3 0x08 3392 #define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03 3393 #define TPS65917_SMPS_PD_CTRL_SMPS2 0x02 3394 #define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01 3395 #define TPS65917_SMPS_PD_CTRL_SMPS1 0x01 3396 #define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00 3397 3398 /* Bit definitions for SMPS_THERMAL_EN */ 3399 #define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40 3400 #define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06 3401 #define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08 3402 #define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03 3403 #define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01 3404 #define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00 3405 3406 /* Bit definitions for SMPS_THERMAL_STATUS */ 3407 #define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40 3408 #define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06 3409 #define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08 3410 #define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03 3411 #define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01 3412 #define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00 3413 3414 /* Bit definitions for SMPS_SHORT_STATUS */ 3415 #define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40 3416 #define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06 3417 #define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10 3418 #define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04 3419 #define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08 3420 #define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03 3421 #define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02 3422 #define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01 3423 #define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01 3424 #define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00 3425 3426 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ 3427 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40 3428 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06 3429 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10 3430 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04 3431 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08 3432 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03 3433 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02 3434 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01 3435 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01 3436 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00 3437 3438 /* Bit definitions for SMPS_POWERGOOD_MASK1 */ 3439 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40 3440 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06 3441 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10 3442 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04 3443 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08 3444 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03 3445 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02 3446 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01 3447 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01 3448 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00 3449 3450 /* Bit definitions for SMPS_POWERGOOD_MASK2 */ 3451 #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 3452 #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07 3453 #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10 3454 #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04 3455 3456 /* Bit definitions for SMPS_PLL_CTRL */ 3457 3458 #define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08 3459 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03 3460 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04 3461 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02 3462 3463 /* Registers for function LDO */ 3464 #define TPS65917_LDO1_CTRL 0x00 3465 #define TPS65917_LDO1_VOLTAGE 0x01 3466 #define TPS65917_LDO2_CTRL 0x02 3467 #define TPS65917_LDO2_VOLTAGE 0x03 3468 #define TPS65917_LDO3_CTRL 0x04 3469 #define TPS65917_LDO3_VOLTAGE 0x05 3470 #define TPS65917_LDO4_CTRL 0x0E 3471 #define TPS65917_LDO4_VOLTAGE 0x0F 3472 #define TPS65917_LDO5_CTRL 0x12 3473 #define TPS65917_LDO5_VOLTAGE 0x13 3474 #define TPS65917_LDO_PD_CTRL1 0x1B 3475 #define TPS65917_LDO_PD_CTRL2 0x1C 3476 #define TPS65917_LDO_SHORT_STATUS1 0x1D 3477 #define TPS65917_LDO_SHORT_STATUS2 0x1E 3478 #define TPS65917_LDO_PD_CTRL3 0x2D 3479 #define TPS65917_LDO_SHORT_STATUS3 0x2E 3480 3481 /* Bit definitions for LDO1_CTRL */ 3482 #define TPS65917_LDO1_CTRL_WR_S 0x80 3483 #define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07 3484 #define TPS65917_LDO1_CTRL_BYPASS_EN 0x40 3485 #define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06 3486 #define TPS65917_LDO1_CTRL_STATUS 0x10 3487 #define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04 3488 #define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04 3489 #define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02 3490 #define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01 3491 #define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00 3492 3493 /* Bit definitions for LDO1_VOLTAGE */ 3494 #define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F 3495 #define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00 3496 3497 /* Bit definitions for LDO2_CTRL */ 3498 #define TPS65917_LDO2_CTRL_WR_S 0x80 3499 #define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07 3500 #define TPS65917_LDO2_CTRL_BYPASS_EN 0x40 3501 #define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06 3502 #define TPS65917_LDO2_CTRL_STATUS 0x10 3503 #define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04 3504 #define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04 3505 #define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02 3506 #define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01 3507 #define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00 3508 3509 /* Bit definitions for LDO2_VOLTAGE */ 3510 #define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F 3511 #define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00 3512 3513 /* Bit definitions for LDO3_CTRL */ 3514 #define TPS65917_LDO3_CTRL_WR_S 0x80 3515 #define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07 3516 #define TPS65917_LDO3_CTRL_STATUS 0x10 3517 #define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04 3518 #define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04 3519 #define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02 3520 #define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01 3521 #define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00 3522 3523 /* Bit definitions for LDO3_VOLTAGE */ 3524 #define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F 3525 #define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00 3526 3527 /* Bit definitions for LDO4_CTRL */ 3528 #define TPS65917_LDO4_CTRL_WR_S 0x80 3529 #define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07 3530 #define TPS65917_LDO4_CTRL_STATUS 0x10 3531 #define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04 3532 #define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04 3533 #define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02 3534 #define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01 3535 #define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00 3536 3537 /* Bit definitions for LDO4_VOLTAGE */ 3538 #define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F 3539 #define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00 3540 3541 /* Bit definitions for LDO5_CTRL */ 3542 #define TPS65917_LDO5_CTRL_WR_S 0x80 3543 #define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07 3544 #define TPS65917_LDO5_CTRL_STATUS 0x10 3545 #define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04 3546 #define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04 3547 #define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02 3548 #define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01 3549 #define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00 3550 3551 /* Bit definitions for LDO5_VOLTAGE */ 3552 #define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F 3553 #define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00 3554 3555 /* Bit definitions for LDO_PD_CTRL1 */ 3556 #define TPS65917_LDO_PD_CTRL1_LDO4 0x80 3557 #define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07 3558 #define TPS65917_LDO_PD_CTRL1_LDO2 0x02 3559 #define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01 3560 #define TPS65917_LDO_PD_CTRL1_LDO1 0x01 3561 #define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00 3562 3563 /* Bit definitions for LDO_PD_CTRL2 */ 3564 #define TPS65917_LDO_PD_CTRL2_LDO3 0x04 3565 #define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02 3566 #define TPS65917_LDO_PD_CTRL2_LDO5 0x02 3567 #define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01 3568 3569 /* Bit definitions for LDO_PD_CTRL3 */ 3570 #define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80 3571 #define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07 3572 3573 /* Bit definitions for LDO_SHORT_STATUS1 */ 3574 #define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80 3575 #define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07 3576 #define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02 3577 #define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01 3578 #define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01 3579 #define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00 3580 3581 /* Bit definitions for LDO_SHORT_STATUS2 */ 3582 #define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04 3583 #define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02 3584 #define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02 3585 #define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01 3586 3587 /* Bit definitions for LDO_SHORT_STATUS2 */ 3588 #define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80 3589 #define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07 3590 3591 /* Bit definitions for REGEN1_CTRL */ 3592 #define TPS65917_REGEN1_CTRL_STATUS 0x10 3593 #define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04 3594 #define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04 3595 #define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02 3596 #define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01 3597 #define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 3598 3599 /* Bit definitions for PLLEN_CTRL */ 3600 #define TPS65917_PLLEN_CTRL_STATUS 0x10 3601 #define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04 3602 #define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04 3603 #define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02 3604 #define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01 3605 #define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00 3606 3607 /* Bit definitions for REGEN2_CTRL */ 3608 #define TPS65917_REGEN2_CTRL_STATUS 0x10 3609 #define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04 3610 #define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04 3611 #define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02 3612 #define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01 3613 #define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 3614 3615 /* Bit definitions for NSLEEP_RES_ASSIGN */ 3616 #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08 3617 #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03 3618 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04 3619 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02 3620 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02 3621 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01 3622 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01 3623 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00 3624 3625 /* Bit definitions for NSLEEP_SMPS_ASSIGN */ 3626 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40 3627 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06 3628 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10 3629 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04 3630 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08 3631 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03 3632 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02 3633 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01 3634 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01 3635 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00 3636 3637 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */ 3638 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80 3639 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07 3640 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02 3641 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01 3642 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01 3643 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00 3644 3645 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */ 3646 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04 3647 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02 3648 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02 3649 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01 3650 3651 /* Bit definitions for ENABLE1_RES_ASSIGN */ 3652 #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08 3653 #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03 3654 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04 3655 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02 3656 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02 3657 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01 3658 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01 3659 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00 3660 3661 /* Bit definitions for ENABLE1_SMPS_ASSIGN */ 3662 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40 3663 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06 3664 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10 3665 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04 3666 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08 3667 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03 3668 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02 3669 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01 3670 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01 3671 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00 3672 3673 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */ 3674 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80 3675 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07 3676 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02 3677 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01 3678 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01 3679 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00 3680 3681 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */ 3682 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04 3683 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02 3684 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02 3685 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01 3686 3687 /* Bit definitions for ENABLE2_RES_ASSIGN */ 3688 #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08 3689 #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03 3690 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04 3691 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02 3692 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02 3693 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01 3694 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01 3695 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00 3696 3697 /* Bit definitions for ENABLE2_SMPS_ASSIGN */ 3698 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40 3699 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06 3700 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10 3701 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04 3702 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08 3703 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03 3704 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02 3705 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01 3706 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01 3707 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00 3708 3709 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */ 3710 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80 3711 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07 3712 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02 3713 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01 3714 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01 3715 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00 3716 3717 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */ 3718 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04 3719 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02 3720 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02 3721 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01 3722 3723 /* Bit definitions for REGEN3_CTRL */ 3724 #define TPS65917_REGEN3_CTRL_STATUS 0x10 3725 #define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04 3726 #define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04 3727 #define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02 3728 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01 3729 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00 3730 3731 /* Registers for function RESOURCE */ 3732 #define TPS65917_REGEN1_CTRL 0x2 3733 #define TPS65917_PLLEN_CTRL 0x3 3734 #define TPS65917_NSLEEP_RES_ASSIGN 0x6 3735 #define TPS65917_NSLEEP_SMPS_ASSIGN 0x7 3736 #define TPS65917_NSLEEP_LDO_ASSIGN1 0x8 3737 #define TPS65917_NSLEEP_LDO_ASSIGN2 0x9 3738 #define TPS65917_ENABLE1_RES_ASSIGN 0xA 3739 #define TPS65917_ENABLE1_SMPS_ASSIGN 0xB 3740 #define TPS65917_ENABLE1_LDO_ASSIGN1 0xC 3741 #define TPS65917_ENABLE1_LDO_ASSIGN2 0xD 3742 #define TPS65917_ENABLE2_RES_ASSIGN 0xE 3743 #define TPS65917_ENABLE2_SMPS_ASSIGN 0xF 3744 #define TPS65917_ENABLE2_LDO_ASSIGN1 0x10 3745 #define TPS65917_ENABLE2_LDO_ASSIGN2 0x11 3746 #define TPS65917_REGEN2_CTRL 0x12 3747 #define TPS65917_REGEN3_CTRL 0x13 3748 3749 static inline int palmas_read(struct palmas *palmas, unsigned int base, 3750 unsigned int reg, unsigned int *val) 3751 { 3752 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 3753 int slave_id = PALMAS_BASE_TO_SLAVE(base); 3754 3755 return regmap_read(palmas->regmap[slave_id], addr, val); 3756 } 3757 3758 static inline int palmas_write(struct palmas *palmas, unsigned int base, 3759 unsigned int reg, unsigned int value) 3760 { 3761 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 3762 int slave_id = PALMAS_BASE_TO_SLAVE(base); 3763 3764 return regmap_write(palmas->regmap[slave_id], addr, value); 3765 } 3766 3767 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base, 3768 unsigned int reg, const void *val, size_t val_count) 3769 { 3770 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 3771 int slave_id = PALMAS_BASE_TO_SLAVE(base); 3772 3773 return regmap_bulk_write(palmas->regmap[slave_id], addr, 3774 val, val_count); 3775 } 3776 3777 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base, 3778 unsigned int reg, void *val, size_t val_count) 3779 { 3780 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 3781 int slave_id = PALMAS_BASE_TO_SLAVE(base); 3782 3783 return regmap_bulk_read(palmas->regmap[slave_id], addr, 3784 val, val_count); 3785 } 3786 3787 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base, 3788 unsigned int reg, unsigned int mask, unsigned int val) 3789 { 3790 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 3791 int slave_id = PALMAS_BASE_TO_SLAVE(base); 3792 3793 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val); 3794 } 3795 3796 static inline int palmas_irq_get_virq(struct palmas *palmas, int irq) 3797 { 3798 return regmap_irq_get_virq(palmas->irq_data, irq); 3799 } 3800 3801 3802 int palmas_ext_control_req_config(struct palmas *palmas, 3803 enum palmas_external_requestor_id ext_control_req_id, 3804 int ext_ctrl, bool enable); 3805 3806 #endif /* __LINUX_MFD_PALMAS_H */ 3807