1 /* 2 * TI Palmas 3 * 4 * Copyright 2011-2013 Texas Instruments Inc. 5 * 6 * Author: Graeme Gregory <[email protected]> 7 * Author: Ian Lartey <[email protected]> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 */ 15 16 #ifndef __LINUX_MFD_PALMAS_H 17 #define __LINUX_MFD_PALMAS_H 18 19 #include <linux/usb/otg.h> 20 #include <linux/leds.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/driver.h> 23 #include <linux/extcon.h> 24 #include <linux/usb/phy_companion.h> 25 26 #define PALMAS_NUM_CLIENTS 3 27 28 /* The ID_REVISION NUMBERS */ 29 #define PALMAS_CHIP_OLD_ID 0x0000 30 #define PALMAS_CHIP_ID 0xC035 31 #define PALMAS_CHIP_CHARGER_ID 0xC036 32 33 #define TPS65917_RESERVED -1 34 35 #define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \ 36 ((a) == PALMAS_CHIP_ID)) 37 #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID) 38 39 /** 40 * Palmas PMIC feature types 41 * 42 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST 43 * regulator. 44 * 45 * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a 46 * specific feature (above) or not. Return non-zero, if yes. 47 */ 48 #define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0) 49 #define PALMAS_PMIC_HAS(b, f) \ 50 ((b)->features & PALMAS_PMIC_FEATURE_ ## f) 51 52 struct palmas_pmic; 53 struct palmas_gpadc; 54 struct palmas_resource; 55 struct palmas_usb; 56 struct palmas_pmic_driver_data; 57 struct palmas_pmic_platform_data; 58 59 enum palmas_usb_state { 60 PALMAS_USB_STATE_DISCONNECT, 61 PALMAS_USB_STATE_VBUS, 62 PALMAS_USB_STATE_ID, 63 }; 64 65 struct palmas { 66 struct device *dev; 67 68 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS]; 69 struct regmap *regmap[PALMAS_NUM_CLIENTS]; 70 71 /* Stored chip id */ 72 int id; 73 74 unsigned int features; 75 /* IRQ Data */ 76 int irq; 77 u32 irq_mask; 78 struct mutex irq_lock; 79 struct regmap_irq_chip_data *irq_data; 80 81 struct palmas_pmic_driver_data *pmic_ddata; 82 83 /* Child Devices */ 84 struct palmas_pmic *pmic; 85 struct palmas_gpadc *gpadc; 86 struct palmas_resource *resource; 87 struct palmas_usb *usb; 88 89 /* GPIO MUXing */ 90 u8 gpio_muxed; 91 u8 led_muxed; 92 u8 pwm_muxed; 93 }; 94 95 #define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \ 96 PALMAS_EXT_CONTROL_ENABLE2 | \ 97 PALMAS_EXT_CONTROL_NSLEEP) 98 99 struct palmas_sleep_requestor_info { 100 int id; 101 int reg_offset; 102 int bit_pos; 103 }; 104 105 struct palmas_regs_info { 106 char *name; 107 char *sname; 108 u8 vsel_addr; 109 u8 ctrl_addr; 110 u8 tstep_addr; 111 int sleep_id; 112 }; 113 114 struct palmas_pmic_driver_data { 115 int smps_start; 116 int smps_end; 117 int ldo_begin; 118 int ldo_end; 119 int max_reg; 120 struct palmas_regs_info *palmas_regs_info; 121 struct of_regulator_match *palmas_matches; 122 struct palmas_sleep_requestor_info *sleep_req_info; 123 int (*smps_register)(struct palmas_pmic *pmic, 124 struct palmas_pmic_driver_data *ddata, 125 struct palmas_pmic_platform_data *pdata, 126 const char *pdev_name, 127 struct regulator_config config); 128 int (*ldo_register)(struct palmas_pmic *pmic, 129 struct palmas_pmic_driver_data *ddata, 130 struct palmas_pmic_platform_data *pdata, 131 const char *pdev_name, 132 struct regulator_config config); 133 }; 134 135 struct palmas_gpadc_platform_data { 136 /* Channel 3 current source is only enabled during conversion */ 137 int ch3_current; 138 139 /* Channel 0 current source can be used for battery detection. 140 * If used for battery detection this will cause a permanent current 141 * consumption depending on current level set here. 142 */ 143 int ch0_current; 144 145 /* default BAT_REMOVAL_DAT setting on device probe */ 146 int bat_removal; 147 148 /* Sets the START_POLARITY bit in the RT_CTRL register */ 149 int start_polarity; 150 }; 151 152 struct palmas_reg_init { 153 /* warm_rest controls the voltage levels after a warm reset 154 * 155 * 0: reload default values from OTP on warm reset 156 * 1: maintain voltage from VSEL on warm reset 157 */ 158 int warm_reset; 159 160 /* roof_floor controls whether the regulator uses the i2c style 161 * of DVS or uses the method where a GPIO or other control method is 162 * attached to the NSLEEP/ENABLE1/ENABLE2 pins 163 * 164 * For SMPS 165 * 166 * 0: i2c selection of voltage 167 * 1: pin selection of voltage. 168 * 169 * For LDO unused 170 */ 171 int roof_floor; 172 173 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in 174 * the data sheet. 175 * 176 * For SMPS 177 * 178 * 0: Off 179 * 1: AUTO 180 * 2: ECO 181 * 3: Forced PWM 182 * 183 * For LDO 184 * 185 * 0: Off 186 * 1: On 187 */ 188 int mode_sleep; 189 190 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE 191 * register. Set this is the default voltage set in OTP needs 192 * to be overridden. 193 */ 194 u8 vsel; 195 196 }; 197 198 enum palmas_regulators { 199 /* SMPS regulators */ 200 PALMAS_REG_SMPS12, 201 PALMAS_REG_SMPS123, 202 PALMAS_REG_SMPS3, 203 PALMAS_REG_SMPS45, 204 PALMAS_REG_SMPS457, 205 PALMAS_REG_SMPS6, 206 PALMAS_REG_SMPS7, 207 PALMAS_REG_SMPS8, 208 PALMAS_REG_SMPS9, 209 PALMAS_REG_SMPS10_OUT2, 210 PALMAS_REG_SMPS10_OUT1, 211 /* LDO regulators */ 212 PALMAS_REG_LDO1, 213 PALMAS_REG_LDO2, 214 PALMAS_REG_LDO3, 215 PALMAS_REG_LDO4, 216 PALMAS_REG_LDO5, 217 PALMAS_REG_LDO6, 218 PALMAS_REG_LDO7, 219 PALMAS_REG_LDO8, 220 PALMAS_REG_LDO9, 221 PALMAS_REG_LDOLN, 222 PALMAS_REG_LDOUSB, 223 /* External regulators */ 224 PALMAS_REG_REGEN1, 225 PALMAS_REG_REGEN2, 226 PALMAS_REG_REGEN3, 227 PALMAS_REG_SYSEN1, 228 PALMAS_REG_SYSEN2, 229 /* Total number of regulators */ 230 PALMAS_NUM_REGS, 231 }; 232 233 enum tps65917_regulators { 234 /* SMPS regulators */ 235 TPS65917_REG_SMPS1, 236 TPS65917_REG_SMPS2, 237 TPS65917_REG_SMPS3, 238 TPS65917_REG_SMPS4, 239 TPS65917_REG_SMPS5, 240 /* LDO regulators */ 241 TPS65917_REG_LDO1, 242 TPS65917_REG_LDO2, 243 TPS65917_REG_LDO3, 244 TPS65917_REG_LDO4, 245 TPS65917_REG_LDO5, 246 TPS65917_REG_REGEN1, 247 TPS65917_REG_REGEN2, 248 TPS65917_REG_REGEN3, 249 250 /* Total number of regulators */ 251 TPS65917_NUM_REGS, 252 }; 253 254 /* External controll signal name */ 255 enum { 256 PALMAS_EXT_CONTROL_ENABLE1 = 0x1, 257 PALMAS_EXT_CONTROL_ENABLE2 = 0x2, 258 PALMAS_EXT_CONTROL_NSLEEP = 0x4, 259 }; 260 261 /* 262 * Palmas device resources can be controlled externally for 263 * enabling/disabling it rather than register write through i2c. 264 * Add the external controlled requestor ID for different resources. 265 */ 266 enum palmas_external_requestor_id { 267 PALMAS_EXTERNAL_REQSTR_ID_REGEN1, 268 PALMAS_EXTERNAL_REQSTR_ID_REGEN2, 269 PALMAS_EXTERNAL_REQSTR_ID_SYSEN1, 270 PALMAS_EXTERNAL_REQSTR_ID_SYSEN2, 271 PALMAS_EXTERNAL_REQSTR_ID_CLK32KG, 272 PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO, 273 PALMAS_EXTERNAL_REQSTR_ID_REGEN3, 274 PALMAS_EXTERNAL_REQSTR_ID_SMPS12, 275 PALMAS_EXTERNAL_REQSTR_ID_SMPS3, 276 PALMAS_EXTERNAL_REQSTR_ID_SMPS45, 277 PALMAS_EXTERNAL_REQSTR_ID_SMPS6, 278 PALMAS_EXTERNAL_REQSTR_ID_SMPS7, 279 PALMAS_EXTERNAL_REQSTR_ID_SMPS8, 280 PALMAS_EXTERNAL_REQSTR_ID_SMPS9, 281 PALMAS_EXTERNAL_REQSTR_ID_SMPS10, 282 PALMAS_EXTERNAL_REQSTR_ID_LDO1, 283 PALMAS_EXTERNAL_REQSTR_ID_LDO2, 284 PALMAS_EXTERNAL_REQSTR_ID_LDO3, 285 PALMAS_EXTERNAL_REQSTR_ID_LDO4, 286 PALMAS_EXTERNAL_REQSTR_ID_LDO5, 287 PALMAS_EXTERNAL_REQSTR_ID_LDO6, 288 PALMAS_EXTERNAL_REQSTR_ID_LDO7, 289 PALMAS_EXTERNAL_REQSTR_ID_LDO8, 290 PALMAS_EXTERNAL_REQSTR_ID_LDO9, 291 PALMAS_EXTERNAL_REQSTR_ID_LDOLN, 292 PALMAS_EXTERNAL_REQSTR_ID_LDOUSB, 293 294 /* Last entry */ 295 PALMAS_EXTERNAL_REQSTR_ID_MAX, 296 }; 297 298 enum tps65917_external_requestor_id { 299 TPS65917_EXTERNAL_REQSTR_ID_REGEN1, 300 TPS65917_EXTERNAL_REQSTR_ID_REGEN2, 301 TPS65917_EXTERNAL_REQSTR_ID_REGEN3, 302 TPS65917_EXTERNAL_REQSTR_ID_SMPS1, 303 TPS65917_EXTERNAL_REQSTR_ID_SMPS2, 304 TPS65917_EXTERNAL_REQSTR_ID_SMPS3, 305 TPS65917_EXTERNAL_REQSTR_ID_SMPS4, 306 TPS65917_EXTERNAL_REQSTR_ID_SMPS5, 307 TPS65917_EXTERNAL_REQSTR_ID_LDO1, 308 TPS65917_EXTERNAL_REQSTR_ID_LDO2, 309 TPS65917_EXTERNAL_REQSTR_ID_LDO3, 310 TPS65917_EXTERNAL_REQSTR_ID_LDO4, 311 TPS65917_EXTERNAL_REQSTR_ID_LDO5, 312 /* Last entry */ 313 TPS65917_EXTERNAL_REQSTR_ID_MAX, 314 }; 315 316 struct palmas_pmic_platform_data { 317 /* An array of pointers to regulator init data indexed by regulator 318 * ID 319 */ 320 struct regulator_init_data *reg_data[PALMAS_NUM_REGS]; 321 322 /* An array of pointers to structures containing sleep mode and DVS 323 * configuration for regulators indexed by ID 324 */ 325 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS]; 326 327 /* use LDO6 for vibrator control */ 328 int ldo6_vibrator; 329 330 /* Enable tracking mode of LDO8 */ 331 bool enable_ldo8_tracking; 332 }; 333 334 struct palmas_usb_platform_data { 335 /* Do we enable the wakeup comparator on probe */ 336 int wakeup; 337 }; 338 339 struct palmas_resource_platform_data { 340 int regen1_mode_sleep; 341 int regen2_mode_sleep; 342 int sysen1_mode_sleep; 343 int sysen2_mode_sleep; 344 345 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */ 346 u8 nsleep_res; 347 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */ 348 u8 nsleep_smps; 349 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */ 350 u8 nsleep_ldo1; 351 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */ 352 u8 nsleep_ldo2; 353 354 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */ 355 u8 enable1_res; 356 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */ 357 u8 enable1_smps; 358 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */ 359 u8 enable1_ldo1; 360 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */ 361 u8 enable1_ldo2; 362 363 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */ 364 u8 enable2_res; 365 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */ 366 u8 enable2_smps; 367 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */ 368 u8 enable2_ldo1; 369 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */ 370 u8 enable2_ldo2; 371 }; 372 373 struct palmas_clk_platform_data { 374 int clk32kg_mode_sleep; 375 int clk32kgaudio_mode_sleep; 376 }; 377 378 struct palmas_platform_data { 379 int irq_flags; 380 int gpio_base; 381 382 /* bit value to be loaded to the POWER_CTRL register */ 383 u8 power_ctrl; 384 385 /* 386 * boolean to select if we want to configure muxing here 387 * then the two value to load into the registers if true 388 */ 389 int mux_from_pdata; 390 u8 pad1, pad2; 391 bool pm_off; 392 393 struct palmas_pmic_platform_data *pmic_pdata; 394 struct palmas_gpadc_platform_data *gpadc_pdata; 395 struct palmas_usb_platform_data *usb_pdata; 396 struct palmas_resource_platform_data *resource_pdata; 397 struct palmas_clk_platform_data *clk_pdata; 398 }; 399 400 struct palmas_gpadc_calibration { 401 s32 gain; 402 s32 gain_error; 403 s32 offset_error; 404 }; 405 406 struct palmas_gpadc { 407 struct device *dev; 408 struct palmas *palmas; 409 410 int ch3_current; 411 int ch0_current; 412 413 int gpadc_force; 414 415 int bat_removal; 416 417 struct mutex reading_lock; 418 struct completion irq_complete; 419 420 int eoc_sw_irq; 421 422 struct palmas_gpadc_calibration *palmas_cal_tbl; 423 424 int conv0_channel; 425 int conv1_channel; 426 int rt_channel; 427 }; 428 429 struct palmas_gpadc_result { 430 s32 raw_code; 431 s32 corrected_code; 432 s32 result; 433 }; 434 435 #define PALMAS_MAX_CHANNELS 16 436 437 /* Define the tps65917 IRQ numbers */ 438 enum tps65917_irqs { 439 /* INT1 registers */ 440 TPS65917_RESERVED1, 441 TPS65917_PWRON_IRQ, 442 TPS65917_LONG_PRESS_KEY_IRQ, 443 TPS65917_RESERVED2, 444 TPS65917_PWRDOWN_IRQ, 445 TPS65917_HOTDIE_IRQ, 446 TPS65917_VSYS_MON_IRQ, 447 TPS65917_RESERVED3, 448 /* INT2 registers */ 449 TPS65917_RESERVED4, 450 TPS65917_OTP_ERROR_IRQ, 451 TPS65917_WDT_IRQ, 452 TPS65917_RESERVED5, 453 TPS65917_RESET_IN_IRQ, 454 TPS65917_FSD_IRQ, 455 TPS65917_SHORT_IRQ, 456 TPS65917_RESERVED6, 457 /* INT3 registers */ 458 TPS65917_GPADC_AUTO_0_IRQ, 459 TPS65917_GPADC_AUTO_1_IRQ, 460 TPS65917_GPADC_EOC_SW_IRQ, 461 TPS65917_RESREVED6, 462 TPS65917_RESERVED7, 463 TPS65917_RESERVED8, 464 TPS65917_RESERVED9, 465 TPS65917_VBUS_IRQ, 466 /* INT4 registers */ 467 TPS65917_GPIO_0_IRQ, 468 TPS65917_GPIO_1_IRQ, 469 TPS65917_GPIO_2_IRQ, 470 TPS65917_GPIO_3_IRQ, 471 TPS65917_GPIO_4_IRQ, 472 TPS65917_GPIO_5_IRQ, 473 TPS65917_GPIO_6_IRQ, 474 TPS65917_RESERVED10, 475 /* Total Number IRQs */ 476 TPS65917_NUM_IRQ, 477 }; 478 479 /* Define the palmas IRQ numbers */ 480 enum palmas_irqs { 481 /* INT1 registers */ 482 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ, 483 PALMAS_PWRON_IRQ, 484 PALMAS_LONG_PRESS_KEY_IRQ, 485 PALMAS_RPWRON_IRQ, 486 PALMAS_PWRDOWN_IRQ, 487 PALMAS_HOTDIE_IRQ, 488 PALMAS_VSYS_MON_IRQ, 489 PALMAS_VBAT_MON_IRQ, 490 /* INT2 registers */ 491 PALMAS_RTC_ALARM_IRQ, 492 PALMAS_RTC_TIMER_IRQ, 493 PALMAS_WDT_IRQ, 494 PALMAS_BATREMOVAL_IRQ, 495 PALMAS_RESET_IN_IRQ, 496 PALMAS_FBI_BB_IRQ, 497 PALMAS_SHORT_IRQ, 498 PALMAS_VAC_ACOK_IRQ, 499 /* INT3 registers */ 500 PALMAS_GPADC_AUTO_0_IRQ, 501 PALMAS_GPADC_AUTO_1_IRQ, 502 PALMAS_GPADC_EOC_SW_IRQ, 503 PALMAS_GPADC_EOC_RT_IRQ, 504 PALMAS_ID_OTG_IRQ, 505 PALMAS_ID_IRQ, 506 PALMAS_VBUS_OTG_IRQ, 507 PALMAS_VBUS_IRQ, 508 /* INT4 registers */ 509 PALMAS_GPIO_0_IRQ, 510 PALMAS_GPIO_1_IRQ, 511 PALMAS_GPIO_2_IRQ, 512 PALMAS_GPIO_3_IRQ, 513 PALMAS_GPIO_4_IRQ, 514 PALMAS_GPIO_5_IRQ, 515 PALMAS_GPIO_6_IRQ, 516 PALMAS_GPIO_7_IRQ, 517 /* Total Number IRQs */ 518 PALMAS_NUM_IRQ, 519 }; 520 521 struct palmas_pmic { 522 struct palmas *palmas; 523 struct device *dev; 524 struct regulator_desc desc[PALMAS_NUM_REGS]; 525 struct regulator_dev *rdev[PALMAS_NUM_REGS]; 526 struct mutex mutex; 527 528 int smps123; 529 int smps457; 530 int smps12; 531 532 int range[PALMAS_REG_SMPS10_OUT1]; 533 unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1]; 534 unsigned int current_reg_mode[PALMAS_REG_SMPS10_OUT1]; 535 }; 536 537 struct palmas_resource { 538 struct palmas *palmas; 539 struct device *dev; 540 }; 541 542 struct palmas_usb { 543 struct palmas *palmas; 544 struct device *dev; 545 546 struct extcon_dev *edev; 547 548 int id_otg_irq; 549 int id_irq; 550 int vbus_otg_irq; 551 int vbus_irq; 552 553 enum palmas_usb_state linkstat; 554 int wakeup; 555 bool enable_vbus_detection; 556 bool enable_id_detection; 557 }; 558 559 #define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator) 560 561 enum usb_irq_events { 562 /* Wakeup events from INT3 */ 563 PALMAS_USB_ID_WAKEPUP, 564 PALMAS_USB_VBUS_WAKEUP, 565 566 /* ID_OTG_EVENTS */ 567 PALMAS_USB_ID_GND, 568 N_PALMAS_USB_ID_GND, 569 PALMAS_USB_ID_C, 570 N_PALMAS_USB_ID_C, 571 PALMAS_USB_ID_B, 572 N_PALMAS_USB_ID_B, 573 PALMAS_USB_ID_A, 574 N_PALMAS_USB_ID_A, 575 PALMAS_USB_ID_FLOAT, 576 N_PALMAS_USB_ID_FLOAT, 577 578 /* VBUS_OTG_EVENTS */ 579 PALMAS_USB_VB_SESS_END, 580 N_PALMAS_USB_VB_SESS_END, 581 PALMAS_USB_VB_SESS_VLD, 582 N_PALMAS_USB_VB_SESS_VLD, 583 PALMAS_USB_VA_SESS_VLD, 584 N_PALMAS_USB_VA_SESS_VLD, 585 PALMAS_USB_VA_VBUS_VLD, 586 N_PALMAS_USB_VA_VBUS_VLD, 587 PALMAS_USB_VADP_SNS, 588 N_PALMAS_USB_VADP_SNS, 589 PALMAS_USB_VADP_PRB, 590 N_PALMAS_USB_VADP_PRB, 591 PALMAS_USB_VOTG_SESS_VLD, 592 N_PALMAS_USB_VOTG_SESS_VLD, 593 }; 594 595 /* defines so we can store the mux settings */ 596 #define PALMAS_GPIO_0_MUXED (1 << 0) 597 #define PALMAS_GPIO_1_MUXED (1 << 1) 598 #define PALMAS_GPIO_2_MUXED (1 << 2) 599 #define PALMAS_GPIO_3_MUXED (1 << 3) 600 #define PALMAS_GPIO_4_MUXED (1 << 4) 601 #define PALMAS_GPIO_5_MUXED (1 << 5) 602 #define PALMAS_GPIO_6_MUXED (1 << 6) 603 #define PALMAS_GPIO_7_MUXED (1 << 7) 604 605 #define PALMAS_LED1_MUXED (1 << 0) 606 #define PALMAS_LED2_MUXED (1 << 1) 607 608 #define PALMAS_PWM1_MUXED (1 << 0) 609 #define PALMAS_PWM2_MUXED (1 << 1) 610 611 /* helper macro to get correct slave number */ 612 #define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1) 613 #define PALMAS_BASE_TO_REG(x, y) ((x & 0xFF) + y) 614 615 /* Base addresses of IP blocks in Palmas */ 616 #define PALMAS_SMPS_DVS_BASE 0x020 617 #define PALMAS_RTC_BASE 0x100 618 #define PALMAS_VALIDITY_BASE 0x118 619 #define PALMAS_SMPS_BASE 0x120 620 #define PALMAS_LDO_BASE 0x150 621 #define PALMAS_DVFS_BASE 0x180 622 #define PALMAS_PMU_CONTROL_BASE 0x1A0 623 #define PALMAS_RESOURCE_BASE 0x1D4 624 #define PALMAS_PU_PD_OD_BASE 0x1F0 625 #define PALMAS_LED_BASE 0x200 626 #define PALMAS_INTERRUPT_BASE 0x210 627 #define PALMAS_USB_OTG_BASE 0x250 628 #define PALMAS_VIBRATOR_BASE 0x270 629 #define PALMAS_GPIO_BASE 0x280 630 #define PALMAS_USB_BASE 0x290 631 #define PALMAS_GPADC_BASE 0x2C0 632 #define PALMAS_TRIM_GPADC_BASE 0x3CD 633 634 /* Registers for function RTC */ 635 #define PALMAS_SECONDS_REG 0x00 636 #define PALMAS_MINUTES_REG 0x01 637 #define PALMAS_HOURS_REG 0x02 638 #define PALMAS_DAYS_REG 0x03 639 #define PALMAS_MONTHS_REG 0x04 640 #define PALMAS_YEARS_REG 0x05 641 #define PALMAS_WEEKS_REG 0x06 642 #define PALMAS_ALARM_SECONDS_REG 0x08 643 #define PALMAS_ALARM_MINUTES_REG 0x09 644 #define PALMAS_ALARM_HOURS_REG 0x0A 645 #define PALMAS_ALARM_DAYS_REG 0x0B 646 #define PALMAS_ALARM_MONTHS_REG 0x0C 647 #define PALMAS_ALARM_YEARS_REG 0x0D 648 #define PALMAS_RTC_CTRL_REG 0x10 649 #define PALMAS_RTC_STATUS_REG 0x11 650 #define PALMAS_RTC_INTERRUPTS_REG 0x12 651 #define PALMAS_RTC_COMP_LSB_REG 0x13 652 #define PALMAS_RTC_COMP_MSB_REG 0x14 653 #define PALMAS_RTC_RES_PROG_REG 0x15 654 #define PALMAS_RTC_RESET_STATUS_REG 0x16 655 656 /* Bit definitions for SECONDS_REG */ 657 #define PALMAS_SECONDS_REG_SEC1_MASK 0x70 658 #define PALMAS_SECONDS_REG_SEC1_SHIFT 0x04 659 #define PALMAS_SECONDS_REG_SEC0_MASK 0x0F 660 #define PALMAS_SECONDS_REG_SEC0_SHIFT 0x00 661 662 /* Bit definitions for MINUTES_REG */ 663 #define PALMAS_MINUTES_REG_MIN1_MASK 0x70 664 #define PALMAS_MINUTES_REG_MIN1_SHIFT 0x04 665 #define PALMAS_MINUTES_REG_MIN0_MASK 0x0F 666 #define PALMAS_MINUTES_REG_MIN0_SHIFT 0x00 667 668 /* Bit definitions for HOURS_REG */ 669 #define PALMAS_HOURS_REG_PM_NAM 0x80 670 #define PALMAS_HOURS_REG_PM_NAM_SHIFT 0x07 671 #define PALMAS_HOURS_REG_HOUR1_MASK 0x30 672 #define PALMAS_HOURS_REG_HOUR1_SHIFT 0x04 673 #define PALMAS_HOURS_REG_HOUR0_MASK 0x0F 674 #define PALMAS_HOURS_REG_HOUR0_SHIFT 0x00 675 676 /* Bit definitions for DAYS_REG */ 677 #define PALMAS_DAYS_REG_DAY1_MASK 0x30 678 #define PALMAS_DAYS_REG_DAY1_SHIFT 0x04 679 #define PALMAS_DAYS_REG_DAY0_MASK 0x0F 680 #define PALMAS_DAYS_REG_DAY0_SHIFT 0x00 681 682 /* Bit definitions for MONTHS_REG */ 683 #define PALMAS_MONTHS_REG_MONTH1 0x10 684 #define PALMAS_MONTHS_REG_MONTH1_SHIFT 0x04 685 #define PALMAS_MONTHS_REG_MONTH0_MASK 0x0F 686 #define PALMAS_MONTHS_REG_MONTH0_SHIFT 0x00 687 688 /* Bit definitions for YEARS_REG */ 689 #define PALMAS_YEARS_REG_YEAR1_MASK 0xf0 690 #define PALMAS_YEARS_REG_YEAR1_SHIFT 0x04 691 #define PALMAS_YEARS_REG_YEAR0_MASK 0x0F 692 #define PALMAS_YEARS_REG_YEAR0_SHIFT 0x00 693 694 /* Bit definitions for WEEKS_REG */ 695 #define PALMAS_WEEKS_REG_WEEK_MASK 0x07 696 #define PALMAS_WEEKS_REG_WEEK_SHIFT 0x00 697 698 /* Bit definitions for ALARM_SECONDS_REG */ 699 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70 700 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 0x04 701 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0F 702 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0x00 703 704 /* Bit definitions for ALARM_MINUTES_REG */ 705 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70 706 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 0x04 707 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0F 708 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0x00 709 710 /* Bit definitions for ALARM_HOURS_REG */ 711 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80 712 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 0x07 713 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30 714 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 0x04 715 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0F 716 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0x00 717 718 /* Bit definitions for ALARM_DAYS_REG */ 719 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30 720 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 0x04 721 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0F 722 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0x00 723 724 /* Bit definitions for ALARM_MONTHS_REG */ 725 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10 726 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 0x04 727 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0F 728 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0x00 729 730 /* Bit definitions for ALARM_YEARS_REG */ 731 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0 732 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 0x04 733 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0F 734 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0x00 735 736 /* Bit definitions for RTC_CTRL_REG */ 737 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80 738 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 0x07 739 #define PALMAS_RTC_CTRL_REG_GET_TIME 0x40 740 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 0x06 741 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20 742 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 0x05 743 #define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10 744 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 0x04 745 #define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08 746 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 0x03 747 #define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04 748 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 0x02 749 #define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02 750 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 0x01 751 #define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01 752 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0x00 753 754 /* Bit definitions for RTC_STATUS_REG */ 755 #define PALMAS_RTC_STATUS_REG_POWER_UP 0x80 756 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 0x07 757 #define PALMAS_RTC_STATUS_REG_ALARM 0x40 758 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 0x06 759 #define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20 760 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 0x05 761 #define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10 762 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 0x04 763 #define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08 764 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 0x03 765 #define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04 766 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 0x02 767 #define PALMAS_RTC_STATUS_REG_RUN 0x02 768 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT 0x01 769 770 /* Bit definitions for RTC_INTERRUPTS_REG */ 771 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10 772 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 0x04 773 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08 774 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 0x03 775 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04 776 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 0x02 777 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03 778 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0x00 779 780 /* Bit definitions for RTC_COMP_LSB_REG */ 781 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xFF 782 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0x00 783 784 /* Bit definitions for RTC_COMP_MSB_REG */ 785 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xFF 786 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0x00 787 788 /* Bit definitions for RTC_RES_PROG_REG */ 789 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3F 790 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0x00 791 792 /* Bit definitions for RTC_RESET_STATUS_REG */ 793 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01 794 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0x00 795 796 /* Registers for function BACKUP */ 797 #define PALMAS_BACKUP0 0x00 798 #define PALMAS_BACKUP1 0x01 799 #define PALMAS_BACKUP2 0x02 800 #define PALMAS_BACKUP3 0x03 801 #define PALMAS_BACKUP4 0x04 802 #define PALMAS_BACKUP5 0x05 803 #define PALMAS_BACKUP6 0x06 804 #define PALMAS_BACKUP7 0x07 805 806 /* Bit definitions for BACKUP0 */ 807 #define PALMAS_BACKUP0_BACKUP_MASK 0xFF 808 #define PALMAS_BACKUP0_BACKUP_SHIFT 0x00 809 810 /* Bit definitions for BACKUP1 */ 811 #define PALMAS_BACKUP1_BACKUP_MASK 0xFF 812 #define PALMAS_BACKUP1_BACKUP_SHIFT 0x00 813 814 /* Bit definitions for BACKUP2 */ 815 #define PALMAS_BACKUP2_BACKUP_MASK 0xFF 816 #define PALMAS_BACKUP2_BACKUP_SHIFT 0x00 817 818 /* Bit definitions for BACKUP3 */ 819 #define PALMAS_BACKUP3_BACKUP_MASK 0xFF 820 #define PALMAS_BACKUP3_BACKUP_SHIFT 0x00 821 822 /* Bit definitions for BACKUP4 */ 823 #define PALMAS_BACKUP4_BACKUP_MASK 0xFF 824 #define PALMAS_BACKUP4_BACKUP_SHIFT 0x00 825 826 /* Bit definitions for BACKUP5 */ 827 #define PALMAS_BACKUP5_BACKUP_MASK 0xFF 828 #define PALMAS_BACKUP5_BACKUP_SHIFT 0x00 829 830 /* Bit definitions for BACKUP6 */ 831 #define PALMAS_BACKUP6_BACKUP_MASK 0xFF 832 #define PALMAS_BACKUP6_BACKUP_SHIFT 0x00 833 834 /* Bit definitions for BACKUP7 */ 835 #define PALMAS_BACKUP7_BACKUP_MASK 0xFF 836 #define PALMAS_BACKUP7_BACKUP_SHIFT 0x00 837 838 /* Registers for function SMPS */ 839 #define PALMAS_SMPS12_CTRL 0x00 840 #define PALMAS_SMPS12_TSTEP 0x01 841 #define PALMAS_SMPS12_FORCE 0x02 842 #define PALMAS_SMPS12_VOLTAGE 0x03 843 #define PALMAS_SMPS3_CTRL 0x04 844 #define PALMAS_SMPS3_VOLTAGE 0x07 845 #define PALMAS_SMPS45_CTRL 0x08 846 #define PALMAS_SMPS45_TSTEP 0x09 847 #define PALMAS_SMPS45_FORCE 0x0A 848 #define PALMAS_SMPS45_VOLTAGE 0x0B 849 #define PALMAS_SMPS6_CTRL 0x0C 850 #define PALMAS_SMPS6_TSTEP 0x0D 851 #define PALMAS_SMPS6_FORCE 0x0E 852 #define PALMAS_SMPS6_VOLTAGE 0x0F 853 #define PALMAS_SMPS7_CTRL 0x10 854 #define PALMAS_SMPS7_VOLTAGE 0x13 855 #define PALMAS_SMPS8_CTRL 0x14 856 #define PALMAS_SMPS8_TSTEP 0x15 857 #define PALMAS_SMPS8_FORCE 0x16 858 #define PALMAS_SMPS8_VOLTAGE 0x17 859 #define PALMAS_SMPS9_CTRL 0x18 860 #define PALMAS_SMPS9_VOLTAGE 0x1B 861 #define PALMAS_SMPS10_CTRL 0x1C 862 #define PALMAS_SMPS10_STATUS 0x1F 863 #define PALMAS_SMPS_CTRL 0x24 864 #define PALMAS_SMPS_PD_CTRL 0x25 865 #define PALMAS_SMPS_DITHER_EN 0x26 866 #define PALMAS_SMPS_THERMAL_EN 0x27 867 #define PALMAS_SMPS_THERMAL_STATUS 0x28 868 #define PALMAS_SMPS_SHORT_STATUS 0x29 869 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A 870 #define PALMAS_SMPS_POWERGOOD_MASK1 0x2B 871 #define PALMAS_SMPS_POWERGOOD_MASK2 0x2C 872 873 /* Bit definitions for SMPS12_CTRL */ 874 #define PALMAS_SMPS12_CTRL_WR_S 0x80 875 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT 0x07 876 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40 877 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 878 #define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30 879 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT 0x04 880 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c 881 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 0x02 882 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03 883 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0x00 884 885 /* Bit definitions for SMPS12_TSTEP */ 886 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03 887 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0x00 888 889 /* Bit definitions for SMPS12_FORCE */ 890 #define PALMAS_SMPS12_FORCE_CMD 0x80 891 #define PALMAS_SMPS12_FORCE_CMD_SHIFT 0x07 892 #define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7F 893 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0x00 894 895 /* Bit definitions for SMPS12_VOLTAGE */ 896 #define PALMAS_SMPS12_VOLTAGE_RANGE 0x80 897 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 0x07 898 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7F 899 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0x00 900 901 /* Bit definitions for SMPS3_CTRL */ 902 #define PALMAS_SMPS3_CTRL_WR_S 0x80 903 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT 0x07 904 #define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30 905 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT 0x04 906 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c 907 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02 908 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 909 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00 910 911 /* Bit definitions for SMPS3_VOLTAGE */ 912 #define PALMAS_SMPS3_VOLTAGE_RANGE 0x80 913 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 0x07 914 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7F 915 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0x00 916 917 /* Bit definitions for SMPS45_CTRL */ 918 #define PALMAS_SMPS45_CTRL_WR_S 0x80 919 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT 0x07 920 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40 921 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 922 #define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30 923 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT 0x04 924 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c 925 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 0x02 926 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03 927 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0x00 928 929 /* Bit definitions for SMPS45_TSTEP */ 930 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03 931 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0x00 932 933 /* Bit definitions for SMPS45_FORCE */ 934 #define PALMAS_SMPS45_FORCE_CMD 0x80 935 #define PALMAS_SMPS45_FORCE_CMD_SHIFT 0x07 936 #define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7F 937 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0x00 938 939 /* Bit definitions for SMPS45_VOLTAGE */ 940 #define PALMAS_SMPS45_VOLTAGE_RANGE 0x80 941 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 0x07 942 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7F 943 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0x00 944 945 /* Bit definitions for SMPS6_CTRL */ 946 #define PALMAS_SMPS6_CTRL_WR_S 0x80 947 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT 0x07 948 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40 949 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 950 #define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30 951 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT 0x04 952 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c 953 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 0x02 954 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03 955 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0x00 956 957 /* Bit definitions for SMPS6_TSTEP */ 958 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03 959 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0x00 960 961 /* Bit definitions for SMPS6_FORCE */ 962 #define PALMAS_SMPS6_FORCE_CMD 0x80 963 #define PALMAS_SMPS6_FORCE_CMD_SHIFT 0x07 964 #define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7F 965 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0x00 966 967 /* Bit definitions for SMPS6_VOLTAGE */ 968 #define PALMAS_SMPS6_VOLTAGE_RANGE 0x80 969 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 0x07 970 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7F 971 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0x00 972 973 /* Bit definitions for SMPS7_CTRL */ 974 #define PALMAS_SMPS7_CTRL_WR_S 0x80 975 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT 0x07 976 #define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30 977 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT 0x04 978 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c 979 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 0x02 980 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03 981 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0x00 982 983 /* Bit definitions for SMPS7_VOLTAGE */ 984 #define PALMAS_SMPS7_VOLTAGE_RANGE 0x80 985 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 0x07 986 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7F 987 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0x00 988 989 /* Bit definitions for SMPS8_CTRL */ 990 #define PALMAS_SMPS8_CTRL_WR_S 0x80 991 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT 0x07 992 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40 993 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 994 #define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30 995 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT 0x04 996 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c 997 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 0x02 998 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03 999 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0x00 1000 1001 /* Bit definitions for SMPS8_TSTEP */ 1002 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03 1003 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0x00 1004 1005 /* Bit definitions for SMPS8_FORCE */ 1006 #define PALMAS_SMPS8_FORCE_CMD 0x80 1007 #define PALMAS_SMPS8_FORCE_CMD_SHIFT 0x07 1008 #define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7F 1009 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0x00 1010 1011 /* Bit definitions for SMPS8_VOLTAGE */ 1012 #define PALMAS_SMPS8_VOLTAGE_RANGE 0x80 1013 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 0x07 1014 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7F 1015 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0x00 1016 1017 /* Bit definitions for SMPS9_CTRL */ 1018 #define PALMAS_SMPS9_CTRL_WR_S 0x80 1019 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT 0x07 1020 #define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30 1021 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT 0x04 1022 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c 1023 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 0x02 1024 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03 1025 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0x00 1026 1027 /* Bit definitions for SMPS9_VOLTAGE */ 1028 #define PALMAS_SMPS9_VOLTAGE_RANGE 0x80 1029 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 0x07 1030 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7F 1031 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0x00 1032 1033 /* Bit definitions for SMPS10_CTRL */ 1034 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0 1035 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 0x04 1036 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0F 1037 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0x00 1038 1039 /* Bit definitions for SMPS10_STATUS */ 1040 #define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0F 1041 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0x00 1042 1043 /* Bit definitions for SMPS_CTRL */ 1044 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20 1045 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 0x05 1046 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10 1047 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 0x04 1048 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c 1049 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 0x02 1050 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03 1051 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0x00 1052 1053 /* Bit definitions for SMPS_PD_CTRL */ 1054 #define PALMAS_SMPS_PD_CTRL_SMPS9 0x40 1055 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 0x06 1056 #define PALMAS_SMPS_PD_CTRL_SMPS8 0x20 1057 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 0x05 1058 #define PALMAS_SMPS_PD_CTRL_SMPS7 0x10 1059 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 0x04 1060 #define PALMAS_SMPS_PD_CTRL_SMPS6 0x08 1061 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 0x03 1062 #define PALMAS_SMPS_PD_CTRL_SMPS45 0x04 1063 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 0x02 1064 #define PALMAS_SMPS_PD_CTRL_SMPS3 0x02 1065 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 0x01 1066 #define PALMAS_SMPS_PD_CTRL_SMPS12 0x01 1067 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0x00 1068 1069 /* Bit definitions for SMPS_THERMAL_EN */ 1070 #define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40 1071 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 0x06 1072 #define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20 1073 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 0x05 1074 #define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08 1075 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 0x03 1076 #define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04 1077 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 0x02 1078 #define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01 1079 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0x00 1080 1081 /* Bit definitions for SMPS_THERMAL_STATUS */ 1082 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40 1083 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 0x06 1084 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20 1085 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 0x05 1086 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08 1087 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 0x03 1088 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04 1089 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 0x02 1090 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01 1091 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0x00 1092 1093 /* Bit definitions for SMPS_SHORT_STATUS */ 1094 #define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80 1095 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 0x07 1096 #define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40 1097 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 0x06 1098 #define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20 1099 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 0x05 1100 #define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10 1101 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 0x04 1102 #define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08 1103 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 0x03 1104 #define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04 1105 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 0x02 1106 #define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02 1107 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x01 1108 #define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01 1109 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0x00 1110 1111 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ 1112 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40 1113 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 0x06 1114 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20 1115 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 0x05 1116 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10 1117 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 0x04 1118 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08 1119 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 0x03 1120 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04 1121 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 0x02 1122 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02 1123 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x01 1124 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01 1125 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0x00 1126 1127 /* Bit definitions for SMPS_POWERGOOD_MASK1 */ 1128 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80 1129 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 0x07 1130 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40 1131 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 0x06 1132 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20 1133 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 0x05 1134 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10 1135 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 0x04 1136 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08 1137 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 0x03 1138 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04 1139 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 0x02 1140 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02 1141 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x01 1142 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01 1143 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0x00 1144 1145 /* Bit definitions for SMPS_POWERGOOD_MASK2 */ 1146 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 1147 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07 1148 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04 1149 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 0x02 1150 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02 1151 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 0x01 1152 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01 1153 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0x00 1154 1155 /* Registers for function LDO */ 1156 #define PALMAS_LDO1_CTRL 0x00 1157 #define PALMAS_LDO1_VOLTAGE 0x01 1158 #define PALMAS_LDO2_CTRL 0x02 1159 #define PALMAS_LDO2_VOLTAGE 0x03 1160 #define PALMAS_LDO3_CTRL 0x04 1161 #define PALMAS_LDO3_VOLTAGE 0x05 1162 #define PALMAS_LDO4_CTRL 0x06 1163 #define PALMAS_LDO4_VOLTAGE 0x07 1164 #define PALMAS_LDO5_CTRL 0x08 1165 #define PALMAS_LDO5_VOLTAGE 0x09 1166 #define PALMAS_LDO6_CTRL 0x0A 1167 #define PALMAS_LDO6_VOLTAGE 0x0B 1168 #define PALMAS_LDO7_CTRL 0x0C 1169 #define PALMAS_LDO7_VOLTAGE 0x0D 1170 #define PALMAS_LDO8_CTRL 0x0E 1171 #define PALMAS_LDO8_VOLTAGE 0x0F 1172 #define PALMAS_LDO9_CTRL 0x10 1173 #define PALMAS_LDO9_VOLTAGE 0x11 1174 #define PALMAS_LDOLN_CTRL 0x12 1175 #define PALMAS_LDOLN_VOLTAGE 0x13 1176 #define PALMAS_LDOUSB_CTRL 0x14 1177 #define PALMAS_LDOUSB_VOLTAGE 0x15 1178 #define PALMAS_LDO_CTRL 0x1A 1179 #define PALMAS_LDO_PD_CTRL1 0x1B 1180 #define PALMAS_LDO_PD_CTRL2 0x1C 1181 #define PALMAS_LDO_SHORT_STATUS1 0x1D 1182 #define PALMAS_LDO_SHORT_STATUS2 0x1E 1183 1184 /* Bit definitions for LDO1_CTRL */ 1185 #define PALMAS_LDO1_CTRL_WR_S 0x80 1186 #define PALMAS_LDO1_CTRL_WR_S_SHIFT 0x07 1187 #define PALMAS_LDO1_CTRL_STATUS 0x10 1188 #define PALMAS_LDO1_CTRL_STATUS_SHIFT 0x04 1189 #define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04 1190 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02 1191 #define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01 1192 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00 1193 1194 /* Bit definitions for LDO1_VOLTAGE */ 1195 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3F 1196 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0x00 1197 1198 /* Bit definitions for LDO2_CTRL */ 1199 #define PALMAS_LDO2_CTRL_WR_S 0x80 1200 #define PALMAS_LDO2_CTRL_WR_S_SHIFT 0x07 1201 #define PALMAS_LDO2_CTRL_STATUS 0x10 1202 #define PALMAS_LDO2_CTRL_STATUS_SHIFT 0x04 1203 #define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04 1204 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02 1205 #define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01 1206 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00 1207 1208 /* Bit definitions for LDO2_VOLTAGE */ 1209 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3F 1210 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0x00 1211 1212 /* Bit definitions for LDO3_CTRL */ 1213 #define PALMAS_LDO3_CTRL_WR_S 0x80 1214 #define PALMAS_LDO3_CTRL_WR_S_SHIFT 0x07 1215 #define PALMAS_LDO3_CTRL_STATUS 0x10 1216 #define PALMAS_LDO3_CTRL_STATUS_SHIFT 0x04 1217 #define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04 1218 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02 1219 #define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01 1220 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00 1221 1222 /* Bit definitions for LDO3_VOLTAGE */ 1223 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3F 1224 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0x00 1225 1226 /* Bit definitions for LDO4_CTRL */ 1227 #define PALMAS_LDO4_CTRL_WR_S 0x80 1228 #define PALMAS_LDO4_CTRL_WR_S_SHIFT 0x07 1229 #define PALMAS_LDO4_CTRL_STATUS 0x10 1230 #define PALMAS_LDO4_CTRL_STATUS_SHIFT 0x04 1231 #define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04 1232 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02 1233 #define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01 1234 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00 1235 1236 /* Bit definitions for LDO4_VOLTAGE */ 1237 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3F 1238 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0x00 1239 1240 /* Bit definitions for LDO5_CTRL */ 1241 #define PALMAS_LDO5_CTRL_WR_S 0x80 1242 #define PALMAS_LDO5_CTRL_WR_S_SHIFT 0x07 1243 #define PALMAS_LDO5_CTRL_STATUS 0x10 1244 #define PALMAS_LDO5_CTRL_STATUS_SHIFT 0x04 1245 #define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04 1246 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02 1247 #define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01 1248 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00 1249 1250 /* Bit definitions for LDO5_VOLTAGE */ 1251 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3F 1252 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0x00 1253 1254 /* Bit definitions for LDO6_CTRL */ 1255 #define PALMAS_LDO6_CTRL_WR_S 0x80 1256 #define PALMAS_LDO6_CTRL_WR_S_SHIFT 0x07 1257 #define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40 1258 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 0x06 1259 #define PALMAS_LDO6_CTRL_STATUS 0x10 1260 #define PALMAS_LDO6_CTRL_STATUS_SHIFT 0x04 1261 #define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04 1262 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 0x02 1263 #define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01 1264 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0x00 1265 1266 /* Bit definitions for LDO6_VOLTAGE */ 1267 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3F 1268 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0x00 1269 1270 /* Bit definitions for LDO7_CTRL */ 1271 #define PALMAS_LDO7_CTRL_WR_S 0x80 1272 #define PALMAS_LDO7_CTRL_WR_S_SHIFT 0x07 1273 #define PALMAS_LDO7_CTRL_STATUS 0x10 1274 #define PALMAS_LDO7_CTRL_STATUS_SHIFT 0x04 1275 #define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04 1276 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 0x02 1277 #define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01 1278 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0x00 1279 1280 /* Bit definitions for LDO7_VOLTAGE */ 1281 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3F 1282 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0x00 1283 1284 /* Bit definitions for LDO8_CTRL */ 1285 #define PALMAS_LDO8_CTRL_WR_S 0x80 1286 #define PALMAS_LDO8_CTRL_WR_S_SHIFT 0x07 1287 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40 1288 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 0x06 1289 #define PALMAS_LDO8_CTRL_STATUS 0x10 1290 #define PALMAS_LDO8_CTRL_STATUS_SHIFT 0x04 1291 #define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04 1292 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 0x02 1293 #define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01 1294 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0x00 1295 1296 /* Bit definitions for LDO8_VOLTAGE */ 1297 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3F 1298 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0x00 1299 1300 /* Bit definitions for LDO9_CTRL */ 1301 #define PALMAS_LDO9_CTRL_WR_S 0x80 1302 #define PALMAS_LDO9_CTRL_WR_S_SHIFT 0x07 1303 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40 1304 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 0x06 1305 #define PALMAS_LDO9_CTRL_STATUS 0x10 1306 #define PALMAS_LDO9_CTRL_STATUS_SHIFT 0x04 1307 #define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04 1308 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 0x02 1309 #define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01 1310 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0x00 1311 1312 /* Bit definitions for LDO9_VOLTAGE */ 1313 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3F 1314 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0x00 1315 1316 /* Bit definitions for LDOLN_CTRL */ 1317 #define PALMAS_LDOLN_CTRL_WR_S 0x80 1318 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT 0x07 1319 #define PALMAS_LDOLN_CTRL_STATUS 0x10 1320 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT 0x04 1321 #define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04 1322 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 0x02 1323 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01 1324 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0x00 1325 1326 /* Bit definitions for LDOLN_VOLTAGE */ 1327 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3F 1328 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0x00 1329 1330 /* Bit definitions for LDOUSB_CTRL */ 1331 #define PALMAS_LDOUSB_CTRL_WR_S 0x80 1332 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 0x07 1333 #define PALMAS_LDOUSB_CTRL_STATUS 0x10 1334 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 0x04 1335 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04 1336 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 0x02 1337 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01 1338 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0x00 1339 1340 /* Bit definitions for LDOUSB_VOLTAGE */ 1341 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3F 1342 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0x00 1343 1344 /* Bit definitions for LDO_CTRL */ 1345 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01 1346 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0x00 1347 1348 /* Bit definitions for LDO_PD_CTRL1 */ 1349 #define PALMAS_LDO_PD_CTRL1_LDO8 0x80 1350 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 0x07 1351 #define PALMAS_LDO_PD_CTRL1_LDO7 0x40 1352 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 0x06 1353 #define PALMAS_LDO_PD_CTRL1_LDO6 0x20 1354 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 0x05 1355 #define PALMAS_LDO_PD_CTRL1_LDO5 0x10 1356 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 0x04 1357 #define PALMAS_LDO_PD_CTRL1_LDO4 0x08 1358 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 0x03 1359 #define PALMAS_LDO_PD_CTRL1_LDO3 0x04 1360 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 0x02 1361 #define PALMAS_LDO_PD_CTRL1_LDO2 0x02 1362 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 0x01 1363 #define PALMAS_LDO_PD_CTRL1_LDO1 0x01 1364 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0x00 1365 1366 /* Bit definitions for LDO_PD_CTRL2 */ 1367 #define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04 1368 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 0x02 1369 #define PALMAS_LDO_PD_CTRL2_LDOLN 0x02 1370 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 0x01 1371 #define PALMAS_LDO_PD_CTRL2_LDO9 0x01 1372 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0x00 1373 1374 /* Bit definitions for LDO_SHORT_STATUS1 */ 1375 #define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80 1376 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 0x07 1377 #define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40 1378 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 0x06 1379 #define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20 1380 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 0x05 1381 #define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10 1382 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 0x04 1383 #define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08 1384 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 0x03 1385 #define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04 1386 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 0x02 1387 #define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02 1388 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01 1389 #define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01 1390 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00 1391 1392 /* Bit definitions for LDO_SHORT_STATUS2 */ 1393 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08 1394 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x03 1395 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04 1396 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 0x02 1397 #define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02 1398 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 0x01 1399 #define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01 1400 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0x00 1401 1402 /* Registers for function PMU_CONTROL */ 1403 #define PALMAS_DEV_CTRL 0x00 1404 #define PALMAS_POWER_CTRL 0x01 1405 #define PALMAS_VSYS_LO 0x02 1406 #define PALMAS_VSYS_MON 0x03 1407 #define PALMAS_VBAT_MON 0x04 1408 #define PALMAS_WATCHDOG 0x05 1409 #define PALMAS_BOOT_STATUS 0x06 1410 #define PALMAS_BATTERY_BOUNCE 0x07 1411 #define PALMAS_BACKUP_BATTERY_CTRL 0x08 1412 #define PALMAS_LONG_PRESS_KEY 0x09 1413 #define PALMAS_OSC_THERM_CTRL 0x0A 1414 #define PALMAS_BATDEBOUNCING 0x0B 1415 #define PALMAS_SWOFF_HWRST 0x0F 1416 #define PALMAS_SWOFF_COLDRST 0x10 1417 #define PALMAS_SWOFF_STATUS 0x11 1418 #define PALMAS_PMU_CONFIG 0x12 1419 #define PALMAS_SPARE 0x14 1420 #define PALMAS_PMU_SECONDARY_INT 0x15 1421 #define PALMAS_SW_REVISION 0x17 1422 #define PALMAS_EXT_CHRG_CTRL 0x18 1423 #define PALMAS_PMU_SECONDARY_INT2 0x19 1424 1425 /* Bit definitions for DEV_CTRL */ 1426 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c 1427 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 0x02 1428 #define PALMAS_DEV_CTRL_SW_RST 0x02 1429 #define PALMAS_DEV_CTRL_SW_RST_SHIFT 0x01 1430 #define PALMAS_DEV_CTRL_DEV_ON 0x01 1431 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0x00 1432 1433 /* Bit definitions for POWER_CTRL */ 1434 #define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04 1435 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 0x02 1436 #define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02 1437 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 0x01 1438 #define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01 1439 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0x00 1440 1441 /* Bit definitions for VSYS_LO */ 1442 #define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1F 1443 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0x00 1444 1445 /* Bit definitions for VSYS_MON */ 1446 #define PALMAS_VSYS_MON_ENABLE 0x80 1447 #define PALMAS_VSYS_MON_ENABLE_SHIFT 0x07 1448 #define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3F 1449 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0x00 1450 1451 /* Bit definitions for VBAT_MON */ 1452 #define PALMAS_VBAT_MON_ENABLE 0x80 1453 #define PALMAS_VBAT_MON_ENABLE_SHIFT 0x07 1454 #define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3F 1455 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0x00 1456 1457 /* Bit definitions for WATCHDOG */ 1458 #define PALMAS_WATCHDOG_LOCK 0x20 1459 #define PALMAS_WATCHDOG_LOCK_SHIFT 0x05 1460 #define PALMAS_WATCHDOG_ENABLE 0x10 1461 #define PALMAS_WATCHDOG_ENABLE_SHIFT 0x04 1462 #define PALMAS_WATCHDOG_MODE 0x08 1463 #define PALMAS_WATCHDOG_MODE_SHIFT 0x03 1464 #define PALMAS_WATCHDOG_TIMER_MASK 0x07 1465 #define PALMAS_WATCHDOG_TIMER_SHIFT 0x00 1466 1467 /* Bit definitions for BOOT_STATUS */ 1468 #define PALMAS_BOOT_STATUS_BOOT1 0x02 1469 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT 0x01 1470 #define PALMAS_BOOT_STATUS_BOOT0 0x01 1471 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0x00 1472 1473 /* Bit definitions for BATTERY_BOUNCE */ 1474 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3F 1475 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0x00 1476 1477 /* Bit definitions for BACKUP_BATTERY_CTRL */ 1478 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80 1479 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 0x07 1480 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40 1481 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 0x06 1482 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20 1483 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 0x05 1484 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10 1485 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 0x04 1486 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08 1487 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 0x03 1488 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06 1489 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 0x01 1490 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01 1491 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0x00 1492 1493 /* Bit definitions for LONG_PRESS_KEY */ 1494 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80 1495 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 0x07 1496 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10 1497 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 0x04 1498 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c 1499 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 0x02 1500 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03 1501 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0x00 1502 1503 /* Bit definitions for OSC_THERM_CTRL */ 1504 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80 1505 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 0x07 1506 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40 1507 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 0x06 1508 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20 1509 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 0x05 1510 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10 1511 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 0x04 1512 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c 1513 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 0x02 1514 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02 1515 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 0x01 1516 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01 1517 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0x00 1518 1519 /* Bit definitions for BATDEBOUNCING */ 1520 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80 1521 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 0x07 1522 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78 1523 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 0x03 1524 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07 1525 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0x00 1526 1527 /* Bit definitions for SWOFF_HWRST */ 1528 #define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80 1529 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 0x07 1530 #define PALMAS_SWOFF_HWRST_PWRDOWN 0x40 1531 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 0x06 1532 #define PALMAS_SWOFF_HWRST_WTD 0x20 1533 #define PALMAS_SWOFF_HWRST_WTD_SHIFT 0x05 1534 #define PALMAS_SWOFF_HWRST_TSHUT 0x10 1535 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 0x04 1536 #define PALMAS_SWOFF_HWRST_RESET_IN 0x08 1537 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 0x03 1538 #define PALMAS_SWOFF_HWRST_SW_RST 0x04 1539 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 0x02 1540 #define PALMAS_SWOFF_HWRST_VSYS_LO 0x02 1541 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 0x01 1542 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01 1543 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0x00 1544 1545 /* Bit definitions for SWOFF_COLDRST */ 1546 #define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80 1547 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 0x07 1548 #define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40 1549 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 0x06 1550 #define PALMAS_SWOFF_COLDRST_WTD 0x20 1551 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT 0x05 1552 #define PALMAS_SWOFF_COLDRST_TSHUT 0x10 1553 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 0x04 1554 #define PALMAS_SWOFF_COLDRST_RESET_IN 0x08 1555 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 0x03 1556 #define PALMAS_SWOFF_COLDRST_SW_RST 0x04 1557 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 0x02 1558 #define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02 1559 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 0x01 1560 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01 1561 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0x00 1562 1563 /* Bit definitions for SWOFF_STATUS */ 1564 #define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80 1565 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 0x07 1566 #define PALMAS_SWOFF_STATUS_PWRDOWN 0x40 1567 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 0x06 1568 #define PALMAS_SWOFF_STATUS_WTD 0x20 1569 #define PALMAS_SWOFF_STATUS_WTD_SHIFT 0x05 1570 #define PALMAS_SWOFF_STATUS_TSHUT 0x10 1571 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 0x04 1572 #define PALMAS_SWOFF_STATUS_RESET_IN 0x08 1573 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 0x03 1574 #define PALMAS_SWOFF_STATUS_SW_RST 0x04 1575 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 0x02 1576 #define PALMAS_SWOFF_STATUS_VSYS_LO 0x02 1577 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 0x01 1578 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01 1579 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0x00 1580 1581 /* Bit definitions for PMU_CONFIG */ 1582 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40 1583 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 0x06 1584 #define PALMAS_PMU_CONFIG_SPARE_MASK 0x30 1585 #define PALMAS_PMU_CONFIG_SPARE_SHIFT 0x04 1586 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c 1587 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 0x02 1588 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02 1589 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 0x01 1590 #define PALMAS_PMU_CONFIG_AUTODEVON 0x01 1591 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0x00 1592 1593 /* Bit definitions for SPARE */ 1594 #define PALMAS_SPARE_SPARE_MASK 0xf8 1595 #define PALMAS_SPARE_SPARE_SHIFT 0x03 1596 #define PALMAS_SPARE_REGEN3_OD 0x04 1597 #define PALMAS_SPARE_REGEN3_OD_SHIFT 0x02 1598 #define PALMAS_SPARE_REGEN2_OD 0x02 1599 #define PALMAS_SPARE_REGEN2_OD_SHIFT 0x01 1600 #define PALMAS_SPARE_REGEN1_OD 0x01 1601 #define PALMAS_SPARE_REGEN1_OD_SHIFT 0x00 1602 1603 /* Bit definitions for PMU_SECONDARY_INT */ 1604 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80 1605 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 0x07 1606 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40 1607 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 0x06 1608 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20 1609 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 0x05 1610 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10 1611 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 0x04 1612 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08 1613 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 0x03 1614 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04 1615 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 0x02 1616 #define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02 1617 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 0x01 1618 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01 1619 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0x00 1620 1621 /* Bit definitions for SW_REVISION */ 1622 #define PALMAS_SW_REVISION_SW_REVISION_MASK 0xFF 1623 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0x00 1624 1625 /* Bit definitions for EXT_CHRG_CTRL */ 1626 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80 1627 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 0x07 1628 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40 1629 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 0x06 1630 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08 1631 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 0x03 1632 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04 1633 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 0x02 1634 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02 1635 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 0x01 1636 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01 1637 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0x00 1638 1639 /* Bit definitions for PMU_SECONDARY_INT2 */ 1640 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20 1641 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 0x05 1642 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10 1643 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 0x04 1644 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02 1645 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 0x01 1646 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01 1647 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0x00 1648 1649 /* Registers for function RESOURCE */ 1650 #define PALMAS_CLK32KG_CTRL 0x00 1651 #define PALMAS_CLK32KGAUDIO_CTRL 0x01 1652 #define PALMAS_REGEN1_CTRL 0x02 1653 #define PALMAS_REGEN2_CTRL 0x03 1654 #define PALMAS_SYSEN1_CTRL 0x04 1655 #define PALMAS_SYSEN2_CTRL 0x05 1656 #define PALMAS_NSLEEP_RES_ASSIGN 0x06 1657 #define PALMAS_NSLEEP_SMPS_ASSIGN 0x07 1658 #define PALMAS_NSLEEP_LDO_ASSIGN1 0x08 1659 #define PALMAS_NSLEEP_LDO_ASSIGN2 0x09 1660 #define PALMAS_ENABLE1_RES_ASSIGN 0x0A 1661 #define PALMAS_ENABLE1_SMPS_ASSIGN 0x0B 1662 #define PALMAS_ENABLE1_LDO_ASSIGN1 0x0C 1663 #define PALMAS_ENABLE1_LDO_ASSIGN2 0x0D 1664 #define PALMAS_ENABLE2_RES_ASSIGN 0x0E 1665 #define PALMAS_ENABLE2_SMPS_ASSIGN 0x0F 1666 #define PALMAS_ENABLE2_LDO_ASSIGN1 0x10 1667 #define PALMAS_ENABLE2_LDO_ASSIGN2 0x11 1668 #define PALMAS_REGEN3_CTRL 0x12 1669 1670 /* Bit definitions for CLK32KG_CTRL */ 1671 #define PALMAS_CLK32KG_CTRL_STATUS 0x10 1672 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 0x04 1673 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04 1674 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 0x02 1675 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01 1676 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0x00 1677 1678 /* Bit definitions for CLK32KGAUDIO_CTRL */ 1679 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10 1680 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 0x04 1681 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08 1682 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 0x03 1683 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04 1684 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 0x02 1685 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01 1686 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0x00 1687 1688 /* Bit definitions for REGEN1_CTRL */ 1689 #define PALMAS_REGEN1_CTRL_STATUS 0x10 1690 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT 0x04 1691 #define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04 1692 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02 1693 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01 1694 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 1695 1696 /* Bit definitions for REGEN2_CTRL */ 1697 #define PALMAS_REGEN2_CTRL_STATUS 0x10 1698 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT 0x04 1699 #define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04 1700 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02 1701 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01 1702 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 1703 1704 /* Bit definitions for SYSEN1_CTRL */ 1705 #define PALMAS_SYSEN1_CTRL_STATUS 0x10 1706 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 0x04 1707 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04 1708 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 0x02 1709 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01 1710 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 1711 1712 /* Bit definitions for SYSEN2_CTRL */ 1713 #define PALMAS_SYSEN2_CTRL_STATUS 0x10 1714 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 0x04 1715 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04 1716 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 0x02 1717 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01 1718 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 1719 1720 /* Bit definitions for NSLEEP_RES_ASSIGN */ 1721 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40 1722 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x06 1723 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20 1724 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05 1725 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10 1726 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 0x04 1727 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08 1728 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 0x03 1729 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04 1730 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 0x02 1731 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02 1732 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01 1733 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01 1734 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00 1735 1736 /* Bit definitions for NSLEEP_SMPS_ASSIGN */ 1737 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80 1738 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 0x07 1739 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40 1740 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 0x06 1741 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20 1742 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 0x05 1743 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10 1744 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 0x04 1745 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08 1746 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 0x03 1747 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04 1748 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 0x02 1749 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02 1750 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x01 1751 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01 1752 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0x00 1753 1754 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */ 1755 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80 1756 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 0x07 1757 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40 1758 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 0x06 1759 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20 1760 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 0x05 1761 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10 1762 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 0x04 1763 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08 1764 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x03 1765 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04 1766 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 0x02 1767 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02 1768 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01 1769 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01 1770 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00 1771 1772 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */ 1773 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04 1774 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 0x02 1775 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02 1776 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 0x01 1777 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01 1778 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0x00 1779 1780 /* Bit definitions for ENABLE1_RES_ASSIGN */ 1781 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40 1782 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x06 1783 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20 1784 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05 1785 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10 1786 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 0x04 1787 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08 1788 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 0x03 1789 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04 1790 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 0x02 1791 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02 1792 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01 1793 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01 1794 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00 1795 1796 /* Bit definitions for ENABLE1_SMPS_ASSIGN */ 1797 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80 1798 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 0x07 1799 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40 1800 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 0x06 1801 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20 1802 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 0x05 1803 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10 1804 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 0x04 1805 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08 1806 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 0x03 1807 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04 1808 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 0x02 1809 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02 1810 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x01 1811 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01 1812 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0x00 1813 1814 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */ 1815 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80 1816 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 0x07 1817 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40 1818 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 0x06 1819 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20 1820 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 0x05 1821 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10 1822 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 0x04 1823 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08 1824 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x03 1825 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04 1826 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 0x02 1827 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02 1828 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01 1829 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01 1830 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00 1831 1832 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */ 1833 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04 1834 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 0x02 1835 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02 1836 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 0x01 1837 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01 1838 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0x00 1839 1840 /* Bit definitions for ENABLE2_RES_ASSIGN */ 1841 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40 1842 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x06 1843 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20 1844 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05 1845 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10 1846 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 0x04 1847 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08 1848 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 0x03 1849 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04 1850 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 0x02 1851 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02 1852 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01 1853 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01 1854 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00 1855 1856 /* Bit definitions for ENABLE2_SMPS_ASSIGN */ 1857 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80 1858 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 0x07 1859 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40 1860 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 0x06 1861 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20 1862 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 0x05 1863 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10 1864 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 0x04 1865 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08 1866 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 0x03 1867 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04 1868 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 0x02 1869 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02 1870 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x01 1871 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01 1872 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0x00 1873 1874 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */ 1875 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80 1876 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 0x07 1877 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40 1878 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 0x06 1879 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20 1880 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 0x05 1881 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10 1882 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 0x04 1883 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08 1884 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x03 1885 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04 1886 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 0x02 1887 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02 1888 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01 1889 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01 1890 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00 1891 1892 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */ 1893 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04 1894 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 0x02 1895 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02 1896 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 0x01 1897 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01 1898 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0x00 1899 1900 /* Bit definitions for REGEN3_CTRL */ 1901 #define PALMAS_REGEN3_CTRL_STATUS 0x10 1902 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT 0x04 1903 #define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04 1904 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02 1905 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01 1906 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00 1907 1908 /* Registers for function PAD_CONTROL */ 1909 #define PALMAS_OD_OUTPUT_CTRL2 0x02 1910 #define PALMAS_POLARITY_CTRL2 0x03 1911 #define PALMAS_PU_PD_INPUT_CTRL1 0x04 1912 #define PALMAS_PU_PD_INPUT_CTRL2 0x05 1913 #define PALMAS_PU_PD_INPUT_CTRL3 0x06 1914 #define PALMAS_PU_PD_INPUT_CTRL5 0x07 1915 #define PALMAS_OD_OUTPUT_CTRL 0x08 1916 #define PALMAS_POLARITY_CTRL 0x09 1917 #define PALMAS_PRIMARY_SECONDARY_PAD1 0x0A 1918 #define PALMAS_PRIMARY_SECONDARY_PAD2 0x0B 1919 #define PALMAS_I2C_SPI 0x0C 1920 #define PALMAS_PU_PD_INPUT_CTRL4 0x0D 1921 #define PALMAS_PRIMARY_SECONDARY_PAD3 0x0E 1922 #define PALMAS_PRIMARY_SECONDARY_PAD4 0x0F 1923 1924 /* Bit definitions for PU_PD_INPUT_CTRL1 */ 1925 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40 1926 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 0x06 1927 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20 1928 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 0x05 1929 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10 1930 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 0x04 1931 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04 1932 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 0x02 1933 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02 1934 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 0x01 1935 1936 /* Bit definitions for PU_PD_INPUT_CTRL2 */ 1937 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20 1938 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 0x05 1939 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10 1940 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 0x04 1941 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08 1942 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 0x03 1943 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04 1944 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 0x02 1945 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02 1946 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 0x01 1947 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01 1948 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0x00 1949 1950 /* Bit definitions for PU_PD_INPUT_CTRL3 */ 1951 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40 1952 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 0x06 1953 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10 1954 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 0x04 1955 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04 1956 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 0x02 1957 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01 1958 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0x00 1959 1960 /* Bit definitions for OD_OUTPUT_CTRL */ 1961 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80 1962 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 0x07 1963 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40 1964 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 0x06 1965 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20 1966 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 0x05 1967 #define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08 1968 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 0x03 1969 1970 /* Bit definitions for POLARITY_CTRL */ 1971 #define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80 1972 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 0x07 1973 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40 1974 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 0x06 1975 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20 1976 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 0x05 1977 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10 1978 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 0x04 1979 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08 1980 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 0x03 1981 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04 1982 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 0x02 1983 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02 1984 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 0x01 1985 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01 1986 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0x00 1987 1988 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */ 1989 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80 1990 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 0x07 1991 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60 1992 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 0x05 1993 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18 1994 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 0x03 1995 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04 1996 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 0x02 1997 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02 1998 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 0x01 1999 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01 2000 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0x00 2001 2002 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */ 2003 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30 2004 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 0x04 2005 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08 2006 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 0x03 2007 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06 2008 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 0x01 2009 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01 2010 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0x00 2011 2012 /* Bit definitions for I2C_SPI */ 2013 #define PALMAS_I2C_SPI_I2C2OTP_EN 0x80 2014 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 0x07 2015 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40 2016 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 0x06 2017 #define PALMAS_I2C_SPI_ID_I2C2 0x20 2018 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT 0x05 2019 #define PALMAS_I2C_SPI_I2C_SPI 0x10 2020 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT 0x04 2021 #define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0F 2022 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0x00 2023 2024 /* Bit definitions for PU_PD_INPUT_CTRL4 */ 2025 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40 2026 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 0x06 2027 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10 2028 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 0x04 2029 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04 2030 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 0x02 2031 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01 2032 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0x00 2033 2034 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */ 2035 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02 2036 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 0x01 2037 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01 2038 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0x00 2039 2040 /* Registers for function LED_PWM */ 2041 #define PALMAS_LED_PERIOD_CTRL 0x00 2042 #define PALMAS_LED_CTRL 0x01 2043 #define PALMAS_PWM_CTRL1 0x02 2044 #define PALMAS_PWM_CTRL2 0x03 2045 2046 /* Bit definitions for LED_PERIOD_CTRL */ 2047 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38 2048 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 0x03 2049 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07 2050 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0x00 2051 2052 /* Bit definitions for LED_CTRL */ 2053 #define PALMAS_LED_CTRL_LED_2_SEQ 0x20 2054 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 0x05 2055 #define PALMAS_LED_CTRL_LED_1_SEQ 0x10 2056 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 0x04 2057 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c 2058 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 0x02 2059 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03 2060 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0x00 2061 2062 /* Bit definitions for PWM_CTRL1 */ 2063 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02 2064 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 0x01 2065 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01 2066 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0x00 2067 2068 /* Bit definitions for PWM_CTRL2 */ 2069 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xFF 2070 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0x00 2071 2072 /* Registers for function INTERRUPT */ 2073 #define PALMAS_INT1_STATUS 0x00 2074 #define PALMAS_INT1_MASK 0x01 2075 #define PALMAS_INT1_LINE_STATE 0x02 2076 #define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x03 2077 #define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x04 2078 #define PALMAS_INT2_STATUS 0x05 2079 #define PALMAS_INT2_MASK 0x06 2080 #define PALMAS_INT2_LINE_STATE 0x07 2081 #define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x08 2082 #define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x09 2083 #define PALMAS_INT3_STATUS 0x0A 2084 #define PALMAS_INT3_MASK 0x0B 2085 #define PALMAS_INT3_LINE_STATE 0x0C 2086 #define PALMAS_INT3_EDGE_DETECT1_RESERVED 0x0D 2087 #define PALMAS_INT3_EDGE_DETECT2_RESERVED 0x0E 2088 #define PALMAS_INT4_STATUS 0x0F 2089 #define PALMAS_INT4_MASK 0x10 2090 #define PALMAS_INT4_LINE_STATE 0x11 2091 #define PALMAS_INT4_EDGE_DETECT1 0x12 2092 #define PALMAS_INT4_EDGE_DETECT2 0x13 2093 #define PALMAS_INT_CTRL 0x14 2094 2095 /* Bit definitions for INT1_STATUS */ 2096 #define PALMAS_INT1_STATUS_VBAT_MON 0x80 2097 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 0x07 2098 #define PALMAS_INT1_STATUS_VSYS_MON 0x40 2099 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 0x06 2100 #define PALMAS_INT1_STATUS_HOTDIE 0x20 2101 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT 0x05 2102 #define PALMAS_INT1_STATUS_PWRDOWN 0x10 2103 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 0x04 2104 #define PALMAS_INT1_STATUS_RPWRON 0x08 2105 #define PALMAS_INT1_STATUS_RPWRON_SHIFT 0x03 2106 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04 2107 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02 2108 #define PALMAS_INT1_STATUS_PWRON 0x02 2109 #define PALMAS_INT1_STATUS_PWRON_SHIFT 0x01 2110 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01 2111 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0x00 2112 2113 /* Bit definitions for INT1_MASK */ 2114 #define PALMAS_INT1_MASK_VBAT_MON 0x80 2115 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT 0x07 2116 #define PALMAS_INT1_MASK_VSYS_MON 0x40 2117 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT 0x06 2118 #define PALMAS_INT1_MASK_HOTDIE 0x20 2119 #define PALMAS_INT1_MASK_HOTDIE_SHIFT 0x05 2120 #define PALMAS_INT1_MASK_PWRDOWN 0x10 2121 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT 0x04 2122 #define PALMAS_INT1_MASK_RPWRON 0x08 2123 #define PALMAS_INT1_MASK_RPWRON_SHIFT 0x03 2124 #define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04 2125 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02 2126 #define PALMAS_INT1_MASK_PWRON 0x02 2127 #define PALMAS_INT1_MASK_PWRON_SHIFT 0x01 2128 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01 2129 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0x00 2130 2131 /* Bit definitions for INT1_LINE_STATE */ 2132 #define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80 2133 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 0x07 2134 #define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40 2135 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06 2136 #define PALMAS_INT1_LINE_STATE_HOTDIE 0x20 2137 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 0x05 2138 #define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10 2139 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04 2140 #define PALMAS_INT1_LINE_STATE_RPWRON 0x08 2141 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 0x03 2142 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 2143 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02 2144 #define PALMAS_INT1_LINE_STATE_PWRON 0x02 2145 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 0x01 2146 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01 2147 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0x00 2148 2149 /* Bit definitions for INT2_STATUS */ 2150 #define PALMAS_INT2_STATUS_VAC_ACOK 0x80 2151 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 0x07 2152 #define PALMAS_INT2_STATUS_SHORT 0x40 2153 #define PALMAS_INT2_STATUS_SHORT_SHIFT 0x06 2154 #define PALMAS_INT2_STATUS_FBI_BB 0x20 2155 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT 0x05 2156 #define PALMAS_INT2_STATUS_RESET_IN 0x10 2157 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT 0x04 2158 #define PALMAS_INT2_STATUS_BATREMOVAL 0x08 2159 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 0x03 2160 #define PALMAS_INT2_STATUS_WDT 0x04 2161 #define PALMAS_INT2_STATUS_WDT_SHIFT 0x02 2162 #define PALMAS_INT2_STATUS_RTC_TIMER 0x02 2163 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 0x01 2164 #define PALMAS_INT2_STATUS_RTC_ALARM 0x01 2165 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0x00 2166 2167 /* Bit definitions for INT2_MASK */ 2168 #define PALMAS_INT2_MASK_VAC_ACOK 0x80 2169 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 0x07 2170 #define PALMAS_INT2_MASK_SHORT 0x40 2171 #define PALMAS_INT2_MASK_SHORT_SHIFT 0x06 2172 #define PALMAS_INT2_MASK_FBI_BB 0x20 2173 #define PALMAS_INT2_MASK_FBI_BB_SHIFT 0x05 2174 #define PALMAS_INT2_MASK_RESET_IN 0x10 2175 #define PALMAS_INT2_MASK_RESET_IN_SHIFT 0x04 2176 #define PALMAS_INT2_MASK_BATREMOVAL 0x08 2177 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 0x03 2178 #define PALMAS_INT2_MASK_WDT 0x04 2179 #define PALMAS_INT2_MASK_WDT_SHIFT 0x02 2180 #define PALMAS_INT2_MASK_RTC_TIMER 0x02 2181 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 0x01 2182 #define PALMAS_INT2_MASK_RTC_ALARM 0x01 2183 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0x00 2184 2185 /* Bit definitions for INT2_LINE_STATE */ 2186 #define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80 2187 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 0x07 2188 #define PALMAS_INT2_LINE_STATE_SHORT 0x40 2189 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 0x06 2190 #define PALMAS_INT2_LINE_STATE_FBI_BB 0x20 2191 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 0x05 2192 #define PALMAS_INT2_LINE_STATE_RESET_IN 0x10 2193 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 0x04 2194 #define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08 2195 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 0x03 2196 #define PALMAS_INT2_LINE_STATE_WDT 0x04 2197 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT 0x02 2198 #define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02 2199 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 0x01 2200 #define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01 2201 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0x00 2202 2203 /* Bit definitions for INT3_STATUS */ 2204 #define PALMAS_INT3_STATUS_VBUS 0x80 2205 #define PALMAS_INT3_STATUS_VBUS_SHIFT 0x07 2206 #define PALMAS_INT3_STATUS_VBUS_OTG 0x40 2207 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 0x06 2208 #define PALMAS_INT3_STATUS_ID 0x20 2209 #define PALMAS_INT3_STATUS_ID_SHIFT 0x05 2210 #define PALMAS_INT3_STATUS_ID_OTG 0x10 2211 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT 0x04 2212 #define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08 2213 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 0x03 2214 #define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04 2215 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02 2216 #define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02 2217 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01 2218 #define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01 2219 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00 2220 2221 /* Bit definitions for INT3_MASK */ 2222 #define PALMAS_INT3_MASK_VBUS 0x80 2223 #define PALMAS_INT3_MASK_VBUS_SHIFT 0x07 2224 #define PALMAS_INT3_MASK_VBUS_OTG 0x40 2225 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 0x06 2226 #define PALMAS_INT3_MASK_ID 0x20 2227 #define PALMAS_INT3_MASK_ID_SHIFT 0x05 2228 #define PALMAS_INT3_MASK_ID_OTG 0x10 2229 #define PALMAS_INT3_MASK_ID_OTG_SHIFT 0x04 2230 #define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08 2231 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 0x03 2232 #define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04 2233 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02 2234 #define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02 2235 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01 2236 #define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01 2237 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00 2238 2239 /* Bit definitions for INT3_LINE_STATE */ 2240 #define PALMAS_INT3_LINE_STATE_VBUS 0x80 2241 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 0x07 2242 #define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40 2243 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 0x06 2244 #define PALMAS_INT3_LINE_STATE_ID 0x20 2245 #define PALMAS_INT3_LINE_STATE_ID_SHIFT 0x05 2246 #define PALMAS_INT3_LINE_STATE_ID_OTG 0x10 2247 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 0x04 2248 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08 2249 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 0x03 2250 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04 2251 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02 2252 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02 2253 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01 2254 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01 2255 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00 2256 2257 /* Bit definitions for INT4_STATUS */ 2258 #define PALMAS_INT4_STATUS_GPIO_7 0x80 2259 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT 0x07 2260 #define PALMAS_INT4_STATUS_GPIO_6 0x40 2261 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT 0x06 2262 #define PALMAS_INT4_STATUS_GPIO_5 0x20 2263 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT 0x05 2264 #define PALMAS_INT4_STATUS_GPIO_4 0x10 2265 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT 0x04 2266 #define PALMAS_INT4_STATUS_GPIO_3 0x08 2267 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT 0x03 2268 #define PALMAS_INT4_STATUS_GPIO_2 0x04 2269 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT 0x02 2270 #define PALMAS_INT4_STATUS_GPIO_1 0x02 2271 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT 0x01 2272 #define PALMAS_INT4_STATUS_GPIO_0 0x01 2273 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0x00 2274 2275 /* Bit definitions for INT4_MASK */ 2276 #define PALMAS_INT4_MASK_GPIO_7 0x80 2277 #define PALMAS_INT4_MASK_GPIO_7_SHIFT 0x07 2278 #define PALMAS_INT4_MASK_GPIO_6 0x40 2279 #define PALMAS_INT4_MASK_GPIO_6_SHIFT 0x06 2280 #define PALMAS_INT4_MASK_GPIO_5 0x20 2281 #define PALMAS_INT4_MASK_GPIO_5_SHIFT 0x05 2282 #define PALMAS_INT4_MASK_GPIO_4 0x10 2283 #define PALMAS_INT4_MASK_GPIO_4_SHIFT 0x04 2284 #define PALMAS_INT4_MASK_GPIO_3 0x08 2285 #define PALMAS_INT4_MASK_GPIO_3_SHIFT 0x03 2286 #define PALMAS_INT4_MASK_GPIO_2 0x04 2287 #define PALMAS_INT4_MASK_GPIO_2_SHIFT 0x02 2288 #define PALMAS_INT4_MASK_GPIO_1 0x02 2289 #define PALMAS_INT4_MASK_GPIO_1_SHIFT 0x01 2290 #define PALMAS_INT4_MASK_GPIO_0 0x01 2291 #define PALMAS_INT4_MASK_GPIO_0_SHIFT 0x00 2292 2293 /* Bit definitions for INT4_LINE_STATE */ 2294 #define PALMAS_INT4_LINE_STATE_GPIO_7 0x80 2295 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 0x07 2296 #define PALMAS_INT4_LINE_STATE_GPIO_6 0x40 2297 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 0x06 2298 #define PALMAS_INT4_LINE_STATE_GPIO_5 0x20 2299 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 0x05 2300 #define PALMAS_INT4_LINE_STATE_GPIO_4 0x10 2301 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 0x04 2302 #define PALMAS_INT4_LINE_STATE_GPIO_3 0x08 2303 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 0x03 2304 #define PALMAS_INT4_LINE_STATE_GPIO_2 0x04 2305 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 0x02 2306 #define PALMAS_INT4_LINE_STATE_GPIO_1 0x02 2307 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 0x01 2308 #define PALMAS_INT4_LINE_STATE_GPIO_0 0x01 2309 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0x00 2310 2311 /* Bit definitions for INT4_EDGE_DETECT1 */ 2312 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 2313 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07 2314 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 2315 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06 2316 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 2317 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05 2318 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 2319 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04 2320 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 2321 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03 2322 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 2323 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02 2324 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 2325 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01 2326 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 2327 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00 2328 2329 /* Bit definitions for INT4_EDGE_DETECT2 */ 2330 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80 2331 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 0x07 2332 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40 2333 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 0x06 2334 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 2335 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05 2336 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 2337 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04 2338 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 2339 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03 2340 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 2341 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02 2342 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 2343 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01 2344 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 2345 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00 2346 2347 /* Bit definitions for INT_CTRL */ 2348 #define PALMAS_INT_CTRL_INT_PENDING 0x04 2349 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT 0x02 2350 #define PALMAS_INT_CTRL_INT_CLEAR 0x01 2351 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0x00 2352 2353 /* Registers for function USB_OTG */ 2354 #define PALMAS_USB_WAKEUP 0x03 2355 #define PALMAS_USB_VBUS_CTRL_SET 0x04 2356 #define PALMAS_USB_VBUS_CTRL_CLR 0x05 2357 #define PALMAS_USB_ID_CTRL_SET 0x06 2358 #define PALMAS_USB_ID_CTRL_CLEAR 0x07 2359 #define PALMAS_USB_VBUS_INT_SRC 0x08 2360 #define PALMAS_USB_VBUS_INT_LATCH_SET 0x09 2361 #define PALMAS_USB_VBUS_INT_LATCH_CLR 0x0A 2362 #define PALMAS_USB_VBUS_INT_EN_LO_SET 0x0B 2363 #define PALMAS_USB_VBUS_INT_EN_LO_CLR 0x0C 2364 #define PALMAS_USB_VBUS_INT_EN_HI_SET 0x0D 2365 #define PALMAS_USB_VBUS_INT_EN_HI_CLR 0x0E 2366 #define PALMAS_USB_ID_INT_SRC 0x0F 2367 #define PALMAS_USB_ID_INT_LATCH_SET 0x10 2368 #define PALMAS_USB_ID_INT_LATCH_CLR 0x11 2369 #define PALMAS_USB_ID_INT_EN_LO_SET 0x12 2370 #define PALMAS_USB_ID_INT_EN_LO_CLR 0x13 2371 #define PALMAS_USB_ID_INT_EN_HI_SET 0x14 2372 #define PALMAS_USB_ID_INT_EN_HI_CLR 0x15 2373 #define PALMAS_USB_OTG_ADP_CTRL 0x16 2374 #define PALMAS_USB_OTG_ADP_HIGH 0x17 2375 #define PALMAS_USB_OTG_ADP_LOW 0x18 2376 #define PALMAS_USB_OTG_ADP_RISE 0x19 2377 #define PALMAS_USB_OTG_REVISION 0x1A 2378 2379 /* Bit definitions for USB_WAKEUP */ 2380 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01 2381 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0x00 2382 2383 /* Bit definitions for USB_VBUS_CTRL_SET */ 2384 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80 2385 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 0x07 2386 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20 2387 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 0x05 2388 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10 2389 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 0x04 2390 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08 2391 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 0x03 2392 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04 2393 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 0x02 2394 2395 /* Bit definitions for USB_VBUS_CTRL_CLR */ 2396 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80 2397 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 0x07 2398 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20 2399 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 0x05 2400 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10 2401 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 0x04 2402 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08 2403 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 0x03 2404 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04 2405 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 0x02 2406 2407 /* Bit definitions for USB_ID_CTRL_SET */ 2408 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80 2409 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 0x07 2410 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40 2411 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 0x06 2412 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20 2413 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 0x05 2414 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10 2415 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 0x04 2416 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08 2417 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 0x03 2418 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04 2419 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 0x02 2420 2421 /* Bit definitions for USB_ID_CTRL_CLEAR */ 2422 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80 2423 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 0x07 2424 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40 2425 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 0x06 2426 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20 2427 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 0x05 2428 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10 2429 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 0x04 2430 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08 2431 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 0x03 2432 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04 2433 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 0x02 2434 2435 /* Bit definitions for USB_VBUS_INT_SRC */ 2436 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80 2437 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 0x07 2438 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40 2439 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 0x06 2440 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20 2441 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 0x05 2442 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08 2443 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 0x03 2444 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04 2445 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 0x02 2446 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02 2447 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 0x01 2448 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01 2449 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0x00 2450 2451 /* Bit definitions for USB_VBUS_INT_LATCH_SET */ 2452 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80 2453 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 0x07 2454 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40 2455 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 0x06 2456 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20 2457 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 0x05 2458 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10 2459 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 0x04 2460 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08 2461 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 0x03 2462 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04 2463 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 0x02 2464 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02 2465 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 0x01 2466 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01 2467 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0x00 2468 2469 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */ 2470 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80 2471 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 0x07 2472 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40 2473 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 0x06 2474 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20 2475 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 0x05 2476 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10 2477 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 0x04 2478 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08 2479 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 0x03 2480 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04 2481 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 0x02 2482 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02 2483 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 0x01 2484 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01 2485 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0x00 2486 2487 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */ 2488 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80 2489 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 0x07 2490 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40 2491 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 0x06 2492 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20 2493 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 0x05 2494 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08 2495 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 0x03 2496 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04 2497 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 0x02 2498 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02 2499 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 0x01 2500 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01 2501 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0x00 2502 2503 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */ 2504 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80 2505 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 0x07 2506 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40 2507 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 0x06 2508 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20 2509 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 0x05 2510 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08 2511 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 0x03 2512 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04 2513 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 0x02 2514 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02 2515 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 0x01 2516 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01 2517 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0x00 2518 2519 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */ 2520 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80 2521 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 0x07 2522 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40 2523 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 0x06 2524 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20 2525 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 0x05 2526 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10 2527 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 0x04 2528 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08 2529 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 0x03 2530 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04 2531 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 0x02 2532 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02 2533 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 0x01 2534 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01 2535 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0x00 2536 2537 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */ 2538 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80 2539 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 0x07 2540 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40 2541 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 0x06 2542 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20 2543 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 0x05 2544 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10 2545 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 0x04 2546 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08 2547 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 0x03 2548 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04 2549 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 0x02 2550 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02 2551 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 0x01 2552 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01 2553 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0x00 2554 2555 /* Bit definitions for USB_ID_INT_SRC */ 2556 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10 2557 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 0x04 2558 #define PALMAS_USB_ID_INT_SRC_ID_A 0x08 2559 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 0x03 2560 #define PALMAS_USB_ID_INT_SRC_ID_B 0x04 2561 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 0x02 2562 #define PALMAS_USB_ID_INT_SRC_ID_C 0x02 2563 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 0x01 2564 #define PALMAS_USB_ID_INT_SRC_ID_GND 0x01 2565 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0x00 2566 2567 /* Bit definitions for USB_ID_INT_LATCH_SET */ 2568 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10 2569 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 0x04 2570 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08 2571 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 0x03 2572 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04 2573 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 0x02 2574 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02 2575 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 0x01 2576 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01 2577 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0x00 2578 2579 /* Bit definitions for USB_ID_INT_LATCH_CLR */ 2580 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10 2581 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 0x04 2582 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08 2583 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 0x03 2584 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04 2585 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 0x02 2586 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02 2587 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 0x01 2588 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01 2589 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0x00 2590 2591 /* Bit definitions for USB_ID_INT_EN_LO_SET */ 2592 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10 2593 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 0x04 2594 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08 2595 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 0x03 2596 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04 2597 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 0x02 2598 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02 2599 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 0x01 2600 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01 2601 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0x00 2602 2603 /* Bit definitions for USB_ID_INT_EN_LO_CLR */ 2604 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10 2605 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 0x04 2606 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08 2607 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 0x03 2608 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04 2609 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 0x02 2610 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02 2611 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 0x01 2612 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01 2613 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0x00 2614 2615 /* Bit definitions for USB_ID_INT_EN_HI_SET */ 2616 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10 2617 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 0x04 2618 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08 2619 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 0x03 2620 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04 2621 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 0x02 2622 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02 2623 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 0x01 2624 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01 2625 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0x00 2626 2627 /* Bit definitions for USB_ID_INT_EN_HI_CLR */ 2628 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10 2629 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 0x04 2630 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08 2631 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 0x03 2632 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04 2633 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 0x02 2634 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02 2635 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 0x01 2636 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01 2637 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0x00 2638 2639 /* Bit definitions for USB_OTG_ADP_CTRL */ 2640 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04 2641 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 0x02 2642 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03 2643 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0x00 2644 2645 /* Bit definitions for USB_OTG_ADP_HIGH */ 2646 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xFF 2647 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0x00 2648 2649 /* Bit definitions for USB_OTG_ADP_LOW */ 2650 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xFF 2651 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0x00 2652 2653 /* Bit definitions for USB_OTG_ADP_RISE */ 2654 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xFF 2655 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0x00 2656 2657 /* Bit definitions for USB_OTG_REVISION */ 2658 #define PALMAS_USB_OTG_REVISION_OTG_REV 0x01 2659 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0x00 2660 2661 /* Registers for function VIBRATOR */ 2662 #define PALMAS_VIBRA_CTRL 0x00 2663 2664 /* Bit definitions for VIBRA_CTRL */ 2665 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06 2666 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 0x01 2667 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01 2668 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0x00 2669 2670 /* Registers for function GPIO */ 2671 #define PALMAS_GPIO_DATA_IN 0x00 2672 #define PALMAS_GPIO_DATA_DIR 0x01 2673 #define PALMAS_GPIO_DATA_OUT 0x02 2674 #define PALMAS_GPIO_DEBOUNCE_EN 0x03 2675 #define PALMAS_GPIO_CLEAR_DATA_OUT 0x04 2676 #define PALMAS_GPIO_SET_DATA_OUT 0x05 2677 #define PALMAS_PU_PD_GPIO_CTRL1 0x06 2678 #define PALMAS_PU_PD_GPIO_CTRL2 0x07 2679 #define PALMAS_OD_OUTPUT_GPIO_CTRL 0x08 2680 #define PALMAS_GPIO_DATA_IN2 0x09 2681 #define PALMAS_GPIO_DATA_DIR2 0x0A 2682 #define PALMAS_GPIO_DATA_OUT2 0x0B 2683 #define PALMAS_GPIO_DEBOUNCE_EN2 0x0C 2684 #define PALMAS_GPIO_CLEAR_DATA_OUT2 0x0D 2685 #define PALMAS_GPIO_SET_DATA_OUT2 0x0E 2686 #define PALMAS_PU_PD_GPIO_CTRL3 0x0F 2687 #define PALMAS_PU_PD_GPIO_CTRL4 0x10 2688 #define PALMAS_OD_OUTPUT_GPIO_CTRL2 0x11 2689 2690 /* Bit definitions for GPIO_DATA_IN */ 2691 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80 2692 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 0x07 2693 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40 2694 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 0x06 2695 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20 2696 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 0x05 2697 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10 2698 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 0x04 2699 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08 2700 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 0x03 2701 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04 2702 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 0x02 2703 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02 2704 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 0x01 2705 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01 2706 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0x00 2707 2708 /* Bit definitions for GPIO_DATA_DIR */ 2709 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80 2710 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 0x07 2711 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40 2712 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 0x06 2713 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20 2714 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 0x05 2715 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10 2716 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 0x04 2717 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08 2718 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 0x03 2719 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04 2720 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 0x02 2721 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02 2722 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 0x01 2723 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01 2724 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0x00 2725 2726 /* Bit definitions for GPIO_DATA_OUT */ 2727 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80 2728 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 0x07 2729 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40 2730 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 0x06 2731 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20 2732 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 0x05 2733 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10 2734 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 0x04 2735 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08 2736 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 0x03 2737 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04 2738 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 0x02 2739 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02 2740 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 0x01 2741 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01 2742 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0x00 2743 2744 /* Bit definitions for GPIO_DEBOUNCE_EN */ 2745 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80 2746 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 0x07 2747 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40 2748 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 0x06 2749 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20 2750 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 0x05 2751 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10 2752 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 0x04 2753 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08 2754 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 0x03 2755 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04 2756 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 0x02 2757 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02 2758 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 0x01 2759 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01 2760 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0x00 2761 2762 /* Bit definitions for GPIO_CLEAR_DATA_OUT */ 2763 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80 2764 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 0x07 2765 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40 2766 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 0x06 2767 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20 2768 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 0x05 2769 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10 2770 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 0x04 2771 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08 2772 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 0x03 2773 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04 2774 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 0x02 2775 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02 2776 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 0x01 2777 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01 2778 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0x00 2779 2780 /* Bit definitions for GPIO_SET_DATA_OUT */ 2781 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80 2782 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 0x07 2783 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40 2784 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 0x06 2785 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20 2786 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 0x05 2787 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10 2788 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 0x04 2789 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08 2790 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 0x03 2791 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04 2792 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 0x02 2793 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02 2794 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 0x01 2795 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01 2796 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0x00 2797 2798 /* Bit definitions for PU_PD_GPIO_CTRL1 */ 2799 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40 2800 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 0x06 2801 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20 2802 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 0x05 2803 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10 2804 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 0x04 2805 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08 2806 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 0x03 2807 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04 2808 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 0x02 2809 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01 2810 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0x00 2811 2812 /* Bit definitions for PU_PD_GPIO_CTRL2 */ 2813 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40 2814 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 0x06 2815 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20 2816 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 0x05 2817 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10 2818 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 0x04 2819 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08 2820 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 0x03 2821 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04 2822 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 0x02 2823 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02 2824 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 0x01 2825 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01 2826 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0x00 2827 2828 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */ 2829 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20 2830 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 0x05 2831 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04 2832 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 0x02 2833 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02 2834 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 0x01 2835 2836 /* Registers for function GPADC */ 2837 #define PALMAS_GPADC_CTRL1 0x00 2838 #define PALMAS_GPADC_CTRL2 0x01 2839 #define PALMAS_GPADC_RT_CTRL 0x02 2840 #define PALMAS_GPADC_AUTO_CTRL 0x03 2841 #define PALMAS_GPADC_STATUS 0x04 2842 #define PALMAS_GPADC_RT_SELECT 0x05 2843 #define PALMAS_GPADC_RT_CONV0_LSB 0x06 2844 #define PALMAS_GPADC_RT_CONV0_MSB 0x07 2845 #define PALMAS_GPADC_AUTO_SELECT 0x08 2846 #define PALMAS_GPADC_AUTO_CONV0_LSB 0x09 2847 #define PALMAS_GPADC_AUTO_CONV0_MSB 0x0A 2848 #define PALMAS_GPADC_AUTO_CONV1_LSB 0x0B 2849 #define PALMAS_GPADC_AUTO_CONV1_MSB 0x0C 2850 #define PALMAS_GPADC_SW_SELECT 0x0D 2851 #define PALMAS_GPADC_SW_CONV0_LSB 0x0E 2852 #define PALMAS_GPADC_SW_CONV0_MSB 0x0F 2853 #define PALMAS_GPADC_THRES_CONV0_LSB 0x10 2854 #define PALMAS_GPADC_THRES_CONV0_MSB 0x11 2855 #define PALMAS_GPADC_THRES_CONV1_LSB 0x12 2856 #define PALMAS_GPADC_THRES_CONV1_MSB 0x13 2857 #define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14 2858 #define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15 2859 2860 /* Bit definitions for GPADC_CTRL1 */ 2861 #define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0 2862 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 0x06 2863 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30 2864 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 0x04 2865 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c 2866 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 0x02 2867 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02 2868 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 0x01 2869 #define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01 2870 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0x00 2871 2872 /* Bit definitions for GPADC_CTRL2 */ 2873 #define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06 2874 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 0x01 2875 2876 /* Bit definitions for GPADC_RT_CTRL */ 2877 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02 2878 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 0x01 2879 #define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01 2880 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0x00 2881 2882 /* Bit definitions for GPADC_AUTO_CTRL */ 2883 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80 2884 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 0x07 2885 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40 2886 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 0x06 2887 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20 2888 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 0x05 2889 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10 2890 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 0x04 2891 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0F 2892 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0x00 2893 2894 /* Bit definitions for GPADC_STATUS */ 2895 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10 2896 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 0x04 2897 2898 /* Bit definitions for GPADC_RT_SELECT */ 2899 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80 2900 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 0x07 2901 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0F 2902 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0x00 2903 2904 /* Bit definitions for GPADC_RT_CONV0_LSB */ 2905 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xFF 2906 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0x00 2907 2908 /* Bit definitions for GPADC_RT_CONV0_MSB */ 2909 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0F 2910 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0x00 2911 2912 /* Bit definitions for GPADC_AUTO_SELECT */ 2913 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xF0 2914 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 0x04 2915 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0F 2916 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0x00 2917 2918 /* Bit definitions for GPADC_AUTO_CONV0_LSB */ 2919 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xFF 2920 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0x00 2921 2922 /* Bit definitions for GPADC_AUTO_CONV0_MSB */ 2923 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0F 2924 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0x00 2925 2926 /* Bit definitions for GPADC_AUTO_CONV1_LSB */ 2927 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xFF 2928 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0x00 2929 2930 /* Bit definitions for GPADC_AUTO_CONV1_MSB */ 2931 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0F 2932 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0x00 2933 2934 /* Bit definitions for GPADC_SW_SELECT */ 2935 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80 2936 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 0x07 2937 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10 2938 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 0x04 2939 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0F 2940 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0x00 2941 2942 /* Bit definitions for GPADC_SW_CONV0_LSB */ 2943 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xFF 2944 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0x00 2945 2946 /* Bit definitions for GPADC_SW_CONV0_MSB */ 2947 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0F 2948 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0x00 2949 2950 /* Bit definitions for GPADC_THRES_CONV0_LSB */ 2951 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xFF 2952 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0x00 2953 2954 /* Bit definitions for GPADC_THRES_CONV0_MSB */ 2955 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80 2956 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 0x07 2957 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0F 2958 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0x00 2959 2960 /* Bit definitions for GPADC_THRES_CONV1_LSB */ 2961 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xFF 2962 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0x00 2963 2964 /* Bit definitions for GPADC_THRES_CONV1_MSB */ 2965 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80 2966 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 0x07 2967 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0F 2968 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0x00 2969 2970 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */ 2971 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20 2972 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 0x05 2973 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10 2974 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 0x04 2975 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0F 2976 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0x00 2977 2978 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */ 2979 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80 2980 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 0x07 2981 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7F 2982 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0x00 2983 2984 /* Registers for function GPADC */ 2985 #define PALMAS_GPADC_TRIM1 0x00 2986 #define PALMAS_GPADC_TRIM2 0x01 2987 #define PALMAS_GPADC_TRIM3 0x02 2988 #define PALMAS_GPADC_TRIM4 0x03 2989 #define PALMAS_GPADC_TRIM5 0x04 2990 #define PALMAS_GPADC_TRIM6 0x05 2991 #define PALMAS_GPADC_TRIM7 0x06 2992 #define PALMAS_GPADC_TRIM8 0x07 2993 #define PALMAS_GPADC_TRIM9 0x08 2994 #define PALMAS_GPADC_TRIM10 0x09 2995 #define PALMAS_GPADC_TRIM11 0x0A 2996 #define PALMAS_GPADC_TRIM12 0x0B 2997 #define PALMAS_GPADC_TRIM13 0x0C 2998 #define PALMAS_GPADC_TRIM14 0x0D 2999 #define PALMAS_GPADC_TRIM15 0x0E 3000 #define PALMAS_GPADC_TRIM16 0x0F 3001 3002 /* TPS65917 Interrupt registers */ 3003 3004 /* Registers for function INTERRUPT */ 3005 #define TPS65917_INT1_STATUS 0x00 3006 #define TPS65917_INT1_MASK 0x01 3007 #define TPS65917_INT1_LINE_STATE 0x02 3008 #define TPS65917_INT2_STATUS 0x05 3009 #define TPS65917_INT2_MASK 0x06 3010 #define TPS65917_INT2_LINE_STATE 0x07 3011 #define TPS65917_INT3_STATUS 0x0A 3012 #define TPS65917_INT3_MASK 0x0B 3013 #define TPS65917_INT3_LINE_STATE 0x0C 3014 #define TPS65917_INT4_STATUS 0x0F 3015 #define TPS65917_INT4_MASK 0x10 3016 #define TPS65917_INT4_LINE_STATE 0x11 3017 #define TPS65917_INT4_EDGE_DETECT1 0x12 3018 #define TPS65917_INT4_EDGE_DETECT2 0x13 3019 #define TPS65917_INT_CTRL 0x14 3020 3021 /* Bit definitions for INT1_STATUS */ 3022 #define TPS65917_INT1_STATUS_VSYS_MON 0x40 3023 #define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06 3024 #define TPS65917_INT1_STATUS_HOTDIE 0x20 3025 #define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05 3026 #define TPS65917_INT1_STATUS_PWRDOWN 0x10 3027 #define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04 3028 #define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04 3029 #define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02 3030 #define TPS65917_INT1_STATUS_PWRON 0x02 3031 #define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01 3032 3033 /* Bit definitions for INT1_MASK */ 3034 #define TPS65917_INT1_MASK_VSYS_MON 0x40 3035 #define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06 3036 #define TPS65917_INT1_MASK_HOTDIE 0x20 3037 #define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05 3038 #define TPS65917_INT1_MASK_PWRDOWN 0x10 3039 #define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04 3040 #define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04 3041 #define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02 3042 #define TPS65917_INT1_MASK_PWRON 0x02 3043 #define TPS65917_INT1_MASK_PWRON_SHIFT 0x01 3044 3045 /* Bit definitions for INT1_LINE_STATE */ 3046 #define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40 3047 #define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06 3048 #define TPS65917_INT1_LINE_STATE_HOTDIE 0x20 3049 #define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05 3050 #define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10 3051 #define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04 3052 #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 3053 #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02 3054 #define TPS65917_INT1_LINE_STATE_PWRON 0x02 3055 #define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01 3056 3057 /* Bit definitions for INT2_STATUS */ 3058 #define TPS65917_INT2_STATUS_SHORT 0x40 3059 #define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06 3060 #define TPS65917_INT2_STATUS_FSD 0x20 3061 #define TPS65917_INT2_STATUS_FSD_SHIFT 0x05 3062 #define TPS65917_INT2_STATUS_RESET_IN 0x10 3063 #define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04 3064 #define TPS65917_INT2_STATUS_WDT 0x04 3065 #define TPS65917_INT2_STATUS_WDT_SHIFT 0x02 3066 #define TPS65917_INT2_STATUS_OTP_ERROR 0x02 3067 #define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01 3068 3069 /* Bit definitions for INT2_MASK */ 3070 #define TPS65917_INT2_MASK_SHORT 0x40 3071 #define TPS65917_INT2_MASK_SHORT_SHIFT 0x06 3072 #define TPS65917_INT2_MASK_FSD 0x20 3073 #define TPS65917_INT2_MASK_FSD_SHIFT 0x05 3074 #define TPS65917_INT2_MASK_RESET_IN 0x10 3075 #define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04 3076 #define TPS65917_INT2_MASK_WDT 0x04 3077 #define TPS65917_INT2_MASK_WDT_SHIFT 0x02 3078 #define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02 3079 #define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01 3080 3081 /* Bit definitions for INT2_LINE_STATE */ 3082 #define TPS65917_INT2_LINE_STATE_SHORT 0x40 3083 #define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06 3084 #define TPS65917_INT2_LINE_STATE_FSD 0x20 3085 #define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05 3086 #define TPS65917_INT2_LINE_STATE_RESET_IN 0x10 3087 #define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04 3088 #define TPS65917_INT2_LINE_STATE_WDT 0x04 3089 #define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02 3090 #define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02 3091 #define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01 3092 3093 /* Bit definitions for INT3_STATUS */ 3094 #define TPS65917_INT3_STATUS_VBUS 0x80 3095 #define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07 3096 #define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04 3097 #define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02 3098 #define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02 3099 #define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01 3100 #define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01 3101 #define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00 3102 3103 /* Bit definitions for INT3_MASK */ 3104 #define TPS65917_INT3_MASK_VBUS 0x80 3105 #define TPS65917_INT3_MASK_VBUS_SHIFT 0x07 3106 #define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04 3107 #define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02 3108 #define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02 3109 #define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01 3110 #define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01 3111 #define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00 3112 3113 /* Bit definitions for INT3_LINE_STATE */ 3114 #define TPS65917_INT3_LINE_STATE_VBUS 0x80 3115 #define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07 3116 #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04 3117 #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02 3118 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02 3119 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01 3120 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01 3121 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00 3122 3123 /* Bit definitions for INT4_STATUS */ 3124 #define TPS65917_INT4_STATUS_GPIO_6 0x40 3125 #define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06 3126 #define TPS65917_INT4_STATUS_GPIO_5 0x20 3127 #define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05 3128 #define TPS65917_INT4_STATUS_GPIO_4 0x10 3129 #define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04 3130 #define TPS65917_INT4_STATUS_GPIO_3 0x08 3131 #define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03 3132 #define TPS65917_INT4_STATUS_GPIO_2 0x04 3133 #define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02 3134 #define TPS65917_INT4_STATUS_GPIO_1 0x02 3135 #define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01 3136 #define TPS65917_INT4_STATUS_GPIO_0 0x01 3137 #define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00 3138 3139 /* Bit definitions for INT4_MASK */ 3140 #define TPS65917_INT4_MASK_GPIO_6 0x40 3141 #define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06 3142 #define TPS65917_INT4_MASK_GPIO_5 0x20 3143 #define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05 3144 #define TPS65917_INT4_MASK_GPIO_4 0x10 3145 #define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04 3146 #define TPS65917_INT4_MASK_GPIO_3 0x08 3147 #define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03 3148 #define TPS65917_INT4_MASK_GPIO_2 0x04 3149 #define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02 3150 #define TPS65917_INT4_MASK_GPIO_1 0x02 3151 #define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01 3152 #define TPS65917_INT4_MASK_GPIO_0 0x01 3153 #define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00 3154 3155 /* Bit definitions for INT4_LINE_STATE */ 3156 #define TPS65917_INT4_LINE_STATE_GPIO_6 0x40 3157 #define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06 3158 #define TPS65917_INT4_LINE_STATE_GPIO_5 0x20 3159 #define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05 3160 #define TPS65917_INT4_LINE_STATE_GPIO_4 0x10 3161 #define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04 3162 #define TPS65917_INT4_LINE_STATE_GPIO_3 0x08 3163 #define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03 3164 #define TPS65917_INT4_LINE_STATE_GPIO_2 0x04 3165 #define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02 3166 #define TPS65917_INT4_LINE_STATE_GPIO_1 0x02 3167 #define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01 3168 #define TPS65917_INT4_LINE_STATE_GPIO_0 0x01 3169 #define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00 3170 3171 /* Bit definitions for INT4_EDGE_DETECT1 */ 3172 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 3173 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07 3174 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 3175 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06 3176 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 3177 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05 3178 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 3179 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04 3180 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 3181 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03 3182 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 3183 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02 3184 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 3185 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01 3186 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 3187 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00 3188 3189 /* Bit definitions for INT4_EDGE_DETECT2 */ 3190 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 3191 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05 3192 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 3193 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04 3194 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 3195 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03 3196 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 3197 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02 3198 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 3199 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01 3200 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 3201 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00 3202 3203 /* Bit definitions for INT_CTRL */ 3204 #define TPS65917_INT_CTRL_INT_PENDING 0x04 3205 #define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02 3206 #define TPS65917_INT_CTRL_INT_CLEAR 0x01 3207 #define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00 3208 3209 /* TPS65917 SMPS Registers */ 3210 3211 /* Registers for function SMPS */ 3212 #define TPS65917_SMPS1_CTRL 0x00 3213 #define TPS65917_SMPS1_FORCE 0x02 3214 #define TPS65917_SMPS1_VOLTAGE 0x03 3215 #define TPS65917_SMPS2_CTRL 0x04 3216 #define TPS65917_SMPS2_FORCE 0x06 3217 #define TPS65917_SMPS2_VOLTAGE 0x07 3218 #define TPS65917_SMPS3_CTRL 0x0C 3219 #define TPS65917_SMPS3_FORCE 0x0E 3220 #define TPS65917_SMPS3_VOLTAGE 0x0F 3221 #define TPS65917_SMPS4_CTRL 0x10 3222 #define TPS65917_SMPS4_VOLTAGE 0x13 3223 #define TPS65917_SMPS5_CTRL 0x18 3224 #define TPS65917_SMPS5_VOLTAGE 0x1B 3225 #define TPS65917_SMPS_CTRL 0x24 3226 #define TPS65917_SMPS_PD_CTRL 0x25 3227 #define TPS65917_SMPS_THERMAL_EN 0x27 3228 #define TPS65917_SMPS_THERMAL_STATUS 0x28 3229 #define TPS65917_SMPS_SHORT_STATUS 0x29 3230 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A 3231 #define TPS65917_SMPS_POWERGOOD_MASK1 0x2B 3232 #define TPS65917_SMPS_POWERGOOD_MASK2 0x2C 3233 3234 /* Bit definitions for SMPS1_CTRL */ 3235 #define TPS65917_SMPS1_CTRL_WR_S 0x80 3236 #define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07 3237 #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40 3238 #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 3239 #define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30 3240 #define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04 3241 #define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C 3242 #define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02 3243 #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03 3244 #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00 3245 3246 /* Bit definitions for SMPS1_FORCE */ 3247 #define TPS65917_SMPS1_FORCE_CMD 0x80 3248 #define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07 3249 #define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F 3250 #define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00 3251 3252 /* Bit definitions for SMPS1_VOLTAGE */ 3253 #define TPS65917_SMPS1_VOLTAGE_RANGE 0x80 3254 #define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07 3255 #define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F 3256 #define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00 3257 3258 /* Bit definitions for SMPS2_CTRL */ 3259 #define TPS65917_SMPS2_CTRL_WR_S 0x80 3260 #define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07 3261 #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40 3262 #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 3263 #define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30 3264 #define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04 3265 #define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C 3266 #define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02 3267 #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03 3268 #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00 3269 3270 /* Bit definitions for SMPS2_FORCE */ 3271 #define TPS65917_SMPS2_FORCE_CMD 0x80 3272 #define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07 3273 #define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F 3274 #define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00 3275 3276 /* Bit definitions for SMPS2_VOLTAGE */ 3277 #define TPS65917_SMPS2_VOLTAGE_RANGE 0x80 3278 #define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07 3279 #define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F 3280 #define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00 3281 3282 /* Bit definitions for SMPS3_CTRL */ 3283 #define TPS65917_SMPS3_CTRL_WR_S 0x80 3284 #define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07 3285 #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40 3286 #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 3287 #define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30 3288 #define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04 3289 #define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C 3290 #define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02 3291 #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 3292 #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00 3293 3294 /* Bit definitions for SMPS3_FORCE */ 3295 #define TPS65917_SMPS3_FORCE_CMD 0x80 3296 #define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07 3297 #define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F 3298 #define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00 3299 3300 /* Bit definitions for SMPS3_VOLTAGE */ 3301 #define TPS65917_SMPS3_VOLTAGE_RANGE 0x80 3302 #define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07 3303 #define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F 3304 #define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00 3305 3306 /* Bit definitions for SMPS4_CTRL */ 3307 #define TPS65917_SMPS4_CTRL_WR_S 0x80 3308 #define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07 3309 #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40 3310 #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 3311 #define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30 3312 #define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04 3313 #define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C 3314 #define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02 3315 #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03 3316 #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00 3317 3318 /* Bit definitions for SMPS4_VOLTAGE */ 3319 #define TPS65917_SMPS4_VOLTAGE_RANGE 0x80 3320 #define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07 3321 #define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F 3322 #define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00 3323 3324 /* Bit definitions for SMPS5_CTRL */ 3325 #define TPS65917_SMPS5_CTRL_WR_S 0x80 3326 #define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07 3327 #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40 3328 #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 3329 #define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30 3330 #define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04 3331 #define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C 3332 #define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02 3333 #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03 3334 #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00 3335 3336 /* Bit definitions for SMPS5_VOLTAGE */ 3337 #define TPS65917_SMPS5_VOLTAGE_RANGE 0x80 3338 #define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07 3339 #define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F 3340 #define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00 3341 3342 /* Bit definitions for SMPS_CTRL */ 3343 #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10 3344 #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04 3345 #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03 3346 #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00 3347 3348 /* Bit definitions for SMPS_PD_CTRL */ 3349 #define TPS65917_SMPS_PD_CTRL_SMPS5 0x40 3350 #define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06 3351 #define TPS65917_SMPS_PD_CTRL_SMPS4 0x10 3352 #define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04 3353 #define TPS65917_SMPS_PD_CTRL_SMPS3 0x08 3354 #define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03 3355 #define TPS65917_SMPS_PD_CTRL_SMPS2 0x02 3356 #define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01 3357 #define TPS65917_SMPS_PD_CTRL_SMPS1 0x01 3358 #define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00 3359 3360 /* Bit definitions for SMPS_THERMAL_EN */ 3361 #define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40 3362 #define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06 3363 #define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08 3364 #define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03 3365 #define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01 3366 #define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00 3367 3368 /* Bit definitions for SMPS_THERMAL_STATUS */ 3369 #define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40 3370 #define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06 3371 #define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08 3372 #define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03 3373 #define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01 3374 #define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00 3375 3376 /* Bit definitions for SMPS_SHORT_STATUS */ 3377 #define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40 3378 #define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06 3379 #define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10 3380 #define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04 3381 #define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08 3382 #define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03 3383 #define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02 3384 #define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01 3385 #define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01 3386 #define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00 3387 3388 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ 3389 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40 3390 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06 3391 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10 3392 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04 3393 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08 3394 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03 3395 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02 3396 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01 3397 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01 3398 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00 3399 3400 /* Bit definitions for SMPS_POWERGOOD_MASK1 */ 3401 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40 3402 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06 3403 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10 3404 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04 3405 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08 3406 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03 3407 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02 3408 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01 3409 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01 3410 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00 3411 3412 /* Bit definitions for SMPS_POWERGOOD_MASK2 */ 3413 #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 3414 #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07 3415 #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10 3416 #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04 3417 3418 /* Bit definitions for SMPS_PLL_CTRL */ 3419 3420 #define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08 3421 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03 3422 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04 3423 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02 3424 3425 /* Registers for function LDO */ 3426 #define TPS65917_LDO1_CTRL 0x00 3427 #define TPS65917_LDO1_VOLTAGE 0x01 3428 #define TPS65917_LDO2_CTRL 0x02 3429 #define TPS65917_LDO2_VOLTAGE 0x03 3430 #define TPS65917_LDO3_CTRL 0x04 3431 #define TPS65917_LDO3_VOLTAGE 0x05 3432 #define TPS65917_LDO4_CTRL 0x0E 3433 #define TPS65917_LDO4_VOLTAGE 0x0F 3434 #define TPS65917_LDO5_CTRL 0x12 3435 #define TPS65917_LDO5_VOLTAGE 0x13 3436 #define TPS65917_LDO_PD_CTRL1 0x1B 3437 #define TPS65917_LDO_PD_CTRL2 0x1C 3438 #define TPS65917_LDO_SHORT_STATUS1 0x1D 3439 #define TPS65917_LDO_SHORT_STATUS2 0x1E 3440 #define TPS65917_LDO_PD_CTRL3 0x2D 3441 #define TPS65917_LDO_SHORT_STATUS3 0x2E 3442 3443 /* Bit definitions for LDO1_CTRL */ 3444 #define TPS65917_LDO1_CTRL_WR_S 0x80 3445 #define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07 3446 #define TPS65917_LDO1_CTRL_BYPASS_EN 0x40 3447 #define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06 3448 #define TPS65917_LDO1_CTRL_STATUS 0x10 3449 #define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04 3450 #define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04 3451 #define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02 3452 #define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01 3453 #define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00 3454 3455 /* Bit definitions for LDO1_VOLTAGE */ 3456 #define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F 3457 #define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00 3458 3459 /* Bit definitions for LDO2_CTRL */ 3460 #define TPS65917_LDO2_CTRL_WR_S 0x80 3461 #define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07 3462 #define TPS65917_LDO2_CTRL_BYPASS_EN 0x40 3463 #define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06 3464 #define TPS65917_LDO2_CTRL_STATUS 0x10 3465 #define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04 3466 #define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04 3467 #define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02 3468 #define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01 3469 #define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00 3470 3471 /* Bit definitions for LDO2_VOLTAGE */ 3472 #define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F 3473 #define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00 3474 3475 /* Bit definitions for LDO3_CTRL */ 3476 #define TPS65917_LDO3_CTRL_WR_S 0x80 3477 #define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07 3478 #define TPS65917_LDO3_CTRL_STATUS 0x10 3479 #define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04 3480 #define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04 3481 #define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02 3482 #define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01 3483 #define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00 3484 3485 /* Bit definitions for LDO3_VOLTAGE */ 3486 #define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F 3487 #define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00 3488 3489 /* Bit definitions for LDO4_CTRL */ 3490 #define TPS65917_LDO4_CTRL_WR_S 0x80 3491 #define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07 3492 #define TPS65917_LDO4_CTRL_STATUS 0x10 3493 #define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04 3494 #define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04 3495 #define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02 3496 #define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01 3497 #define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00 3498 3499 /* Bit definitions for LDO4_VOLTAGE */ 3500 #define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F 3501 #define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00 3502 3503 /* Bit definitions for LDO5_CTRL */ 3504 #define TPS65917_LDO5_CTRL_WR_S 0x80 3505 #define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07 3506 #define TPS65917_LDO5_CTRL_STATUS 0x10 3507 #define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04 3508 #define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04 3509 #define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02 3510 #define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01 3511 #define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00 3512 3513 /* Bit definitions for LDO5_VOLTAGE */ 3514 #define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F 3515 #define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00 3516 3517 /* Bit definitions for LDO_PD_CTRL1 */ 3518 #define TPS65917_LDO_PD_CTRL1_LDO4 0x80 3519 #define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07 3520 #define TPS65917_LDO_PD_CTRL1_LDO2 0x02 3521 #define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01 3522 #define TPS65917_LDO_PD_CTRL1_LDO1 0x01 3523 #define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00 3524 3525 /* Bit definitions for LDO_PD_CTRL2 */ 3526 #define TPS65917_LDO_PD_CTRL2_LDO3 0x04 3527 #define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02 3528 #define TPS65917_LDO_PD_CTRL2_LDO5 0x02 3529 #define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01 3530 3531 /* Bit definitions for LDO_PD_CTRL3 */ 3532 #define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80 3533 #define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07 3534 3535 /* Bit definitions for LDO_SHORT_STATUS1 */ 3536 #define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80 3537 #define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07 3538 #define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02 3539 #define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01 3540 #define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01 3541 #define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00 3542 3543 /* Bit definitions for LDO_SHORT_STATUS2 */ 3544 #define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04 3545 #define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02 3546 #define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02 3547 #define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01 3548 3549 /* Bit definitions for LDO_SHORT_STATUS2 */ 3550 #define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80 3551 #define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07 3552 3553 /* Bit definitions for REGEN1_CTRL */ 3554 #define TPS65917_REGEN1_CTRL_STATUS 0x10 3555 #define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04 3556 #define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04 3557 #define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02 3558 #define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01 3559 #define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 3560 3561 /* Bit definitions for PLLEN_CTRL */ 3562 #define TPS65917_PLLEN_CTRL_STATUS 0x10 3563 #define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04 3564 #define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04 3565 #define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02 3566 #define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01 3567 #define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00 3568 3569 /* Bit definitions for REGEN2_CTRL */ 3570 #define TPS65917_REGEN2_CTRL_STATUS 0x10 3571 #define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04 3572 #define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04 3573 #define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02 3574 #define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01 3575 #define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 3576 3577 /* Bit definitions for NSLEEP_RES_ASSIGN */ 3578 #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08 3579 #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03 3580 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04 3581 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02 3582 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02 3583 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01 3584 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01 3585 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00 3586 3587 /* Bit definitions for NSLEEP_SMPS_ASSIGN */ 3588 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40 3589 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06 3590 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10 3591 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04 3592 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08 3593 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03 3594 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02 3595 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01 3596 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01 3597 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00 3598 3599 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */ 3600 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80 3601 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07 3602 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02 3603 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01 3604 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01 3605 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00 3606 3607 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */ 3608 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04 3609 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02 3610 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02 3611 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01 3612 3613 /* Bit definitions for ENABLE1_RES_ASSIGN */ 3614 #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08 3615 #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03 3616 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04 3617 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02 3618 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02 3619 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01 3620 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01 3621 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00 3622 3623 /* Bit definitions for ENABLE1_SMPS_ASSIGN */ 3624 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40 3625 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06 3626 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10 3627 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04 3628 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08 3629 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03 3630 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02 3631 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01 3632 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01 3633 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00 3634 3635 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */ 3636 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80 3637 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07 3638 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02 3639 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01 3640 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01 3641 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00 3642 3643 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */ 3644 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04 3645 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02 3646 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02 3647 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01 3648 3649 /* Bit definitions for ENABLE2_RES_ASSIGN */ 3650 #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08 3651 #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03 3652 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04 3653 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02 3654 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02 3655 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01 3656 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01 3657 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00 3658 3659 /* Bit definitions for ENABLE2_SMPS_ASSIGN */ 3660 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40 3661 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06 3662 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10 3663 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04 3664 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08 3665 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03 3666 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02 3667 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01 3668 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01 3669 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00 3670 3671 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */ 3672 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80 3673 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07 3674 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02 3675 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01 3676 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01 3677 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00 3678 3679 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */ 3680 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04 3681 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02 3682 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02 3683 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01 3684 3685 /* Bit definitions for REGEN3_CTRL */ 3686 #define TPS65917_REGEN3_CTRL_STATUS 0x10 3687 #define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04 3688 #define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04 3689 #define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02 3690 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01 3691 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00 3692 3693 /* Registers for function RESOURCE */ 3694 #define TPS65917_REGEN1_CTRL 0x2 3695 #define TPS65917_PLLEN_CTRL 0x3 3696 #define TPS65917_NSLEEP_RES_ASSIGN 0x6 3697 #define TPS65917_NSLEEP_SMPS_ASSIGN 0x7 3698 #define TPS65917_NSLEEP_LDO_ASSIGN1 0x8 3699 #define TPS65917_NSLEEP_LDO_ASSIGN2 0x9 3700 #define TPS65917_ENABLE1_RES_ASSIGN 0xA 3701 #define TPS65917_ENABLE1_SMPS_ASSIGN 0xB 3702 #define TPS65917_ENABLE1_LDO_ASSIGN1 0xC 3703 #define TPS65917_ENABLE1_LDO_ASSIGN2 0xD 3704 #define TPS65917_ENABLE2_RES_ASSIGN 0xE 3705 #define TPS65917_ENABLE2_SMPS_ASSIGN 0xF 3706 #define TPS65917_ENABLE2_LDO_ASSIGN1 0x10 3707 #define TPS65917_ENABLE2_LDO_ASSIGN2 0x11 3708 #define TPS65917_REGEN2_CTRL 0x12 3709 #define TPS65917_REGEN3_CTRL 0x13 3710 3711 static inline int palmas_read(struct palmas *palmas, unsigned int base, 3712 unsigned int reg, unsigned int *val) 3713 { 3714 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 3715 int slave_id = PALMAS_BASE_TO_SLAVE(base); 3716 3717 return regmap_read(palmas->regmap[slave_id], addr, val); 3718 } 3719 3720 static inline int palmas_write(struct palmas *palmas, unsigned int base, 3721 unsigned int reg, unsigned int value) 3722 { 3723 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 3724 int slave_id = PALMAS_BASE_TO_SLAVE(base); 3725 3726 return regmap_write(palmas->regmap[slave_id], addr, value); 3727 } 3728 3729 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base, 3730 unsigned int reg, const void *val, size_t val_count) 3731 { 3732 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 3733 int slave_id = PALMAS_BASE_TO_SLAVE(base); 3734 3735 return regmap_bulk_write(palmas->regmap[slave_id], addr, 3736 val, val_count); 3737 } 3738 3739 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base, 3740 unsigned int reg, void *val, size_t val_count) 3741 { 3742 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 3743 int slave_id = PALMAS_BASE_TO_SLAVE(base); 3744 3745 return regmap_bulk_read(palmas->regmap[slave_id], addr, 3746 val, val_count); 3747 } 3748 3749 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base, 3750 unsigned int reg, unsigned int mask, unsigned int val) 3751 { 3752 unsigned int addr = PALMAS_BASE_TO_REG(base, reg); 3753 int slave_id = PALMAS_BASE_TO_SLAVE(base); 3754 3755 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val); 3756 } 3757 3758 static inline int palmas_irq_get_virq(struct palmas *palmas, int irq) 3759 { 3760 return regmap_irq_get_virq(palmas->irq_data, irq); 3761 } 3762 3763 3764 int palmas_ext_control_req_config(struct palmas *palmas, 3765 enum palmas_external_requestor_id ext_control_req_id, 3766 int ext_ctrl, bool enable); 3767 3768 #endif /* __LINUX_MFD_PALMAS_H */ 3769