1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Flora Fu, MediaTek 5 */ 6 7 #ifndef __MFD_MT6397_CORE_H__ 8 #define __MFD_MT6397_CORE_H__ 9 10 #include <linux/mutex.h> 11 #include <linux/notifier.h> 12 13 enum chip_id { 14 MT6323_CHIP_ID = 0x23, 15 MT6391_CHIP_ID = 0x91, 16 MT6397_CHIP_ID = 0x97, 17 }; 18 19 enum mt6397_irq_numbers { 20 MT6397_IRQ_SPKL_AB = 0, 21 MT6397_IRQ_SPKR_AB, 22 MT6397_IRQ_SPKL, 23 MT6397_IRQ_SPKR, 24 MT6397_IRQ_BAT_L, 25 MT6397_IRQ_BAT_H, 26 MT6397_IRQ_FG_BAT_L, 27 MT6397_IRQ_FG_BAT_H, 28 MT6397_IRQ_WATCHDOG, 29 MT6397_IRQ_PWRKEY, 30 MT6397_IRQ_THR_L, 31 MT6397_IRQ_THR_H, 32 MT6397_IRQ_VBATON_UNDET, 33 MT6397_IRQ_BVALID_DET, 34 MT6397_IRQ_CHRDET, 35 MT6397_IRQ_OV, 36 MT6397_IRQ_LDO, 37 MT6397_IRQ_HOMEKEY, 38 MT6397_IRQ_ACCDET, 39 MT6397_IRQ_AUDIO, 40 MT6397_IRQ_RTC, 41 MT6397_IRQ_PWRKEY_RSTB, 42 MT6397_IRQ_HDMI_SIFM, 43 MT6397_IRQ_HDMI_CEC, 44 MT6397_IRQ_VCA15, 45 MT6397_IRQ_VSRMCA15, 46 MT6397_IRQ_VCORE, 47 MT6397_IRQ_VGPU, 48 MT6397_IRQ_VIO18, 49 MT6397_IRQ_VPCA7, 50 MT6397_IRQ_VSRMCA7, 51 MT6397_IRQ_VDRM, 52 MT6397_IRQ_NR, 53 }; 54 55 struct mt6397_chip { 56 struct device *dev; 57 struct regmap *regmap; 58 struct notifier_block pm_nb; 59 int irq; 60 struct irq_domain *irq_domain; 61 struct mutex irqlock; 62 u16 wake_mask[2]; 63 u16 irq_masks_cur[2]; 64 u16 irq_masks_cache[2]; 65 u16 int_con[2]; 66 u16 int_status[2]; 67 u16 chip_id; 68 }; 69 70 int mt6397_irq_init(struct mt6397_chip *chip); 71 72 #endif /* __MFD_MT6397_CORE_H__ */ 73