1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022 AngeloGioacchino Del Regno <[email protected]> 4 */ 5 6 #ifndef __MFD_MT6331_CORE_H__ 7 #define __MFD_MT6331_CORE_H__ 8 9 enum mt6331_irq_status_numbers { 10 MT6331_IRQ_STATUS_PWRKEY = 0, 11 MT6331_IRQ_STATUS_HOMEKEY, 12 MT6331_IRQ_STATUS_CHRDET, 13 MT6331_IRQ_STATUS_THR_H, 14 MT6331_IRQ_STATUS_THR_L, 15 MT6331_IRQ_STATUS_BAT_H, 16 MT6331_IRQ_STATUS_BAT_L, 17 MT6331_IRQ_STATUS_RTC, 18 MT6331_IRQ_STATUS_AUDIO, 19 MT6331_IRQ_STATUS_MAD, 20 MT6331_IRQ_STATUS_ACCDET, 21 MT6331_IRQ_STATUS_ACCDET_EINT, 22 MT6331_IRQ_STATUS_ACCDET_NEGV = 12, 23 MT6331_IRQ_STATUS_VDVFS11_OC = 16, 24 MT6331_IRQ_STATUS_VDVFS12_OC, 25 MT6331_IRQ_STATUS_VDVFS13_OC, 26 MT6331_IRQ_STATUS_VDVFS14_OC, 27 MT6331_IRQ_STATUS_GPU_OC, 28 MT6331_IRQ_STATUS_VCORE1_OC, 29 MT6331_IRQ_STATUS_VCORE2_OC, 30 MT6331_IRQ_STATUS_VIO18_OC, 31 MT6331_IRQ_STATUS_LDO_OC, 32 MT6331_IRQ_STATUS_NR, 33 }; 34 35 #define MT6331_IRQ_CON0_BASE MT6331_IRQ_STATUS_PWRKEY 36 #define MT6331_IRQ_CON0_BITS (MT6331_IRQ_STATUS_ACCDET_NEGV + 1) 37 #define MT6331_IRQ_CON1_BASE MT6331_IRQ_STATUS_VDVFS11_OC 38 #define MT6331_IRQ_CON1_BITS (MT6331_IRQ_STATUS_LDO_OC - MT6331_IRQ_STATUS_VDFS11_OC + 1) 39 40 #endif /* __MFD_MT6331_CORE_H__ */ 41