1 /*
2  * max77693-private.h - Voltage regulator driver for the Maxim 77693
3  *
4  *  Copyright (C) 2012 Samsung Electrnoics
5  *  SangYoung Son <[email protected]>
6  *
7  * This program is not provided / owned by Maxim Integrated Products.
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
22  */
23 
24 #ifndef __LINUX_MFD_MAX77693_PRIV_H
25 #define __LINUX_MFD_MAX77693_PRIV_H
26 
27 #include <linux/i2c.h>
28 
29 #define MAX77693_NUM_IRQ_MUIC_REGS	3
30 #define MAX77693_REG_INVALID		(0xff)
31 
32 /* Slave addr = 0xCC: PMIC, Charger, Flash LED */
33 enum max77693_pmic_reg {
34 	MAX77693_LED_REG_IFLASH1			= 0x00,
35 	MAX77693_LED_REG_IFLASH2			= 0x01,
36 	MAX77693_LED_REG_ITORCH				= 0x02,
37 	MAX77693_LED_REG_ITORCHTIMER			= 0x03,
38 	MAX77693_LED_REG_FLASH_TIMER			= 0x04,
39 	MAX77693_LED_REG_FLASH_EN			= 0x05,
40 	MAX77693_LED_REG_MAX_FLASH1			= 0x06,
41 	MAX77693_LED_REG_MAX_FLASH2			= 0x07,
42 	MAX77693_LED_REG_MAX_FLASH3			= 0x08,
43 	MAX77693_LED_REG_MAX_FLASH4			= 0x09,
44 	MAX77693_LED_REG_VOUT_CNTL			= 0x0A,
45 	MAX77693_LED_REG_VOUT_FLASH1			= 0x0B,
46 	MAX77693_LED_REG_VOUT_FLASH2			= 0x0C,
47 	MAX77693_LED_REG_FLASH_INT			= 0x0E,
48 	MAX77693_LED_REG_FLASH_INT_MASK			= 0x0F,
49 	MAX77693_LED_REG_FLASH_INT_STATUS		= 0x10,
50 
51 	MAX77693_PMIC_REG_PMIC_ID1			= 0x20,
52 	MAX77693_PMIC_REG_PMIC_ID2			= 0x21,
53 	MAX77693_PMIC_REG_INTSRC			= 0x22,
54 	MAX77693_PMIC_REG_INTSRC_MASK			= 0x23,
55 	MAX77693_PMIC_REG_TOPSYS_INT			= 0x24,
56 	MAX77693_PMIC_REG_TOPSYS_INT_MASK		= 0x26,
57 	MAX77693_PMIC_REG_TOPSYS_STAT			= 0x28,
58 	MAX77693_PMIC_REG_MAINCTRL1			= 0x2A,
59 	MAX77693_PMIC_REG_LSCNFG			= 0x2B,
60 
61 	MAX77693_CHG_REG_CHG_INT			= 0xB0,
62 	MAX77693_CHG_REG_CHG_INT_MASK			= 0xB1,
63 	MAX77693_CHG_REG_CHG_INT_OK			= 0xB2,
64 	MAX77693_CHG_REG_CHG_DETAILS_00			= 0xB3,
65 	MAX77693_CHG_REG_CHG_DETAILS_01			= 0xB4,
66 	MAX77693_CHG_REG_CHG_DETAILS_02			= 0xB5,
67 	MAX77693_CHG_REG_CHG_DETAILS_03			= 0xB6,
68 	MAX77693_CHG_REG_CHG_CNFG_00			= 0xB7,
69 	MAX77693_CHG_REG_CHG_CNFG_01			= 0xB8,
70 	MAX77693_CHG_REG_CHG_CNFG_02			= 0xB9,
71 	MAX77693_CHG_REG_CHG_CNFG_03			= 0xBA,
72 	MAX77693_CHG_REG_CHG_CNFG_04			= 0xBB,
73 	MAX77693_CHG_REG_CHG_CNFG_05			= 0xBC,
74 	MAX77693_CHG_REG_CHG_CNFG_06			= 0xBD,
75 	MAX77693_CHG_REG_CHG_CNFG_07			= 0xBE,
76 	MAX77693_CHG_REG_CHG_CNFG_08			= 0xBF,
77 	MAX77693_CHG_REG_CHG_CNFG_09			= 0xC0,
78 	MAX77693_CHG_REG_CHG_CNFG_10			= 0xC1,
79 	MAX77693_CHG_REG_CHG_CNFG_11			= 0xC2,
80 	MAX77693_CHG_REG_CHG_CNFG_12			= 0xC3,
81 	MAX77693_CHG_REG_CHG_CNFG_13			= 0xC4,
82 	MAX77693_CHG_REG_CHG_CNFG_14			= 0xC5,
83 	MAX77693_CHG_REG_SAFEOUT_CTRL			= 0xC6,
84 
85 	MAX77693_PMIC_REG_END,
86 };
87 
88 /* MAX77693 CHG_CNFG_00 register */
89 #define CHG_CNFG_00_CHG_MASK		0x1
90 #define CHG_CNFG_00_BUCK_MASK		0x4
91 
92 /* MAX77693 CHG_CNFG_09 Register */
93 #define CHG_CNFG_09_CHGIN_ILIM_MASK	0x7F
94 
95 /* MAX77693 CHG_CTRL Register */
96 #define SAFEOUT_CTRL_SAFEOUT1_MASK	0x3
97 #define SAFEOUT_CTRL_SAFEOUT2_MASK	0xC
98 #define SAFEOUT_CTRL_ENSAFEOUT1_MASK	0x40
99 #define SAFEOUT_CTRL_ENSAFEOUT2_MASK	0x80
100 
101 /* Slave addr = 0x4A: MUIC */
102 enum max77693_muic_reg {
103 	MAX77693_MUIC_REG_ID		= 0x00,
104 	MAX77693_MUIC_REG_INT1		= 0x01,
105 	MAX77693_MUIC_REG_INT2		= 0x02,
106 	MAX77693_MUIC_REG_INT3		= 0x03,
107 	MAX77693_MUIC_REG_STATUS1	= 0x04,
108 	MAX77693_MUIC_REG_STATUS2	= 0x05,
109 	MAX77693_MUIC_REG_STATUS3	= 0x06,
110 	MAX77693_MUIC_REG_INTMASK1	= 0x07,
111 	MAX77693_MUIC_REG_INTMASK2	= 0x08,
112 	MAX77693_MUIC_REG_INTMASK3	= 0x09,
113 	MAX77693_MUIC_REG_CDETCTRL1	= 0x0A,
114 	MAX77693_MUIC_REG_CDETCTRL2	= 0x0B,
115 	MAX77693_MUIC_REG_CTRL1		= 0x0C,
116 	MAX77693_MUIC_REG_CTRL2		= 0x0D,
117 	MAX77693_MUIC_REG_CTRL3		= 0x0E,
118 
119 	MAX77693_MUIC_REG_END,
120 };
121 
122 /* MAX77693 INTMASK1~2 Register */
123 #define INTMASK1_ADC1K_SHIFT		3
124 #define INTMASK1_ADCERR_SHIFT		2
125 #define INTMASK1_ADCLOW_SHIFT		1
126 #define INTMASK1_ADC_SHIFT		0
127 #define INTMASK1_ADC1K_MASK		(1 << INTMASK1_ADC1K_SHIFT)
128 #define INTMASK1_ADCERR_MASK		(1 << INTMASK1_ADCERR_SHIFT)
129 #define INTMASK1_ADCLOW_MASK		(1 << INTMASK1_ADCLOW_SHIFT)
130 #define INTMASK1_ADC_MASK		(1 << INTMASK1_ADC_SHIFT)
131 
132 #define INTMASK2_VIDRM_SHIFT		5
133 #define INTMASK2_VBVOLT_SHIFT		4
134 #define INTMASK2_DXOVP_SHIFT		3
135 #define INTMASK2_DCDTMR_SHIFT		2
136 #define INTMASK2_CHGDETRUN_SHIFT	1
137 #define INTMASK2_CHGTYP_SHIFT		0
138 #define INTMASK2_VIDRM_MASK		(1 << INTMASK2_VIDRM_SHIFT)
139 #define INTMASK2_VBVOLT_MASK		(1 << INTMASK2_VBVOLT_SHIFT)
140 #define INTMASK2_DXOVP_MASK		(1 << INTMASK2_DXOVP_SHIFT)
141 #define INTMASK2_DCDTMR_MASK		(1 << INTMASK2_DCDTMR_SHIFT)
142 #define INTMASK2_CHGDETRUN_MASK		(1 << INTMASK2_CHGDETRUN_SHIFT)
143 #define INTMASK2_CHGTYP_MASK		(1 << INTMASK2_CHGTYP_SHIFT)
144 
145 /* MAX77693 MUIC - STATUS1~3 Register */
146 #define STATUS1_ADC_SHIFT		(0)
147 #define STATUS1_ADCLOW_SHIFT		(5)
148 #define STATUS1_ADCERR_SHIFT		(6)
149 #define STATUS1_ADC1K_SHIFT		(7)
150 #define STATUS1_ADC_MASK		(0x1f << STATUS1_ADC_SHIFT)
151 #define STATUS1_ADCLOW_MASK		(0x1 << STATUS1_ADCLOW_SHIFT)
152 #define STATUS1_ADCERR_MASK		(0x1 << STATUS1_ADCERR_SHIFT)
153 #define STATUS1_ADC1K_MASK		(0x1 << STATUS1_ADC1K_SHIFT)
154 
155 #define STATUS2_CHGTYP_SHIFT		(0)
156 #define STATUS2_CHGDETRUN_SHIFT		(3)
157 #define STATUS2_DCDTMR_SHIFT		(4)
158 #define STATUS2_DXOVP_SHIFT		(5)
159 #define STATUS2_VBVOLT_SHIFT		(6)
160 #define STATUS2_VIDRM_SHIFT		(7)
161 #define STATUS2_CHGTYP_MASK		(0x7 << STATUS2_CHGTYP_SHIFT)
162 #define STATUS2_CHGDETRUN_MASK		(0x1 << STATUS2_CHGDETRUN_SHIFT)
163 #define STATUS2_DCDTMR_MASK		(0x1 << STATUS2_DCDTMR_SHIFT)
164 #define STATUS2_DXOVP_MASK		(0x1 << STATUS2_DXOVP_SHIFT)
165 #define STATUS2_VBVOLT_MASK		(0x1 << STATUS2_VBVOLT_SHIFT)
166 #define STATUS2_VIDRM_MASK		(0x1 << STATUS2_VIDRM_SHIFT)
167 
168 #define STATUS3_OVP_SHIFT		(2)
169 #define STATUS3_OVP_MASK		(0x1 << STATUS3_OVP_SHIFT)
170 
171 /* MAX77693 CDETCTRL1~2 register */
172 #define CDETCTRL1_CHGDETEN_SHIFT	(0)
173 #define CDETCTRL1_CHGTYPMAN_SHIFT	(1)
174 #define CDETCTRL1_DCDEN_SHIFT		(2)
175 #define CDETCTRL1_DCD2SCT_SHIFT		(3)
176 #define CDETCTRL1_CDDELAY_SHIFT		(4)
177 #define CDETCTRL1_DCDCPL_SHIFT		(5)
178 #define CDETCTRL1_CDPDET_SHIFT		(7)
179 #define CDETCTRL1_CHGDETEN_MASK		(0x1 << CDETCTRL1_CHGDETEN_SHIFT)
180 #define CDETCTRL1_CHGTYPMAN_MASK	(0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
181 #define CDETCTRL1_DCDEN_MASK		(0x1 << CDETCTRL1_DCDEN_SHIFT)
182 #define CDETCTRL1_DCD2SCT_MASK		(0x1 << CDETCTRL1_DCD2SCT_SHIFT)
183 #define CDETCTRL1_CDDELAY_MASK		(0x1 << CDETCTRL1_CDDELAY_SHIFT)
184 #define CDETCTRL1_DCDCPL_MASK		(0x1 << CDETCTRL1_DCDCPL_SHIFT)
185 #define CDETCTRL1_CDPDET_MASK		(0x1 << CDETCTRL1_CDPDET_SHIFT)
186 
187 #define CDETCTRL2_VIDRMEN_SHIFT		(1)
188 #define CDETCTRL2_DXOVPEN_SHIFT		(3)
189 #define CDETCTRL2_VIDRMEN_MASK		(0x1 << CDETCTRL2_VIDRMEN_SHIFT)
190 #define CDETCTRL2_DXOVPEN_MASK		(0x1 << CDETCTRL2_DXOVPEN_SHIFT)
191 
192 /* MAX77693 MUIC - CONTROL1~3 register */
193 #define COMN1SW_SHIFT			(0)
194 #define COMP2SW_SHIFT			(3)
195 #define COMN1SW_MASK			(0x7 << COMN1SW_SHIFT)
196 #define COMP2SW_MASK			(0x7 << COMP2SW_SHIFT)
197 #define COMP_SW_MASK			(COMP2SW_MASK | COMN1SW_MASK)
198 #define CONTROL1_SW_USB			((1 << COMP2SW_SHIFT) \
199 						| (1 << COMN1SW_SHIFT))
200 #define CONTROL1_SW_AUDIO		((2 << COMP2SW_SHIFT) \
201 						| (2 << COMN1SW_SHIFT))
202 #define CONTROL1_SW_UART		((3 << COMP2SW_SHIFT) \
203 						| (3 << COMN1SW_SHIFT))
204 #define CONTROL1_SW_OPEN		((0 << COMP2SW_SHIFT) \
205 						| (0 << COMN1SW_SHIFT))
206 
207 #define CONTROL2_LOWPWR_SHIFT		(0)
208 #define CONTROL2_ADCEN_SHIFT		(1)
209 #define CONTROL2_CPEN_SHIFT		(2)
210 #define CONTROL2_SFOUTASRT_SHIFT	(3)
211 #define CONTROL2_SFOUTORD_SHIFT		(4)
212 #define CONTROL2_ACCDET_SHIFT		(5)
213 #define CONTROL2_USBCPINT_SHIFT		(6)
214 #define CONTROL2_RCPS_SHIFT		(7)
215 #define CONTROL2_LOWPWR_MASK		(0x1 << CONTROL2_LOWPWR_SHIFT)
216 #define CONTROL2_ADCEN_MASK		(0x1 << CONTROL2_ADCEN_SHIFT)
217 #define CONTROL2_CPEN_MASK		(0x1 << CONTROL2_CPEN_SHIFT)
218 #define CONTROL2_SFOUTASRT_MASK		(0x1 << CONTROL2_SFOUTASRT_SHIFT)
219 #define CONTROL2_SFOUTORD_MASK		(0x1 << CONTROL2_SFOUTORD_SHIFT)
220 #define CONTROL2_ACCDET_MASK		(0x1 << CONTROL2_ACCDET_SHIFT)
221 #define CONTROL2_USBCPINT_MASK		(0x1 << CONTROL2_USBCPINT_SHIFT)
222 #define CONTROL2_RCPS_MASK		(0x1 << CONTROL2_RCPS_SHIFT)
223 
224 #define CONTROL3_JIGSET_SHIFT		(0)
225 #define CONTROL3_BTLDSET_SHIFT		(2)
226 #define CONTROL3_ADCDBSET_SHIFT		(4)
227 #define CONTROL3_JIGSET_MASK		(0x3 << CONTROL3_JIGSET_SHIFT)
228 #define CONTROL3_BTLDSET_MASK		(0x3 << CONTROL3_BTLDSET_SHIFT)
229 #define CONTROL3_ADCDBSET_MASK		(0x3 << CONTROL3_ADCDBSET_SHIFT)
230 
231 /* Slave addr = 0x90: Haptic */
232 enum max77693_haptic_reg {
233 	MAX77693_HAPTIC_REG_STATUS		= 0x00,
234 	MAX77693_HAPTIC_REG_CONFIG1		= 0x01,
235 	MAX77693_HAPTIC_REG_CONFIG2		= 0x02,
236 	MAX77693_HAPTIC_REG_CONFIG_CHNL		= 0x03,
237 	MAX77693_HAPTIC_REG_CONFG_CYC1		= 0x04,
238 	MAX77693_HAPTIC_REG_CONFG_CYC2		= 0x05,
239 	MAX77693_HAPTIC_REG_CONFIG_PER1		= 0x06,
240 	MAX77693_HAPTIC_REG_CONFIG_PER2		= 0x07,
241 	MAX77693_HAPTIC_REG_CONFIG_PER3		= 0x08,
242 	MAX77693_HAPTIC_REG_CONFIG_PER4		= 0x09,
243 	MAX77693_HAPTIC_REG_CONFIG_DUTY1	= 0x0A,
244 	MAX77693_HAPTIC_REG_CONFIG_DUTY2	= 0x0B,
245 	MAX77693_HAPTIC_REG_CONFIG_PWM1		= 0x0C,
246 	MAX77693_HAPTIC_REG_CONFIG_PWM2		= 0x0D,
247 	MAX77693_HAPTIC_REG_CONFIG_PWM3		= 0x0E,
248 	MAX77693_HAPTIC_REG_CONFIG_PWM4		= 0x0F,
249 	MAX77693_HAPTIC_REG_REV			= 0x10,
250 
251 	MAX77693_HAPTIC_REG_END,
252 };
253 
254 enum max77693_irq_source {
255 	LED_INT = 0,
256 	TOPSYS_INT,
257 	CHG_INT,
258 	MUIC_INT1,
259 	MUIC_INT2,
260 	MUIC_INT3,
261 
262 	MAX77693_IRQ_GROUP_NR,
263 };
264 
265 #define LED_IRQ_FLED2_OPEN		BIT(0)
266 #define LED_IRQ_FLED2_SHORT		BIT(1)
267 #define LED_IRQ_FLED1_OPEN		BIT(2)
268 #define LED_IRQ_FLED1_SHORT		BIT(3)
269 #define LED_IRQ_MAX_FLASH		BIT(4)
270 
271 #define TOPSYS_IRQ_T120C_INT		BIT(0)
272 #define TOPSYS_IRQ_T140C_INT		BIT(1)
273 #define TOPSYS_IRQ_LOWSYS_INT		BIT(3)
274 
275 #define CHG_IRQ_BYP_I			BIT(0)
276 #define CHG_IRQ_THM_I			BIT(2)
277 #define CHG_IRQ_BAT_I			BIT(3)
278 #define CHG_IRQ_CHG_I			BIT(4)
279 #define CHG_IRQ_CHGIN_I			BIT(6)
280 
281 #define MUIC_IRQ_INT1_ADC		BIT(0)
282 #define MUIC_IRQ_INT1_ADC_LOW		BIT(1)
283 #define MUIC_IRQ_INT1_ADC_ERR		BIT(2)
284 #define MUIC_IRQ_INT1_ADC1K		BIT(3)
285 
286 #define MUIC_IRQ_INT2_CHGTYP		BIT(0)
287 #define MUIC_IRQ_INT2_CHGDETREUN	BIT(1)
288 #define MUIC_IRQ_INT2_DCDTMR		BIT(2)
289 #define MUIC_IRQ_INT2_DXOVP		BIT(3)
290 #define MUIC_IRQ_INT2_VBVOLT		BIT(4)
291 #define MUIC_IRQ_INT2_VIDRM		BIT(5)
292 
293 #define MUIC_IRQ_INT3_EOC		BIT(0)
294 #define MUIC_IRQ_INT3_CGMBC		BIT(1)
295 #define MUIC_IRQ_INT3_OVP		BIT(2)
296 #define MUIC_IRQ_INT3_MBCCHG_ERR	BIT(3)
297 #define MUIC_IRQ_INT3_CHG_ENABLED	BIT(4)
298 #define MUIC_IRQ_INT3_BAT_DET		BIT(5)
299 
300 enum max77693_irq {
301 	/* PMIC - FLASH */
302 	MAX77693_LED_IRQ_FLED2_OPEN,
303 	MAX77693_LED_IRQ_FLED2_SHORT,
304 	MAX77693_LED_IRQ_FLED1_OPEN,
305 	MAX77693_LED_IRQ_FLED1_SHORT,
306 	MAX77693_LED_IRQ_MAX_FLASH,
307 
308 	/* PMIC - TOPSYS */
309 	MAX77693_TOPSYS_IRQ_T120C_INT,
310 	MAX77693_TOPSYS_IRQ_T140C_INT,
311 	MAX77693_TOPSYS_IRQ_LOWSYS_INT,
312 
313 	/* PMIC - Charger */
314 	MAX77693_CHG_IRQ_BYP_I,
315 	MAX77693_CHG_IRQ_THM_I,
316 	MAX77693_CHG_IRQ_BAT_I,
317 	MAX77693_CHG_IRQ_CHG_I,
318 	MAX77693_CHG_IRQ_CHGIN_I,
319 
320 	MAX77693_IRQ_NR,
321 };
322 
323 enum max77693_irq_muic {
324 	/* MUIC INT1 */
325 	MAX77693_MUIC_IRQ_INT1_ADC,
326 	MAX77693_MUIC_IRQ_INT1_ADC_LOW,
327 	MAX77693_MUIC_IRQ_INT1_ADC_ERR,
328 	MAX77693_MUIC_IRQ_INT1_ADC1K,
329 
330 	/* MUIC INT2 */
331 	MAX77693_MUIC_IRQ_INT2_CHGTYP,
332 	MAX77693_MUIC_IRQ_INT2_CHGDETREUN,
333 	MAX77693_MUIC_IRQ_INT2_DCDTMR,
334 	MAX77693_MUIC_IRQ_INT2_DXOVP,
335 	MAX77693_MUIC_IRQ_INT2_VBVOLT,
336 	MAX77693_MUIC_IRQ_INT2_VIDRM,
337 
338 	/* MUIC INT3 */
339 	MAX77693_MUIC_IRQ_INT3_EOC,
340 	MAX77693_MUIC_IRQ_INT3_CGMBC,
341 	MAX77693_MUIC_IRQ_INT3_OVP,
342 	MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR,
343 	MAX77693_MUIC_IRQ_INT3_CHG_ENABLED,
344 	MAX77693_MUIC_IRQ_INT3_BAT_DET,
345 
346 	MAX77693_MUIC_IRQ_NR,
347 };
348 
349 struct max77693_dev {
350 	struct device *dev;
351 	struct i2c_client *i2c;		/* 0xCC , PMIC, Charger, Flash LED */
352 	struct i2c_client *muic;	/* 0x4A , MUIC */
353 	struct i2c_client *haptic;	/* 0x90 , Haptic */
354 
355 	int type;
356 
357 	struct regmap *regmap;
358 	struct regmap *regmap_muic;
359 	struct regmap *regmap_haptic;
360 
361 	struct regmap_irq_chip_data *irq_data_led;
362 	struct regmap_irq_chip_data *irq_data_topsys;
363 	struct regmap_irq_chip_data *irq_data_charger;
364 	struct regmap_irq_chip_data *irq_data_muic;
365 
366 	int irq;
367 	int irq_gpio;
368 	struct mutex irqlock;
369 	int irq_masks_cur[MAX77693_IRQ_GROUP_NR];
370 	int irq_masks_cache[MAX77693_IRQ_GROUP_NR];
371 };
372 
373 enum max77693_types {
374 	TYPE_MAX77693,
375 };
376 
377 extern int max77693_irq_init(struct max77693_dev *max77686);
378 extern void max77693_irq_exit(struct max77693_dev *max77686);
379 extern int max77693_irq_resume(struct max77693_dev *max77686);
380 
381 #endif /*  __LINUX_MFD_MAX77693_PRIV_H */
382