1*25f1ca31SMika Westerberg /* SPDX-License-Identifier: GPL-2.0 */
2*25f1ca31SMika Westerberg #ifndef MFD_INTEL_PMC_BXT_H
3*25f1ca31SMika Westerberg #define MFD_INTEL_PMC_BXT_H
4*25f1ca31SMika Westerberg
5*25f1ca31SMika Westerberg /* GCR reg offsets from GCR base */
6*25f1ca31SMika Westerberg #define PMC_GCR_PMC_CFG_REG 0x08
7*25f1ca31SMika Westerberg #define PMC_GCR_TELEM_DEEP_S0IX_REG 0x78
8*25f1ca31SMika Westerberg #define PMC_GCR_TELEM_SHLW_S0IX_REG 0x80
9*25f1ca31SMika Westerberg
10*25f1ca31SMika Westerberg /* PMC_CFG_REG bit masks */
11*25f1ca31SMika Westerberg #define PMC_CFG_NO_REBOOT_EN BIT(4)
12*25f1ca31SMika Westerberg
13*25f1ca31SMika Westerberg /**
14*25f1ca31SMika Westerberg * struct intel_pmc_dev - Intel PMC device structure
15*25f1ca31SMika Westerberg * @dev: Pointer to the parent PMC device
16*25f1ca31SMika Westerberg * @scu: Pointer to the SCU IPC device data structure
17*25f1ca31SMika Westerberg * @gcr_mem_base: Virtual base address of GCR (Global Configuration Registers)
18*25f1ca31SMika Westerberg * @gcr_lock: Lock used to serialize access to GCR registers
19*25f1ca31SMika Westerberg * @telem_base: Pointer to telemetry SSRAM base resource or %NULL if not
20*25f1ca31SMika Westerberg * available
21*25f1ca31SMika Westerberg */
22*25f1ca31SMika Westerberg struct intel_pmc_dev {
23*25f1ca31SMika Westerberg struct device *dev;
24*25f1ca31SMika Westerberg struct intel_scu_ipc_dev *scu;
25*25f1ca31SMika Westerberg void __iomem *gcr_mem_base;
26*25f1ca31SMika Westerberg spinlock_t gcr_lock;
27*25f1ca31SMika Westerberg struct resource *telem_base;
28*25f1ca31SMika Westerberg };
29*25f1ca31SMika Westerberg
30*25f1ca31SMika Westerberg #if IS_ENABLED(CONFIG_MFD_INTEL_PMC_BXT)
31*25f1ca31SMika Westerberg int intel_pmc_gcr_read64(struct intel_pmc_dev *pmc, u32 offset, u64 *data);
32*25f1ca31SMika Westerberg int intel_pmc_gcr_update(struct intel_pmc_dev *pmc, u32 offset, u32 mask, u32 val);
33*25f1ca31SMika Westerberg int intel_pmc_s0ix_counter_read(struct intel_pmc_dev *pmc, u64 *data);
34*25f1ca31SMika Westerberg #else
intel_pmc_gcr_read64(struct intel_pmc_dev * pmc,u32 offset,u64 * data)35*25f1ca31SMika Westerberg static inline int intel_pmc_gcr_read64(struct intel_pmc_dev *pmc, u32 offset,
36*25f1ca31SMika Westerberg u64 *data)
37*25f1ca31SMika Westerberg {
38*25f1ca31SMika Westerberg return -ENOTSUPP;
39*25f1ca31SMika Westerberg }
40*25f1ca31SMika Westerberg
intel_pmc_gcr_update(struct intel_pmc_dev * pmc,u32 offset,u32 mask,u32 val)41*25f1ca31SMika Westerberg static inline int intel_pmc_gcr_update(struct intel_pmc_dev *pmc, u32 offset,
42*25f1ca31SMika Westerberg u32 mask, u32 val)
43*25f1ca31SMika Westerberg {
44*25f1ca31SMika Westerberg return -ENOTSUPP;
45*25f1ca31SMika Westerberg }
46*25f1ca31SMika Westerberg
intel_pmc_s0ix_counter_read(struct intel_pmc_dev * pmc,u64 * data)47*25f1ca31SMika Westerberg static inline int intel_pmc_s0ix_counter_read(struct intel_pmc_dev *pmc, u64 *data)
48*25f1ca31SMika Westerberg {
49*25f1ca31SMika Westerberg return -ENOTSUPP;
50*25f1ca31SMika Westerberg }
51*25f1ca31SMika Westerberg #endif
52*25f1ca31SMika Westerberg
53*25f1ca31SMika Westerberg #endif /* MFD_INTEL_PMC_BXT_H */
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