1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Intel MAX 10 Board Management Controller chip. 4 * 5 * Copyright (C) 2018-2020 Intel Corporation, Inc. 6 */ 7 #ifndef __MFD_INTEL_M10_BMC_H 8 #define __MFD_INTEL_M10_BMC_H 9 10 #include <linux/regmap.h> 11 12 #define M10BMC_LEGACY_SYS_BASE 0x300400 13 #define M10BMC_SYS_BASE 0x300800 14 #define M10BMC_MEM_END 0x200000fc 15 16 /* Register offset of system registers */ 17 #define NIOS2_FW_VERSION 0x0 18 #define M10BMC_MAC_LOW 0x10 19 #define M10BMC_MAC_BYTE4 GENMASK(7, 0) 20 #define M10BMC_MAC_BYTE3 GENMASK(15, 8) 21 #define M10BMC_MAC_BYTE2 GENMASK(23, 16) 22 #define M10BMC_MAC_BYTE1 GENMASK(31, 24) 23 #define M10BMC_MAC_HIGH 0x14 24 #define M10BMC_MAC_BYTE6 GENMASK(7, 0) 25 #define M10BMC_MAC_BYTE5 GENMASK(15, 8) 26 #define M10BMC_MAC_COUNT GENMASK(23, 16) 27 #define M10BMC_TEST_REG 0x3c 28 #define M10BMC_BUILD_VER 0x68 29 #define M10BMC_VER_MAJOR_MSK GENMASK(23, 16) 30 #define M10BMC_VER_PCB_INFO_MSK GENMASK(31, 24) 31 #define M10BMC_VER_LEGACY_INVALID 0xffffffff 32 33 /** 34 * struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure 35 * @dev: this device 36 * @regmap: the regmap used to access registers by m10bmc itself 37 */ 38 struct intel_m10bmc { 39 struct device *dev; 40 struct regmap *regmap; 41 }; 42 43 /* 44 * register access helper functions. 45 * 46 * m10bmc_raw_read - read m10bmc register per addr 47 * m10bmc_sys_read - read m10bmc system register per offset 48 */ 49 static inline int 50 m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr, 51 unsigned int *val) 52 { 53 int ret; 54 55 ret = regmap_read(m10bmc->regmap, addr, val); 56 if (ret) 57 dev_err(m10bmc->dev, "fail to read raw reg %x: %d\n", 58 addr, ret); 59 60 return ret; 61 } 62 63 /* 64 * The base of the system registers could be configured by HW developers, and 65 * in HW SPEC, the base is not added to the addresses of the system registers. 66 * 67 * This macro helps to simplify the accessing of the system registers. And if 68 * the base is reconfigured in HW, SW developers could simply change the 69 * M10BMC_SYS_BASE accordingly. 70 */ 71 #define m10bmc_sys_read(m10bmc, offset, val) \ 72 m10bmc_raw_read(m10bmc, M10BMC_SYS_BASE + (offset), val) 73 74 #endif /* __MFD_INTEL_M10_BMC_H */ 75