1 /* 2 * Marvell MBUS common definitions. 3 * 4 * Copyright (C) 2008 Marvell Semiconductor 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #ifndef __LINUX_MBUS_H 12 #define __LINUX_MBUS_H 13 14 struct mbus_dram_target_info 15 { 16 /* 17 * The 4-bit MBUS target ID of the DRAM controller. 18 */ 19 u8 mbus_dram_target_id; 20 21 /* 22 * The base address, size, and MBUS attribute ID for each 23 * of the possible DRAM chip selects. Peripherals are 24 * required to support at least 4 decode windows. 25 */ 26 int num_cs; 27 struct mbus_dram_window { 28 u8 cs_index; 29 u8 mbus_attr; 30 u32 base; 31 u32 size; 32 } cs[4]; 33 }; 34 35 /* Flags for PCI/PCIe address decoding regions */ 36 #define MVEBU_MBUS_PCI_IO 0x1 37 #define MVEBU_MBUS_PCI_MEM 0x2 38 #define MVEBU_MBUS_PCI_WA 0x3 39 40 /* 41 * Magic value that explicits that we don't need a remapping-capable 42 * address decoding window. 43 */ 44 #define MVEBU_MBUS_NO_REMAP (0xffffffff) 45 46 /* 47 * The Marvell mbus is to be found only on SOCs from the Orion family 48 * at the moment. Provide a dummy stub for other architectures. 49 */ 50 #ifdef CONFIG_PLAT_ORION 51 extern const struct mbus_dram_target_info *mv_mbus_dram_info(void); 52 #else 53 static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void) 54 { 55 return NULL; 56 } 57 #endif 58 59 int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base, 60 size_t size, phys_addr_t remap, 61 unsigned int flags); 62 int mvebu_mbus_add_window(const char *devname, phys_addr_t base, 63 size_t size); 64 int mvebu_mbus_del_window(phys_addr_t base, size_t size); 65 int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base, 66 size_t mbus_size, phys_addr_t sdram_phys_base, 67 size_t sdram_size); 68 69 #endif /* __LINUX_MBUS_H */ 70