1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_IRQ_H 3 #define _LINUX_IRQ_H 4 5 /* 6 * Please do not include this file in generic code. There is currently 7 * no requirement for any architecture to implement anything held 8 * within this file. 9 * 10 * Thanks. --rmk 11 */ 12 13 #include <linux/cache.h> 14 #include <linux/spinlock.h> 15 #include <linux/cpumask.h> 16 #include <linux/irqhandler.h> 17 #include <linux/irqreturn.h> 18 #include <linux/irqnr.h> 19 #include <linux/topology.h> 20 #include <linux/io.h> 21 #include <linux/slab.h> 22 23 #include <asm/irq.h> 24 #include <asm/ptrace.h> 25 #include <asm/irq_regs.h> 26 27 struct seq_file; 28 struct module; 29 struct msi_msg; 30 struct irq_affinity_desc; 31 enum irqchip_irq_state; 32 33 /* 34 * IRQ line status. 35 * 36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h 37 * 38 * IRQ_TYPE_NONE - default, unspecified type 39 * IRQ_TYPE_EDGE_RISING - rising edge triggered 40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered 41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 42 * IRQ_TYPE_LEVEL_HIGH - high level triggered 43 * IRQ_TYPE_LEVEL_LOW - low level triggered 44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 45 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits 46 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type 47 * to setup the HW to a sane default (used 48 * by irqdomain map() callbacks to synchronize 49 * the HW state and SW flags for a newly 50 * allocated descriptor). 51 * 52 * IRQ_TYPE_PROBE - Special flag for probing in progress 53 * 54 * Bits which can be modified via irq_set/clear/modify_status_flags() 55 * IRQ_LEVEL - Interrupt is level type. Will be also 56 * updated in the code when the above trigger 57 * bits are modified via irq_set_irq_type() 58 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect 59 * it from affinity setting 60 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing 61 * IRQ_NOREQUEST - Interrupt cannot be requested via 62 * request_irq() 63 * IRQ_NOTHREAD - Interrupt cannot be threaded 64 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in 65 * request/setup_irq() 66 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) 67 * IRQ_NESTED_THREAD - Interrupt nests into another thread 68 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable 69 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude 70 * it from the spurious interrupt detection 71 * mechanism and from core side polling. 72 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable 73 * IRQ_HIDDEN - Don't show up in /proc/interrupts 74 * IRQ_NO_DEBUG - Exclude from note_interrupt() debugging 75 */ 76 enum { 77 IRQ_TYPE_NONE = 0x00000000, 78 IRQ_TYPE_EDGE_RISING = 0x00000001, 79 IRQ_TYPE_EDGE_FALLING = 0x00000002, 80 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), 81 IRQ_TYPE_LEVEL_HIGH = 0x00000004, 82 IRQ_TYPE_LEVEL_LOW = 0x00000008, 83 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), 84 IRQ_TYPE_SENSE_MASK = 0x0000000f, 85 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, 86 87 IRQ_TYPE_PROBE = 0x00000010, 88 89 IRQ_LEVEL = (1 << 8), 90 IRQ_PER_CPU = (1 << 9), 91 IRQ_NOPROBE = (1 << 10), 92 IRQ_NOREQUEST = (1 << 11), 93 IRQ_NOAUTOEN = (1 << 12), 94 IRQ_NO_BALANCING = (1 << 13), 95 IRQ_NESTED_THREAD = (1 << 15), 96 IRQ_NOTHREAD = (1 << 16), 97 IRQ_PER_CPU_DEVID = (1 << 17), 98 IRQ_IS_POLLED = (1 << 18), 99 IRQ_DISABLE_UNLAZY = (1 << 19), 100 IRQ_HIDDEN = (1 << 20), 101 IRQ_NO_DEBUG = (1 << 21), 102 }; 103 104 #define IRQF_MODIFY_MASK \ 105 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ 106 IRQ_NOAUTOEN | IRQ_LEVEL | IRQ_NO_BALANCING | \ 107 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ 108 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_HIDDEN) 109 110 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 111 112 /* 113 * Return value for chip->irq_set_affinity() 114 * 115 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity 116 * IRQ_SET_MASK_NOCOPY - OK, chip did update irq_common_data.affinity 117 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to 118 * support stacked irqchips, which indicates skipping 119 * all descendant irqchips. 120 */ 121 enum { 122 IRQ_SET_MASK_OK = 0, 123 IRQ_SET_MASK_OK_NOCOPY, 124 IRQ_SET_MASK_OK_DONE, 125 }; 126 127 struct msi_desc; 128 struct irq_domain; 129 130 /** 131 * struct irq_common_data - per irq data shared by all irqchips 132 * @state_use_accessors: status information for irq chip functions. 133 * Use accessor functions to deal with it 134 * @node: node index useful for balancing 135 * @handler_data: per-IRQ data for the irq_chip methods 136 * @affinity: IRQ affinity on SMP. If this is an IPI 137 * related irq, then this is the mask of the 138 * CPUs to which an IPI can be sent. 139 * @effective_affinity: The effective IRQ affinity on SMP as some irq 140 * chips do not allow multi CPU destinations. 141 * A subset of @affinity. 142 * @msi_desc: MSI descriptor 143 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional. 144 */ 145 struct irq_common_data { 146 unsigned int __private state_use_accessors; 147 #ifdef CONFIG_NUMA 148 unsigned int node; 149 #endif 150 void *handler_data; 151 struct msi_desc *msi_desc; 152 #ifdef CONFIG_SMP 153 cpumask_var_t affinity; 154 #endif 155 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 156 cpumask_var_t effective_affinity; 157 #endif 158 #ifdef CONFIG_GENERIC_IRQ_IPI 159 unsigned int ipi_offset; 160 #endif 161 }; 162 163 /** 164 * struct irq_data - per irq chip data passed down to chip functions 165 * @mask: precomputed bitmask for accessing the chip registers 166 * @irq: interrupt number 167 * @hwirq: hardware interrupt number, local to the interrupt domain 168 * @common: point to data shared by all irqchips 169 * @chip: low level interrupt hardware access 170 * @domain: Interrupt translation domain; responsible for mapping 171 * between hwirq number and linux irq number. 172 * @parent_data: pointer to parent struct irq_data to support hierarchy 173 * irq_domain 174 * @chip_data: platform-specific per-chip private data for the chip 175 * methods, to allow shared chip implementations 176 */ 177 struct irq_data { 178 u32 mask; 179 unsigned int irq; 180 irq_hw_number_t hwirq; 181 struct irq_common_data *common; 182 struct irq_chip *chip; 183 struct irq_domain *domain; 184 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 185 struct irq_data *parent_data; 186 #endif 187 void *chip_data; 188 }; 189 190 /* 191 * Bit masks for irq_common_data.state_use_accessors 192 * 193 * IRQD_TRIGGER_MASK - Mask for the trigger type bits 194 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 195 * IRQD_ACTIVATED - Interrupt has already been activated 196 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 197 * IRQD_PER_CPU - Interrupt is per cpu 198 * IRQD_AFFINITY_SET - Interrupt affinity was set 199 * IRQD_LEVEL - Interrupt is level triggered 200 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup 201 * from suspend 202 * IRQD_IRQ_DISABLED - Disabled state of the interrupt 203 * IRQD_IRQ_MASKED - Masked state of the interrupt 204 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt 205 * IRQD_WAKEUP_ARMED - Wakeup mode armed 206 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU 207 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel 208 * IRQD_IRQ_STARTED - Startup state of the interrupt 209 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity 210 * mask. Applies only to affinity managed irqs. 211 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target 212 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set 213 * IRQD_CAN_RESERVE - Can use reservation mode 214 * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked 215 * from actual interrupt context. 216 * IRQD_AFFINITY_ON_ACTIVATE - Affinity is set on activation. Don't call 217 * irq_chip::irq_set_affinity() when deactivated. 218 * IRQD_IRQ_ENABLED_ON_SUSPEND - Interrupt is enabled on suspend by irq pm if 219 * irqchip have flag IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND set. 220 * IRQD_RESEND_WHEN_IN_PROGRESS - Interrupt may fire when already in progress in which 221 * case it must be resent at the next available opportunity. 222 */ 223 enum { 224 IRQD_TRIGGER_MASK = 0xf, 225 IRQD_SETAFFINITY_PENDING = BIT(8), 226 IRQD_ACTIVATED = BIT(9), 227 IRQD_NO_BALANCING = BIT(10), 228 IRQD_PER_CPU = BIT(11), 229 IRQD_AFFINITY_SET = BIT(12), 230 IRQD_LEVEL = BIT(13), 231 IRQD_WAKEUP_STATE = BIT(14), 232 IRQD_IRQ_DISABLED = BIT(16), 233 IRQD_IRQ_MASKED = BIT(17), 234 IRQD_IRQ_INPROGRESS = BIT(18), 235 IRQD_WAKEUP_ARMED = BIT(19), 236 IRQD_FORWARDED_TO_VCPU = BIT(20), 237 IRQD_AFFINITY_MANAGED = BIT(21), 238 IRQD_IRQ_STARTED = BIT(22), 239 IRQD_MANAGED_SHUTDOWN = BIT(23), 240 IRQD_SINGLE_TARGET = BIT(24), 241 IRQD_DEFAULT_TRIGGER_SET = BIT(25), 242 IRQD_CAN_RESERVE = BIT(26), 243 IRQD_HANDLE_ENFORCE_IRQCTX = BIT(27), 244 IRQD_AFFINITY_ON_ACTIVATE = BIT(28), 245 IRQD_IRQ_ENABLED_ON_SUSPEND = BIT(29), 246 IRQD_RESEND_WHEN_IN_PROGRESS = BIT(30), 247 }; 248 249 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors) 250 251 static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 252 { 253 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING; 254 } 255 256 static inline bool irqd_is_per_cpu(struct irq_data *d) 257 { 258 return __irqd_to_state(d) & IRQD_PER_CPU; 259 } 260 261 static inline bool irqd_can_balance(struct irq_data *d) 262 { 263 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); 264 } 265 266 static inline bool irqd_affinity_was_set(struct irq_data *d) 267 { 268 return __irqd_to_state(d) & IRQD_AFFINITY_SET; 269 } 270 271 static inline void irqd_mark_affinity_was_set(struct irq_data *d) 272 { 273 __irqd_to_state(d) |= IRQD_AFFINITY_SET; 274 } 275 276 static inline bool irqd_trigger_type_was_set(struct irq_data *d) 277 { 278 return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET; 279 } 280 281 static inline u32 irqd_get_trigger_type(struct irq_data *d) 282 { 283 return __irqd_to_state(d) & IRQD_TRIGGER_MASK; 284 } 285 286 /* 287 * Must only be called inside irq_chip.irq_set_type() functions or 288 * from the DT/ACPI setup code. 289 */ 290 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) 291 { 292 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK; 293 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK; 294 __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET; 295 } 296 297 static inline bool irqd_is_level_type(struct irq_data *d) 298 { 299 return __irqd_to_state(d) & IRQD_LEVEL; 300 } 301 302 /* 303 * Must only be called of irqchip.irq_set_affinity() or low level 304 * hierarchy domain allocation functions. 305 */ 306 static inline void irqd_set_single_target(struct irq_data *d) 307 { 308 __irqd_to_state(d) |= IRQD_SINGLE_TARGET; 309 } 310 311 static inline bool irqd_is_single_target(struct irq_data *d) 312 { 313 return __irqd_to_state(d) & IRQD_SINGLE_TARGET; 314 } 315 316 static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d) 317 { 318 __irqd_to_state(d) |= IRQD_HANDLE_ENFORCE_IRQCTX; 319 } 320 321 static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d) 322 { 323 return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX; 324 } 325 326 static inline bool irqd_is_enabled_on_suspend(struct irq_data *d) 327 { 328 return __irqd_to_state(d) & IRQD_IRQ_ENABLED_ON_SUSPEND; 329 } 330 331 static inline bool irqd_is_wakeup_set(struct irq_data *d) 332 { 333 return __irqd_to_state(d) & IRQD_WAKEUP_STATE; 334 } 335 336 static inline bool irqd_irq_disabled(struct irq_data *d) 337 { 338 return __irqd_to_state(d) & IRQD_IRQ_DISABLED; 339 } 340 341 static inline bool irqd_irq_masked(struct irq_data *d) 342 { 343 return __irqd_to_state(d) & IRQD_IRQ_MASKED; 344 } 345 346 static inline bool irqd_irq_inprogress(struct irq_data *d) 347 { 348 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; 349 } 350 351 static inline bool irqd_is_wakeup_armed(struct irq_data *d) 352 { 353 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED; 354 } 355 356 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d) 357 { 358 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU; 359 } 360 361 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d) 362 { 363 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU; 364 } 365 366 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d) 367 { 368 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; 369 } 370 371 static inline bool irqd_affinity_is_managed(struct irq_data *d) 372 { 373 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED; 374 } 375 376 static inline bool irqd_is_activated(struct irq_data *d) 377 { 378 return __irqd_to_state(d) & IRQD_ACTIVATED; 379 } 380 381 static inline void irqd_set_activated(struct irq_data *d) 382 { 383 __irqd_to_state(d) |= IRQD_ACTIVATED; 384 } 385 386 static inline void irqd_clr_activated(struct irq_data *d) 387 { 388 __irqd_to_state(d) &= ~IRQD_ACTIVATED; 389 } 390 391 static inline bool irqd_is_started(struct irq_data *d) 392 { 393 return __irqd_to_state(d) & IRQD_IRQ_STARTED; 394 } 395 396 static inline bool irqd_is_managed_and_shutdown(struct irq_data *d) 397 { 398 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN; 399 } 400 401 static inline void irqd_set_can_reserve(struct irq_data *d) 402 { 403 __irqd_to_state(d) |= IRQD_CAN_RESERVE; 404 } 405 406 static inline void irqd_clr_can_reserve(struct irq_data *d) 407 { 408 __irqd_to_state(d) &= ~IRQD_CAN_RESERVE; 409 } 410 411 static inline bool irqd_can_reserve(struct irq_data *d) 412 { 413 return __irqd_to_state(d) & IRQD_CAN_RESERVE; 414 } 415 416 static inline void irqd_set_affinity_on_activate(struct irq_data *d) 417 { 418 __irqd_to_state(d) |= IRQD_AFFINITY_ON_ACTIVATE; 419 } 420 421 static inline bool irqd_affinity_on_activate(struct irq_data *d) 422 { 423 return __irqd_to_state(d) & IRQD_AFFINITY_ON_ACTIVATE; 424 } 425 426 static inline void irqd_set_resend_when_in_progress(struct irq_data *d) 427 { 428 __irqd_to_state(d) |= IRQD_RESEND_WHEN_IN_PROGRESS; 429 } 430 431 static inline bool irqd_needs_resend_when_in_progress(struct irq_data *d) 432 { 433 return __irqd_to_state(d) & IRQD_RESEND_WHEN_IN_PROGRESS; 434 } 435 436 #undef __irqd_to_state 437 438 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) 439 { 440 return d->hwirq; 441 } 442 443 /** 444 * struct irq_chip - hardware interrupt chip descriptor 445 * 446 * @name: name for /proc/interrupts 447 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 448 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 449 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) 450 * @irq_disable: disable the interrupt 451 * @irq_ack: start of a new interrupt 452 * @irq_mask: mask an interrupt source 453 * @irq_mask_ack: ack and mask an interrupt source 454 * @irq_unmask: unmask an interrupt source 455 * @irq_eoi: end of interrupt 456 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force 457 * argument is true, it tells the driver to 458 * unconditionally apply the affinity setting. Sanity 459 * checks against the supplied affinity mask are not 460 * required. This is used for CPU hotplug where the 461 * target CPU is not yet set in the cpu_online_mask. 462 * @irq_retrigger: resend an IRQ to the CPU 463 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ 464 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 465 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 466 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 467 * @irq_cpu_online: configure an interrupt source for a secondary CPU 468 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU 469 * @irq_suspend: function called from core code on suspend once per 470 * chip, when one or more interrupts are installed 471 * @irq_resume: function called from core code on resume once per chip, 472 * when one ore more interrupts are installed 473 * @irq_pm_shutdown: function called from core code on shutdown once per chip 474 * @irq_calc_mask: Optional function to set irq_data.mask for special cases 475 * @irq_print_chip: optional to print special chip info in show_interrupts 476 * @irq_request_resources: optional to request resources before calling 477 * any other callback related to this irq 478 * @irq_release_resources: optional to release resources acquired with 479 * irq_request_resources 480 * @irq_compose_msi_msg: optional to compose message content for MSI 481 * @irq_write_msi_msg: optional to write message content for MSI 482 * @irq_get_irqchip_state: return the internal state of an interrupt 483 * @irq_set_irqchip_state: set the internal state of a interrupt 484 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine 485 * @ipi_send_single: send a single IPI to destination cpus 486 * @ipi_send_mask: send an IPI to destination cpus in cpumask 487 * @irq_nmi_setup: function called from core code before enabling an NMI 488 * @irq_nmi_teardown: function called from core code after disabling an NMI 489 * @flags: chip specific flags 490 */ 491 struct irq_chip { 492 const char *name; 493 unsigned int (*irq_startup)(struct irq_data *data); 494 void (*irq_shutdown)(struct irq_data *data); 495 void (*irq_enable)(struct irq_data *data); 496 void (*irq_disable)(struct irq_data *data); 497 498 void (*irq_ack)(struct irq_data *data); 499 void (*irq_mask)(struct irq_data *data); 500 void (*irq_mask_ack)(struct irq_data *data); 501 void (*irq_unmask)(struct irq_data *data); 502 void (*irq_eoi)(struct irq_data *data); 503 504 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); 505 int (*irq_retrigger)(struct irq_data *data); 506 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); 507 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 508 509 void (*irq_bus_lock)(struct irq_data *data); 510 void (*irq_bus_sync_unlock)(struct irq_data *data); 511 512 #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE 513 void (*irq_cpu_online)(struct irq_data *data); 514 void (*irq_cpu_offline)(struct irq_data *data); 515 #endif 516 void (*irq_suspend)(struct irq_data *data); 517 void (*irq_resume)(struct irq_data *data); 518 void (*irq_pm_shutdown)(struct irq_data *data); 519 520 void (*irq_calc_mask)(struct irq_data *data); 521 522 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 523 int (*irq_request_resources)(struct irq_data *data); 524 void (*irq_release_resources)(struct irq_data *data); 525 526 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); 527 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); 528 529 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); 530 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); 531 532 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); 533 534 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); 535 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); 536 537 int (*irq_nmi_setup)(struct irq_data *data); 538 void (*irq_nmi_teardown)(struct irq_data *data); 539 540 unsigned long flags; 541 }; 542 543 /* 544 * irq_chip specific flags 545 * 546 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() 547 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled 548 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path 549 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks 550 * when irq enabled 551 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip 552 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask 553 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode 554 * IRQCHIP_SUPPORTS_LEVEL_MSI: Chip can provide two doorbells for Level MSIs 555 * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips 556 * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs 557 * in the suspend path if they are in disabled state 558 * IRQCHIP_AFFINITY_PRE_STARTUP: Default affinity update before startup 559 * IRQCHIP_IMMUTABLE: Don't ever change anything in this chip 560 * IRQCHIP_MOVE_DEFERRED: Move the interrupt in actual interrupt context 561 */ 562 enum { 563 IRQCHIP_SET_TYPE_MASKED = (1 << 0), 564 IRQCHIP_EOI_IF_HANDLED = (1 << 1), 565 IRQCHIP_MASK_ON_SUSPEND = (1 << 2), 566 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), 567 IRQCHIP_SKIP_SET_WAKE = (1 << 4), 568 IRQCHIP_ONESHOT_SAFE = (1 << 5), 569 IRQCHIP_EOI_THREADED = (1 << 6), 570 IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7), 571 IRQCHIP_SUPPORTS_NMI = (1 << 8), 572 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9), 573 IRQCHIP_AFFINITY_PRE_STARTUP = (1 << 10), 574 IRQCHIP_IMMUTABLE = (1 << 11), 575 IRQCHIP_MOVE_DEFERRED = (1 << 12), 576 }; 577 578 #include <linux/irqdesc.h> 579 580 /* 581 * Pick up the arch-dependent methods: 582 */ 583 #include <asm/hw_irq.h> 584 585 #ifndef NR_IRQS_LEGACY 586 # define NR_IRQS_LEGACY 0 587 #endif 588 589 #ifndef ARCH_IRQ_INIT_FLAGS 590 # define ARCH_IRQ_INIT_FLAGS 0 591 #endif 592 593 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS 594 595 struct irqaction; 596 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); 597 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); 598 599 #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE 600 extern void irq_cpu_online(void); 601 extern void irq_cpu_offline(void); 602 #endif 603 extern int irq_set_affinity_locked(struct irq_data *data, 604 const struct cpumask *cpumask, bool force); 605 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info); 606 607 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION) 608 extern void irq_migrate_all_off_this_cpu(void); 609 extern int irq_affinity_online_cpu(unsigned int cpu); 610 #else 611 # define irq_affinity_online_cpu NULL 612 #endif 613 614 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) 615 void __irq_move_irq(struct irq_data *data); 616 static inline void irq_move_irq(struct irq_data *data) 617 { 618 if (unlikely(irqd_is_setaffinity_pending(data))) 619 __irq_move_irq(data); 620 } 621 void irq_move_masked_irq(struct irq_data *data); 622 void irq_force_complete_move(struct irq_desc *desc); 623 #else 624 static inline void irq_move_irq(struct irq_data *data) { } 625 static inline void irq_move_masked_irq(struct irq_data *data) { } 626 static inline void irq_force_complete_move(struct irq_desc *desc) { } 627 #endif 628 629 extern int no_irq_affinity; 630 631 #ifdef CONFIG_HARDIRQS_SW_RESEND 632 int irq_set_parent(int irq, int parent_irq); 633 #else 634 static inline int irq_set_parent(int irq, int parent_irq) 635 { 636 return 0; 637 } 638 #endif 639 640 /* 641 * Built-in IRQ handlers for various IRQ types, 642 * callable via desc->handle_irq() 643 */ 644 extern void handle_level_irq(struct irq_desc *desc); 645 extern void handle_fasteoi_irq(struct irq_desc *desc); 646 extern void handle_edge_irq(struct irq_desc *desc); 647 extern void handle_edge_eoi_irq(struct irq_desc *desc); 648 extern void handle_simple_irq(struct irq_desc *desc); 649 extern void handle_untracked_irq(struct irq_desc *desc); 650 extern void handle_percpu_irq(struct irq_desc *desc); 651 extern void handle_percpu_devid_irq(struct irq_desc *desc); 652 extern void handle_bad_irq(struct irq_desc *desc); 653 extern void handle_nested_irq(unsigned int irq); 654 655 extern void handle_fasteoi_nmi(struct irq_desc *desc); 656 extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc); 657 658 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); 659 extern int irq_chip_pm_get(struct irq_data *data); 660 extern int irq_chip_pm_put(struct irq_data *data); 661 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 662 extern void handle_fasteoi_ack_irq(struct irq_desc *desc); 663 extern void handle_fasteoi_mask_irq(struct irq_desc *desc); 664 extern int irq_chip_set_parent_state(struct irq_data *data, 665 enum irqchip_irq_state which, 666 bool val); 667 extern int irq_chip_get_parent_state(struct irq_data *data, 668 enum irqchip_irq_state which, 669 bool *state); 670 extern void irq_chip_enable_parent(struct irq_data *data); 671 extern void irq_chip_disable_parent(struct irq_data *data); 672 extern void irq_chip_ack_parent(struct irq_data *data); 673 extern int irq_chip_retrigger_hierarchy(struct irq_data *data); 674 extern void irq_chip_mask_parent(struct irq_data *data); 675 extern void irq_chip_mask_ack_parent(struct irq_data *data); 676 extern void irq_chip_unmask_parent(struct irq_data *data); 677 extern void irq_chip_eoi_parent(struct irq_data *data); 678 extern int irq_chip_set_affinity_parent(struct irq_data *data, 679 const struct cpumask *dest, 680 bool force); 681 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); 682 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, 683 void *vcpu_info); 684 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); 685 extern int irq_chip_request_resources_parent(struct irq_data *data); 686 extern void irq_chip_release_resources_parent(struct irq_data *data); 687 #endif 688 689 /* Disable or mask interrupts during a kernel kexec */ 690 extern void machine_kexec_mask_interrupts(void); 691 692 /* Handling of unhandled and spurious interrupts: */ 693 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret); 694 695 696 /* Enable/disable irq debugging output: */ 697 extern int noirqdebug_setup(char *str); 698 699 /* Checks whether the interrupt can be requested by request_irq(): */ 700 extern int can_request_irq(unsigned int irq, unsigned long irqflags); 701 702 /* Dummy irq-chip implementations: */ 703 extern struct irq_chip no_irq_chip; 704 extern struct irq_chip dummy_irq_chip; 705 706 extern void 707 irq_set_chip_and_handler_name(unsigned int irq, const struct irq_chip *chip, 708 irq_flow_handler_t handle, const char *name); 709 710 static inline void irq_set_chip_and_handler(unsigned int irq, 711 const struct irq_chip *chip, 712 irq_flow_handler_t handle) 713 { 714 irq_set_chip_and_handler_name(irq, chip, handle, NULL); 715 } 716 717 extern int irq_set_percpu_devid(unsigned int irq); 718 extern int irq_set_percpu_devid_partition(unsigned int irq, 719 const struct cpumask *affinity); 720 extern int irq_get_percpu_devid_partition(unsigned int irq, 721 struct cpumask *affinity); 722 723 extern void 724 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, 725 const char *name); 726 727 static inline void 728 irq_set_handler(unsigned int irq, irq_flow_handler_t handle) 729 { 730 __irq_set_handler(irq, handle, 0, NULL); 731 } 732 733 /* 734 * Set a highlevel chained flow handler for a given IRQ. 735 * (a chained handler is automatically enabled and set to 736 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 737 */ 738 static inline void 739 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) 740 { 741 __irq_set_handler(irq, handle, 1, NULL); 742 } 743 744 /* 745 * Set a highlevel chained flow handler and its data for a given IRQ. 746 * (a chained handler is automatically enabled and set to 747 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 748 */ 749 void 750 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, 751 void *data); 752 753 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); 754 755 static inline void irq_set_status_flags(unsigned int irq, unsigned long set) 756 { 757 irq_modify_status(irq, 0, set); 758 } 759 760 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) 761 { 762 irq_modify_status(irq, clr, 0); 763 } 764 765 static inline void irq_set_noprobe(unsigned int irq) 766 { 767 irq_modify_status(irq, 0, IRQ_NOPROBE); 768 } 769 770 static inline void irq_set_probe(unsigned int irq) 771 { 772 irq_modify_status(irq, IRQ_NOPROBE, 0); 773 } 774 775 static inline void irq_set_nothread(unsigned int irq) 776 { 777 irq_modify_status(irq, 0, IRQ_NOTHREAD); 778 } 779 780 static inline void irq_set_thread(unsigned int irq) 781 { 782 irq_modify_status(irq, IRQ_NOTHREAD, 0); 783 } 784 785 static inline void irq_set_nested_thread(unsigned int irq, bool nest) 786 { 787 if (nest) 788 irq_set_status_flags(irq, IRQ_NESTED_THREAD); 789 else 790 irq_clear_status_flags(irq, IRQ_NESTED_THREAD); 791 } 792 793 static inline void irq_set_percpu_devid_flags(unsigned int irq) 794 { 795 irq_set_status_flags(irq, 796 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | 797 IRQ_NOPROBE | IRQ_PER_CPU_DEVID); 798 } 799 800 /* Set/get chip/data for an IRQ: */ 801 extern int irq_set_chip(unsigned int irq, const struct irq_chip *chip); 802 extern int irq_set_handler_data(unsigned int irq, void *data); 803 extern int irq_set_chip_data(unsigned int irq, void *data); 804 extern int irq_set_irq_type(unsigned int irq, unsigned int type); 805 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 806 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, 807 struct msi_desc *entry); 808 extern struct irq_data *irq_get_irq_data(unsigned int irq); 809 810 static inline struct irq_chip *irq_get_chip(unsigned int irq) 811 { 812 struct irq_data *d = irq_get_irq_data(irq); 813 return d ? d->chip : NULL; 814 } 815 816 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) 817 { 818 return d->chip; 819 } 820 821 static inline void *irq_get_chip_data(unsigned int irq) 822 { 823 struct irq_data *d = irq_get_irq_data(irq); 824 return d ? d->chip_data : NULL; 825 } 826 827 static inline void *irq_data_get_irq_chip_data(struct irq_data *d) 828 { 829 return d->chip_data; 830 } 831 832 static inline void *irq_get_handler_data(unsigned int irq) 833 { 834 struct irq_data *d = irq_get_irq_data(irq); 835 return d ? d->common->handler_data : NULL; 836 } 837 838 static inline void *irq_data_get_irq_handler_data(struct irq_data *d) 839 { 840 return d->common->handler_data; 841 } 842 843 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) 844 { 845 struct irq_data *d = irq_get_irq_data(irq); 846 return d ? d->common->msi_desc : NULL; 847 } 848 849 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d) 850 { 851 return d->common->msi_desc; 852 } 853 854 static inline u32 irq_get_trigger_type(unsigned int irq) 855 { 856 struct irq_data *d = irq_get_irq_data(irq); 857 return d ? irqd_get_trigger_type(d) : 0; 858 } 859 860 static inline int irq_common_data_get_node(struct irq_common_data *d) 861 { 862 #ifdef CONFIG_NUMA 863 return d->node; 864 #else 865 return 0; 866 #endif 867 } 868 869 static inline int irq_data_get_node(struct irq_data *d) 870 { 871 return irq_common_data_get_node(d->common); 872 } 873 874 static inline 875 const struct cpumask *irq_data_get_affinity_mask(struct irq_data *d) 876 { 877 #ifdef CONFIG_SMP 878 return d->common->affinity; 879 #else 880 return cpumask_of(0); 881 #endif 882 } 883 884 static inline void irq_data_update_affinity(struct irq_data *d, 885 const struct cpumask *m) 886 { 887 #ifdef CONFIG_SMP 888 cpumask_copy(d->common->affinity, m); 889 #endif 890 } 891 892 static inline const struct cpumask *irq_get_affinity_mask(int irq) 893 { 894 struct irq_data *d = irq_get_irq_data(irq); 895 896 return d ? irq_data_get_affinity_mask(d) : NULL; 897 } 898 899 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 900 static inline 901 const struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 902 { 903 return d->common->effective_affinity; 904 } 905 static inline void irq_data_update_effective_affinity(struct irq_data *d, 906 const struct cpumask *m) 907 { 908 cpumask_copy(d->common->effective_affinity, m); 909 } 910 #else 911 static inline void irq_data_update_effective_affinity(struct irq_data *d, 912 const struct cpumask *m) 913 { 914 } 915 static inline 916 const struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 917 { 918 return irq_data_get_affinity_mask(d); 919 } 920 #endif 921 922 static inline 923 const struct cpumask *irq_get_effective_affinity_mask(unsigned int irq) 924 { 925 struct irq_data *d = irq_get_irq_data(irq); 926 927 return d ? irq_data_get_effective_affinity_mask(d) : NULL; 928 } 929 930 unsigned int arch_dynirq_lower_bound(unsigned int from); 931 932 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, 933 struct module *owner, 934 const struct irq_affinity_desc *affinity); 935 936 int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from, 937 unsigned int cnt, int node, struct module *owner, 938 const struct irq_affinity_desc *affinity); 939 940 /* use macros to avoid needing export.h for THIS_MODULE */ 941 #define irq_alloc_descs(irq, from, cnt, node) \ 942 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL) 943 944 #define irq_alloc_desc(node) \ 945 irq_alloc_descs(-1, 1, 1, node) 946 947 #define irq_alloc_desc_at(at, node) \ 948 irq_alloc_descs(at, at, 1, node) 949 950 #define irq_alloc_desc_from(from, node) \ 951 irq_alloc_descs(-1, from, 1, node) 952 953 #define irq_alloc_descs_from(from, cnt, node) \ 954 irq_alloc_descs(-1, from, cnt, node) 955 956 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \ 957 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL) 958 959 #define devm_irq_alloc_desc(dev, node) \ 960 devm_irq_alloc_descs(dev, -1, 1, 1, node) 961 962 #define devm_irq_alloc_desc_at(dev, at, node) \ 963 devm_irq_alloc_descs(dev, at, at, 1, node) 964 965 #define devm_irq_alloc_desc_from(dev, from, node) \ 966 devm_irq_alloc_descs(dev, -1, from, 1, node) 967 968 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \ 969 devm_irq_alloc_descs(dev, -1, from, cnt, node) 970 971 void irq_free_descs(unsigned int irq, unsigned int cnt); 972 static inline void irq_free_desc(unsigned int irq) 973 { 974 irq_free_descs(irq, 1); 975 } 976 977 #ifdef CONFIG_GENERIC_IRQ_LEGACY 978 void irq_init_desc(unsigned int irq); 979 #endif 980 981 /** 982 * struct irq_chip_regs - register offsets for struct irq_gci 983 * @enable: Enable register offset to reg_base 984 * @disable: Disable register offset to reg_base 985 * @mask: Mask register offset to reg_base 986 * @ack: Ack register offset to reg_base 987 * @eoi: Eoi register offset to reg_base 988 * @type: Type configuration register offset to reg_base 989 */ 990 struct irq_chip_regs { 991 unsigned long enable; 992 unsigned long disable; 993 unsigned long mask; 994 unsigned long ack; 995 unsigned long eoi; 996 unsigned long type; 997 }; 998 999 /** 1000 * struct irq_chip_type - Generic interrupt chip instance for a flow type 1001 * @chip: The real interrupt chip which provides the callbacks 1002 * @regs: Register offsets for this chip 1003 * @handler: Flow handler associated with this chip 1004 * @type: Chip can handle these flow types 1005 * @mask_cache_priv: Cached mask register private to the chip type 1006 * @mask_cache: Pointer to cached mask register 1007 * 1008 * A irq_generic_chip can have several instances of irq_chip_type when 1009 * it requires different functions and register offsets for different 1010 * flow types. 1011 */ 1012 struct irq_chip_type { 1013 struct irq_chip chip; 1014 struct irq_chip_regs regs; 1015 irq_flow_handler_t handler; 1016 u32 type; 1017 u32 mask_cache_priv; 1018 u32 *mask_cache; 1019 }; 1020 1021 /** 1022 * struct irq_chip_generic - Generic irq chip data structure 1023 * @lock: Lock to protect register and cache data access 1024 * @reg_base: Register base address (virtual) 1025 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL) 1026 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL) 1027 * @suspend: Function called from core code on suspend once per 1028 * chip; can be useful instead of irq_chip::suspend to 1029 * handle chip details even when no interrupts are in use 1030 * @resume: Function called from core code on resume once per chip; 1031 * can be useful instead of irq_chip::suspend to handle 1032 * chip details even when no interrupts are in use 1033 * @irq_base: Interrupt base nr for this chip 1034 * @irq_cnt: Number of interrupts handled by this chip 1035 * @mask_cache: Cached mask register shared between all chip types 1036 * @wake_enabled: Interrupt can wakeup from suspend 1037 * @wake_active: Interrupt is marked as an wakeup from suspend source 1038 * @num_ct: Number of available irq_chip_type instances (usually 1) 1039 * @private: Private data for non generic chip callbacks 1040 * @installed: bitfield to denote installed interrupts 1041 * @unused: bitfield to denote unused interrupts 1042 * @domain: irq domain pointer 1043 * @list: List head for keeping track of instances 1044 * @chip_types: Array of interrupt irq_chip_types 1045 * 1046 * Note, that irq_chip_generic can have multiple irq_chip_type 1047 * implementations which can be associated to a particular irq line of 1048 * an irq_chip_generic instance. That allows to share and protect 1049 * state in an irq_chip_generic instance when we need to implement 1050 * different flow mechanisms (level/edge) for it. 1051 */ 1052 struct irq_chip_generic { 1053 raw_spinlock_t lock; 1054 void __iomem *reg_base; 1055 u32 (*reg_readl)(void __iomem *addr); 1056 void (*reg_writel)(u32 val, void __iomem *addr); 1057 void (*suspend)(struct irq_chip_generic *gc); 1058 void (*resume)(struct irq_chip_generic *gc); 1059 unsigned int irq_base; 1060 unsigned int irq_cnt; 1061 u32 mask_cache; 1062 u32 wake_enabled; 1063 u32 wake_active; 1064 unsigned int num_ct; 1065 void *private; 1066 unsigned long installed; 1067 unsigned long unused; 1068 struct irq_domain *domain; 1069 struct list_head list; 1070 struct irq_chip_type chip_types[]; 1071 }; 1072 1073 /** 1074 * enum irq_gc_flags - Initialization flags for generic irq chips 1075 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg 1076 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for 1077 * irq chips which need to call irq_set_wake() on 1078 * the parent irq. Usually GPIO implementations 1079 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private 1080 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask 1081 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE) 1082 */ 1083 enum irq_gc_flags { 1084 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 1085 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 1086 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, 1087 IRQ_GC_NO_MASK = 1 << 3, 1088 IRQ_GC_BE_IO = 1 << 4, 1089 }; 1090 1091 /* 1092 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains 1093 * @irqs_per_chip: Number of interrupts per chip 1094 * @num_chips: Number of chips 1095 * @irq_flags_to_set: IRQ* flags to set on irq setup 1096 * @irq_flags_to_clear: IRQ* flags to clear on irq setup 1097 * @gc_flags: Generic chip specific setup flags 1098 * @exit: Function called on each chip when they are destroyed. 1099 * @gc: Array of pointers to generic interrupt chips 1100 */ 1101 struct irq_domain_chip_generic { 1102 unsigned int irqs_per_chip; 1103 unsigned int num_chips; 1104 unsigned int irq_flags_to_clear; 1105 unsigned int irq_flags_to_set; 1106 enum irq_gc_flags gc_flags; 1107 void (*exit)(struct irq_chip_generic *gc); 1108 struct irq_chip_generic *gc[]; 1109 }; 1110 1111 /** 1112 * struct irq_domain_chip_generic_info - Generic chip information structure 1113 * @name: Name of the generic interrupt chip 1114 * @handler: Interrupt handler used by the generic interrupt chip 1115 * @irqs_per_chip: Number of interrupts each chip handles (max 32) 1116 * @num_ct: Number of irq_chip_type instances associated with each 1117 * chip 1118 * @irq_flags_to_clear: IRQ_* bits to clear in the mapping function 1119 * @irq_flags_to_set: IRQ_* bits to set in the mapping function 1120 * @gc_flags: Generic chip specific setup flags 1121 * @init: Function called on each chip when they are created. 1122 * Allow to do some additional chip initialisation. 1123 * @exit: Function called on each chip when they are destroyed. 1124 * Allow to do some chip cleanup operation. 1125 */ 1126 struct irq_domain_chip_generic_info { 1127 const char *name; 1128 irq_flow_handler_t handler; 1129 unsigned int irqs_per_chip; 1130 unsigned int num_ct; 1131 unsigned int irq_flags_to_clear; 1132 unsigned int irq_flags_to_set; 1133 enum irq_gc_flags gc_flags; 1134 int (*init)(struct irq_chip_generic *gc); 1135 void (*exit)(struct irq_chip_generic *gc); 1136 }; 1137 1138 /* Generic chip callback functions */ 1139 void irq_gc_noop(struct irq_data *d); 1140 void irq_gc_mask_disable_reg(struct irq_data *d); 1141 void irq_gc_mask_set_bit(struct irq_data *d); 1142 void irq_gc_mask_clr_bit(struct irq_data *d); 1143 void irq_gc_unmask_enable_reg(struct irq_data *d); 1144 void irq_gc_ack_set_bit(struct irq_data *d); 1145 void irq_gc_ack_clr_bit(struct irq_data *d); 1146 void irq_gc_mask_disable_and_ack_set(struct irq_data *d); 1147 void irq_gc_eoi(struct irq_data *d); 1148 int irq_gc_set_wake(struct irq_data *d, unsigned int on); 1149 1150 /* Setup functions for irq_chip_generic */ 1151 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, 1152 irq_hw_number_t hw_irq); 1153 void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq); 1154 struct irq_chip_generic * 1155 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, 1156 void __iomem *reg_base, irq_flow_handler_t handler); 1157 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 1158 enum irq_gc_flags flags, unsigned int clr, 1159 unsigned int set); 1160 int irq_setup_alt_chip(struct irq_data *d, unsigned int type); 1161 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 1162 unsigned int clr, unsigned int set); 1163 1164 struct irq_chip_generic * 1165 devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct, 1166 unsigned int irq_base, void __iomem *reg_base, 1167 irq_flow_handler_t handler); 1168 int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc, 1169 u32 msk, enum irq_gc_flags flags, 1170 unsigned int clr, unsigned int set); 1171 1172 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); 1173 1174 #ifdef CONFIG_GENERIC_IRQ_CHIP 1175 int irq_domain_alloc_generic_chips(struct irq_domain *d, 1176 const struct irq_domain_chip_generic_info *info); 1177 void irq_domain_remove_generic_chips(struct irq_domain *d); 1178 #else 1179 static inline int 1180 irq_domain_alloc_generic_chips(struct irq_domain *d, 1181 const struct irq_domain_chip_generic_info *info) 1182 { 1183 return -EINVAL; 1184 } 1185 static inline void irq_domain_remove_generic_chips(struct irq_domain *d) { } 1186 #endif /* CONFIG_GENERIC_IRQ_CHIP */ 1187 1188 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, 1189 int num_ct, const char *name, 1190 irq_flow_handler_t handler, 1191 unsigned int clr, unsigned int set, 1192 enum irq_gc_flags flags); 1193 1194 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \ 1195 handler, clr, set, flags) \ 1196 ({ \ 1197 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \ 1198 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\ 1199 handler, clr, set, flags); \ 1200 }) 1201 1202 static inline void irq_free_generic_chip(struct irq_chip_generic *gc) 1203 { 1204 kfree(gc); 1205 } 1206 1207 static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc, 1208 u32 msk, unsigned int clr, 1209 unsigned int set) 1210 { 1211 irq_remove_generic_chip(gc, msk, clr, set); 1212 irq_free_generic_chip(gc); 1213 } 1214 1215 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) 1216 { 1217 return container_of(d->chip, struct irq_chip_type, chip); 1218 } 1219 1220 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) 1221 1222 #ifdef CONFIG_SMP 1223 static inline void irq_gc_lock(struct irq_chip_generic *gc) 1224 { 1225 raw_spin_lock(&gc->lock); 1226 } 1227 1228 static inline void irq_gc_unlock(struct irq_chip_generic *gc) 1229 { 1230 raw_spin_unlock(&gc->lock); 1231 } 1232 #else 1233 static inline void irq_gc_lock(struct irq_chip_generic *gc) { } 1234 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } 1235 #endif 1236 1237 /* 1238 * The irqsave variants are for usage in non interrupt code. Do not use 1239 * them in irq_chip callbacks. Use irq_gc_lock() instead. 1240 */ 1241 #define irq_gc_lock_irqsave(gc, flags) \ 1242 raw_spin_lock_irqsave(&(gc)->lock, flags) 1243 1244 #define irq_gc_unlock_irqrestore(gc, flags) \ 1245 raw_spin_unlock_irqrestore(&(gc)->lock, flags) 1246 1247 static inline void irq_reg_writel(struct irq_chip_generic *gc, 1248 u32 val, int reg_offset) 1249 { 1250 if (gc->reg_writel) 1251 gc->reg_writel(val, gc->reg_base + reg_offset); 1252 else 1253 writel(val, gc->reg_base + reg_offset); 1254 } 1255 1256 static inline u32 irq_reg_readl(struct irq_chip_generic *gc, 1257 int reg_offset) 1258 { 1259 if (gc->reg_readl) 1260 return gc->reg_readl(gc->reg_base + reg_offset); 1261 else 1262 return readl(gc->reg_base + reg_offset); 1263 } 1264 1265 struct irq_matrix; 1266 struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits, 1267 unsigned int alloc_start, 1268 unsigned int alloc_end); 1269 void irq_matrix_online(struct irq_matrix *m); 1270 void irq_matrix_offline(struct irq_matrix *m); 1271 void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace); 1272 int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk); 1273 void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk); 1274 int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk, 1275 unsigned int *mapped_cpu); 1276 void irq_matrix_reserve(struct irq_matrix *m); 1277 void irq_matrix_remove_reserved(struct irq_matrix *m); 1278 int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk, 1279 bool reserved, unsigned int *mapped_cpu); 1280 void irq_matrix_free(struct irq_matrix *m, unsigned int cpu, 1281 unsigned int bit, bool managed); 1282 void irq_matrix_assign(struct irq_matrix *m, unsigned int bit); 1283 unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown); 1284 unsigned int irq_matrix_allocated(struct irq_matrix *m); 1285 unsigned int irq_matrix_reserved(struct irq_matrix *m); 1286 void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind); 1287 1288 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */ 1289 #define INVALID_HWIRQ (~0UL) 1290 irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu); 1291 int __ipi_send_single(struct irq_desc *desc, unsigned int cpu); 1292 int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest); 1293 int ipi_send_single(unsigned int virq, unsigned int cpu); 1294 int ipi_send_mask(unsigned int virq, const struct cpumask *dest); 1295 1296 void ipi_mux_process(void); 1297 int ipi_mux_create(unsigned int nr_ipi, void (*mux_send)(unsigned int cpu)); 1298 1299 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER 1300 /* 1301 * Registers a generic IRQ handling function as the top-level IRQ handler in 1302 * the system, which is generally the first C code called from an assembly 1303 * architecture-specific interrupt handler. 1304 * 1305 * Returns 0 on success, or -EBUSY if an IRQ handler has already been 1306 * registered. 1307 */ 1308 int __init set_handle_irq(void (*handle_irq)(struct pt_regs *)); 1309 1310 /* 1311 * Allows interrupt handlers to find the irqchip that's been registered as the 1312 * top-level IRQ handler. 1313 */ 1314 extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init; 1315 asmlinkage void generic_handle_arch_irq(struct pt_regs *regs); 1316 #else 1317 #ifndef set_handle_irq 1318 #define set_handle_irq(handle_irq) \ 1319 do { \ 1320 (void)handle_irq; \ 1321 WARN_ON(1); \ 1322 } while (0) 1323 #endif 1324 #endif 1325 1326 #endif /* _LINUX_IRQ_H */ 1327