1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_IRQ_H 3 #define _LINUX_IRQ_H 4 5 /* 6 * Please do not include this file in generic code. There is currently 7 * no requirement for any architecture to implement anything held 8 * within this file. 9 * 10 * Thanks. --rmk 11 */ 12 13 #include <linux/cache.h> 14 #include <linux/spinlock.h> 15 #include <linux/cpumask.h> 16 #include <linux/irqhandler.h> 17 #include <linux/irqreturn.h> 18 #include <linux/irqnr.h> 19 #include <linux/topology.h> 20 #include <linux/io.h> 21 #include <linux/slab.h> 22 23 #include <asm/irq.h> 24 #include <asm/ptrace.h> 25 #include <asm/irq_regs.h> 26 27 struct seq_file; 28 struct module; 29 struct msi_msg; 30 struct irq_affinity_desc; 31 enum irqchip_irq_state; 32 33 /* 34 * IRQ line status. 35 * 36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h 37 * 38 * IRQ_TYPE_NONE - default, unspecified type 39 * IRQ_TYPE_EDGE_RISING - rising edge triggered 40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered 41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 42 * IRQ_TYPE_LEVEL_HIGH - high level triggered 43 * IRQ_TYPE_LEVEL_LOW - low level triggered 44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 45 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits 46 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type 47 * to setup the HW to a sane default (used 48 * by irqdomain map() callbacks to synchronize 49 * the HW state and SW flags for a newly 50 * allocated descriptor). 51 * 52 * IRQ_TYPE_PROBE - Special flag for probing in progress 53 * 54 * Bits which can be modified via irq_set/clear/modify_status_flags() 55 * IRQ_LEVEL - Interrupt is level type. Will be also 56 * updated in the code when the above trigger 57 * bits are modified via irq_set_irq_type() 58 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect 59 * it from affinity setting 60 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing 61 * IRQ_NOREQUEST - Interrupt cannot be requested via 62 * request_irq() 63 * IRQ_NOTHREAD - Interrupt cannot be threaded 64 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in 65 * request/setup_irq() 66 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) 67 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context 68 * IRQ_NESTED_THREAD - Interrupt nests into another thread 69 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable 70 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude 71 * it from the spurious interrupt detection 72 * mechanism and from core side polling. 73 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable 74 */ 75 enum { 76 IRQ_TYPE_NONE = 0x00000000, 77 IRQ_TYPE_EDGE_RISING = 0x00000001, 78 IRQ_TYPE_EDGE_FALLING = 0x00000002, 79 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), 80 IRQ_TYPE_LEVEL_HIGH = 0x00000004, 81 IRQ_TYPE_LEVEL_LOW = 0x00000008, 82 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), 83 IRQ_TYPE_SENSE_MASK = 0x0000000f, 84 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, 85 86 IRQ_TYPE_PROBE = 0x00000010, 87 88 IRQ_LEVEL = (1 << 8), 89 IRQ_PER_CPU = (1 << 9), 90 IRQ_NOPROBE = (1 << 10), 91 IRQ_NOREQUEST = (1 << 11), 92 IRQ_NOAUTOEN = (1 << 12), 93 IRQ_NO_BALANCING = (1 << 13), 94 IRQ_MOVE_PCNTXT = (1 << 14), 95 IRQ_NESTED_THREAD = (1 << 15), 96 IRQ_NOTHREAD = (1 << 16), 97 IRQ_PER_CPU_DEVID = (1 << 17), 98 IRQ_IS_POLLED = (1 << 18), 99 IRQ_DISABLE_UNLAZY = (1 << 19), 100 }; 101 102 #define IRQF_MODIFY_MASK \ 103 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ 104 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ 105 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ 106 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY) 107 108 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 109 110 /* 111 * Return value for chip->irq_set_affinity() 112 * 113 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity 114 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity 115 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to 116 * support stacked irqchips, which indicates skipping 117 * all descendent irqchips. 118 */ 119 enum { 120 IRQ_SET_MASK_OK = 0, 121 IRQ_SET_MASK_OK_NOCOPY, 122 IRQ_SET_MASK_OK_DONE, 123 }; 124 125 struct msi_desc; 126 struct irq_domain; 127 128 /** 129 * struct irq_common_data - per irq data shared by all irqchips 130 * @state_use_accessors: status information for irq chip functions. 131 * Use accessor functions to deal with it 132 * @node: node index useful for balancing 133 * @handler_data: per-IRQ data for the irq_chip methods 134 * @affinity: IRQ affinity on SMP. If this is an IPI 135 * related irq, then this is the mask of the 136 * CPUs to which an IPI can be sent. 137 * @effective_affinity: The effective IRQ affinity on SMP as some irq 138 * chips do not allow multi CPU destinations. 139 * A subset of @affinity. 140 * @msi_desc: MSI descriptor 141 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional. 142 */ 143 struct irq_common_data { 144 unsigned int __private state_use_accessors; 145 #ifdef CONFIG_NUMA 146 unsigned int node; 147 #endif 148 void *handler_data; 149 struct msi_desc *msi_desc; 150 cpumask_var_t affinity; 151 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 152 cpumask_var_t effective_affinity; 153 #endif 154 #ifdef CONFIG_GENERIC_IRQ_IPI 155 unsigned int ipi_offset; 156 #endif 157 }; 158 159 /** 160 * struct irq_data - per irq chip data passed down to chip functions 161 * @mask: precomputed bitmask for accessing the chip registers 162 * @irq: interrupt number 163 * @hwirq: hardware interrupt number, local to the interrupt domain 164 * @common: point to data shared by all irqchips 165 * @chip: low level interrupt hardware access 166 * @domain: Interrupt translation domain; responsible for mapping 167 * between hwirq number and linux irq number. 168 * @parent_data: pointer to parent struct irq_data to support hierarchy 169 * irq_domain 170 * @chip_data: platform-specific per-chip private data for the chip 171 * methods, to allow shared chip implementations 172 */ 173 struct irq_data { 174 u32 mask; 175 unsigned int irq; 176 unsigned long hwirq; 177 struct irq_common_data *common; 178 struct irq_chip *chip; 179 struct irq_domain *domain; 180 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 181 struct irq_data *parent_data; 182 #endif 183 void *chip_data; 184 }; 185 186 /* 187 * Bit masks for irq_common_data.state_use_accessors 188 * 189 * IRQD_TRIGGER_MASK - Mask for the trigger type bits 190 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 191 * IRQD_ACTIVATED - Interrupt has already been activated 192 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 193 * IRQD_PER_CPU - Interrupt is per cpu 194 * IRQD_AFFINITY_SET - Interrupt affinity was set 195 * IRQD_LEVEL - Interrupt is level triggered 196 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup 197 * from suspend 198 * IRQD_MOVE_PCNTXT - Interrupt can be moved in process 199 * context 200 * IRQD_IRQ_DISABLED - Disabled state of the interrupt 201 * IRQD_IRQ_MASKED - Masked state of the interrupt 202 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt 203 * IRQD_WAKEUP_ARMED - Wakeup mode armed 204 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU 205 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel 206 * IRQD_IRQ_STARTED - Startup state of the interrupt 207 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity 208 * mask. Applies only to affinity managed irqs. 209 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target 210 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set 211 * IRQD_CAN_RESERVE - Can use reservation mode 212 * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change 213 * required 214 * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked 215 * from actual interrupt context. 216 * IRQD_AFFINITY_ON_ACTIVATE - Affinity is set on activation. Don't call 217 * irq_chip::irq_set_affinity() when deactivated. 218 */ 219 enum { 220 IRQD_TRIGGER_MASK = 0xf, 221 IRQD_SETAFFINITY_PENDING = (1 << 8), 222 IRQD_ACTIVATED = (1 << 9), 223 IRQD_NO_BALANCING = (1 << 10), 224 IRQD_PER_CPU = (1 << 11), 225 IRQD_AFFINITY_SET = (1 << 12), 226 IRQD_LEVEL = (1 << 13), 227 IRQD_WAKEUP_STATE = (1 << 14), 228 IRQD_MOVE_PCNTXT = (1 << 15), 229 IRQD_IRQ_DISABLED = (1 << 16), 230 IRQD_IRQ_MASKED = (1 << 17), 231 IRQD_IRQ_INPROGRESS = (1 << 18), 232 IRQD_WAKEUP_ARMED = (1 << 19), 233 IRQD_FORWARDED_TO_VCPU = (1 << 20), 234 IRQD_AFFINITY_MANAGED = (1 << 21), 235 IRQD_IRQ_STARTED = (1 << 22), 236 IRQD_MANAGED_SHUTDOWN = (1 << 23), 237 IRQD_SINGLE_TARGET = (1 << 24), 238 IRQD_DEFAULT_TRIGGER_SET = (1 << 25), 239 IRQD_CAN_RESERVE = (1 << 26), 240 IRQD_MSI_NOMASK_QUIRK = (1 << 27), 241 IRQD_HANDLE_ENFORCE_IRQCTX = (1 << 28), 242 IRQD_AFFINITY_ON_ACTIVATE = (1 << 29), 243 }; 244 245 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors) 246 247 static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 248 { 249 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING; 250 } 251 252 static inline bool irqd_is_per_cpu(struct irq_data *d) 253 { 254 return __irqd_to_state(d) & IRQD_PER_CPU; 255 } 256 257 static inline bool irqd_can_balance(struct irq_data *d) 258 { 259 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); 260 } 261 262 static inline bool irqd_affinity_was_set(struct irq_data *d) 263 { 264 return __irqd_to_state(d) & IRQD_AFFINITY_SET; 265 } 266 267 static inline void irqd_mark_affinity_was_set(struct irq_data *d) 268 { 269 __irqd_to_state(d) |= IRQD_AFFINITY_SET; 270 } 271 272 static inline bool irqd_trigger_type_was_set(struct irq_data *d) 273 { 274 return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET; 275 } 276 277 static inline u32 irqd_get_trigger_type(struct irq_data *d) 278 { 279 return __irqd_to_state(d) & IRQD_TRIGGER_MASK; 280 } 281 282 /* 283 * Must only be called inside irq_chip.irq_set_type() functions or 284 * from the DT/ACPI setup code. 285 */ 286 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) 287 { 288 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK; 289 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK; 290 __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET; 291 } 292 293 static inline bool irqd_is_level_type(struct irq_data *d) 294 { 295 return __irqd_to_state(d) & IRQD_LEVEL; 296 } 297 298 /* 299 * Must only be called of irqchip.irq_set_affinity() or low level 300 * hieararchy domain allocation functions. 301 */ 302 static inline void irqd_set_single_target(struct irq_data *d) 303 { 304 __irqd_to_state(d) |= IRQD_SINGLE_TARGET; 305 } 306 307 static inline bool irqd_is_single_target(struct irq_data *d) 308 { 309 return __irqd_to_state(d) & IRQD_SINGLE_TARGET; 310 } 311 312 static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d) 313 { 314 __irqd_to_state(d) |= IRQD_HANDLE_ENFORCE_IRQCTX; 315 } 316 317 static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d) 318 { 319 return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX; 320 } 321 322 static inline bool irqd_is_wakeup_set(struct irq_data *d) 323 { 324 return __irqd_to_state(d) & IRQD_WAKEUP_STATE; 325 } 326 327 static inline bool irqd_can_move_in_process_context(struct irq_data *d) 328 { 329 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT; 330 } 331 332 static inline bool irqd_irq_disabled(struct irq_data *d) 333 { 334 return __irqd_to_state(d) & IRQD_IRQ_DISABLED; 335 } 336 337 static inline bool irqd_irq_masked(struct irq_data *d) 338 { 339 return __irqd_to_state(d) & IRQD_IRQ_MASKED; 340 } 341 342 static inline bool irqd_irq_inprogress(struct irq_data *d) 343 { 344 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; 345 } 346 347 static inline bool irqd_is_wakeup_armed(struct irq_data *d) 348 { 349 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED; 350 } 351 352 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d) 353 { 354 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU; 355 } 356 357 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d) 358 { 359 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU; 360 } 361 362 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d) 363 { 364 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; 365 } 366 367 static inline bool irqd_affinity_is_managed(struct irq_data *d) 368 { 369 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED; 370 } 371 372 static inline bool irqd_is_activated(struct irq_data *d) 373 { 374 return __irqd_to_state(d) & IRQD_ACTIVATED; 375 } 376 377 static inline void irqd_set_activated(struct irq_data *d) 378 { 379 __irqd_to_state(d) |= IRQD_ACTIVATED; 380 } 381 382 static inline void irqd_clr_activated(struct irq_data *d) 383 { 384 __irqd_to_state(d) &= ~IRQD_ACTIVATED; 385 } 386 387 static inline bool irqd_is_started(struct irq_data *d) 388 { 389 return __irqd_to_state(d) & IRQD_IRQ_STARTED; 390 } 391 392 static inline bool irqd_is_managed_and_shutdown(struct irq_data *d) 393 { 394 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN; 395 } 396 397 static inline void irqd_set_can_reserve(struct irq_data *d) 398 { 399 __irqd_to_state(d) |= IRQD_CAN_RESERVE; 400 } 401 402 static inline void irqd_clr_can_reserve(struct irq_data *d) 403 { 404 __irqd_to_state(d) &= ~IRQD_CAN_RESERVE; 405 } 406 407 static inline bool irqd_can_reserve(struct irq_data *d) 408 { 409 return __irqd_to_state(d) & IRQD_CAN_RESERVE; 410 } 411 412 static inline void irqd_set_msi_nomask_quirk(struct irq_data *d) 413 { 414 __irqd_to_state(d) |= IRQD_MSI_NOMASK_QUIRK; 415 } 416 417 static inline void irqd_clr_msi_nomask_quirk(struct irq_data *d) 418 { 419 __irqd_to_state(d) &= ~IRQD_MSI_NOMASK_QUIRK; 420 } 421 422 static inline bool irqd_msi_nomask_quirk(struct irq_data *d) 423 { 424 return __irqd_to_state(d) & IRQD_MSI_NOMASK_QUIRK; 425 } 426 427 static inline void irqd_set_affinity_on_activate(struct irq_data *d) 428 { 429 __irqd_to_state(d) |= IRQD_AFFINITY_ON_ACTIVATE; 430 } 431 432 static inline bool irqd_affinity_on_activate(struct irq_data *d) 433 { 434 return __irqd_to_state(d) & IRQD_AFFINITY_ON_ACTIVATE; 435 } 436 437 #undef __irqd_to_state 438 439 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) 440 { 441 return d->hwirq; 442 } 443 444 /** 445 * struct irq_chip - hardware interrupt chip descriptor 446 * 447 * @parent_device: pointer to parent device for irqchip 448 * @name: name for /proc/interrupts 449 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 450 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 451 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) 452 * @irq_disable: disable the interrupt 453 * @irq_ack: start of a new interrupt 454 * @irq_mask: mask an interrupt source 455 * @irq_mask_ack: ack and mask an interrupt source 456 * @irq_unmask: unmask an interrupt source 457 * @irq_eoi: end of interrupt 458 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force 459 * argument is true, it tells the driver to 460 * unconditionally apply the affinity setting. Sanity 461 * checks against the supplied affinity mask are not 462 * required. This is used for CPU hotplug where the 463 * target CPU is not yet set in the cpu_online_mask. 464 * @irq_retrigger: resend an IRQ to the CPU 465 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ 466 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 467 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 468 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 469 * @irq_cpu_online: configure an interrupt source for a secondary CPU 470 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU 471 * @irq_suspend: function called from core code on suspend once per 472 * chip, when one or more interrupts are installed 473 * @irq_resume: function called from core code on resume once per chip, 474 * when one ore more interrupts are installed 475 * @irq_pm_shutdown: function called from core code on shutdown once per chip 476 * @irq_calc_mask: Optional function to set irq_data.mask for special cases 477 * @irq_print_chip: optional to print special chip info in show_interrupts 478 * @irq_request_resources: optional to request resources before calling 479 * any other callback related to this irq 480 * @irq_release_resources: optional to release resources acquired with 481 * irq_request_resources 482 * @irq_compose_msi_msg: optional to compose message content for MSI 483 * @irq_write_msi_msg: optional to write message content for MSI 484 * @irq_get_irqchip_state: return the internal state of an interrupt 485 * @irq_set_irqchip_state: set the internal state of a interrupt 486 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine 487 * @ipi_send_single: send a single IPI to destination cpus 488 * @ipi_send_mask: send an IPI to destination cpus in cpumask 489 * @irq_nmi_setup: function called from core code before enabling an NMI 490 * @irq_nmi_teardown: function called from core code after disabling an NMI 491 * @flags: chip specific flags 492 */ 493 struct irq_chip { 494 struct device *parent_device; 495 const char *name; 496 unsigned int (*irq_startup)(struct irq_data *data); 497 void (*irq_shutdown)(struct irq_data *data); 498 void (*irq_enable)(struct irq_data *data); 499 void (*irq_disable)(struct irq_data *data); 500 501 void (*irq_ack)(struct irq_data *data); 502 void (*irq_mask)(struct irq_data *data); 503 void (*irq_mask_ack)(struct irq_data *data); 504 void (*irq_unmask)(struct irq_data *data); 505 void (*irq_eoi)(struct irq_data *data); 506 507 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); 508 int (*irq_retrigger)(struct irq_data *data); 509 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); 510 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 511 512 void (*irq_bus_lock)(struct irq_data *data); 513 void (*irq_bus_sync_unlock)(struct irq_data *data); 514 515 void (*irq_cpu_online)(struct irq_data *data); 516 void (*irq_cpu_offline)(struct irq_data *data); 517 518 void (*irq_suspend)(struct irq_data *data); 519 void (*irq_resume)(struct irq_data *data); 520 void (*irq_pm_shutdown)(struct irq_data *data); 521 522 void (*irq_calc_mask)(struct irq_data *data); 523 524 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 525 int (*irq_request_resources)(struct irq_data *data); 526 void (*irq_release_resources)(struct irq_data *data); 527 528 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); 529 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); 530 531 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); 532 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); 533 534 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); 535 536 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); 537 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); 538 539 int (*irq_nmi_setup)(struct irq_data *data); 540 void (*irq_nmi_teardown)(struct irq_data *data); 541 542 unsigned long flags; 543 }; 544 545 /* 546 * irq_chip specific flags 547 * 548 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() 549 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled 550 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path 551 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks 552 * when irq enabled 553 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip 554 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask 555 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode 556 * IRQCHIP_SUPPORTS_LEVEL_MSI Chip can provide two doorbells for Level MSIs 557 * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips 558 */ 559 enum { 560 IRQCHIP_SET_TYPE_MASKED = (1 << 0), 561 IRQCHIP_EOI_IF_HANDLED = (1 << 1), 562 IRQCHIP_MASK_ON_SUSPEND = (1 << 2), 563 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), 564 IRQCHIP_SKIP_SET_WAKE = (1 << 4), 565 IRQCHIP_ONESHOT_SAFE = (1 << 5), 566 IRQCHIP_EOI_THREADED = (1 << 6), 567 IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7), 568 IRQCHIP_SUPPORTS_NMI = (1 << 8), 569 }; 570 571 #include <linux/irqdesc.h> 572 573 /* 574 * Pick up the arch-dependent methods: 575 */ 576 #include <asm/hw_irq.h> 577 578 #ifndef NR_IRQS_LEGACY 579 # define NR_IRQS_LEGACY 0 580 #endif 581 582 #ifndef ARCH_IRQ_INIT_FLAGS 583 # define ARCH_IRQ_INIT_FLAGS 0 584 #endif 585 586 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS 587 588 struct irqaction; 589 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); 590 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); 591 592 extern void irq_cpu_online(void); 593 extern void irq_cpu_offline(void); 594 extern int irq_set_affinity_locked(struct irq_data *data, 595 const struct cpumask *cpumask, bool force); 596 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info); 597 598 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION) 599 extern void irq_migrate_all_off_this_cpu(void); 600 extern int irq_affinity_online_cpu(unsigned int cpu); 601 #else 602 # define irq_affinity_online_cpu NULL 603 #endif 604 605 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) 606 void __irq_move_irq(struct irq_data *data); 607 static inline void irq_move_irq(struct irq_data *data) 608 { 609 if (unlikely(irqd_is_setaffinity_pending(data))) 610 __irq_move_irq(data); 611 } 612 void irq_move_masked_irq(struct irq_data *data); 613 void irq_force_complete_move(struct irq_desc *desc); 614 #else 615 static inline void irq_move_irq(struct irq_data *data) { } 616 static inline void irq_move_masked_irq(struct irq_data *data) { } 617 static inline void irq_force_complete_move(struct irq_desc *desc) { } 618 #endif 619 620 extern int no_irq_affinity; 621 622 #ifdef CONFIG_HARDIRQS_SW_RESEND 623 int irq_set_parent(int irq, int parent_irq); 624 #else 625 static inline int irq_set_parent(int irq, int parent_irq) 626 { 627 return 0; 628 } 629 #endif 630 631 /* 632 * Built-in IRQ handlers for various IRQ types, 633 * callable via desc->handle_irq() 634 */ 635 extern void handle_level_irq(struct irq_desc *desc); 636 extern void handle_fasteoi_irq(struct irq_desc *desc); 637 extern void handle_edge_irq(struct irq_desc *desc); 638 extern void handle_edge_eoi_irq(struct irq_desc *desc); 639 extern void handle_simple_irq(struct irq_desc *desc); 640 extern void handle_untracked_irq(struct irq_desc *desc); 641 extern void handle_percpu_irq(struct irq_desc *desc); 642 extern void handle_percpu_devid_irq(struct irq_desc *desc); 643 extern void handle_bad_irq(struct irq_desc *desc); 644 extern void handle_nested_irq(unsigned int irq); 645 646 extern void handle_fasteoi_nmi(struct irq_desc *desc); 647 extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc); 648 649 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); 650 extern int irq_chip_pm_get(struct irq_data *data); 651 extern int irq_chip_pm_put(struct irq_data *data); 652 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 653 extern void handle_fasteoi_ack_irq(struct irq_desc *desc); 654 extern void handle_fasteoi_mask_irq(struct irq_desc *desc); 655 extern int irq_chip_set_parent_state(struct irq_data *data, 656 enum irqchip_irq_state which, 657 bool val); 658 extern int irq_chip_get_parent_state(struct irq_data *data, 659 enum irqchip_irq_state which, 660 bool *state); 661 extern void irq_chip_enable_parent(struct irq_data *data); 662 extern void irq_chip_disable_parent(struct irq_data *data); 663 extern void irq_chip_ack_parent(struct irq_data *data); 664 extern int irq_chip_retrigger_hierarchy(struct irq_data *data); 665 extern void irq_chip_mask_parent(struct irq_data *data); 666 extern void irq_chip_mask_ack_parent(struct irq_data *data); 667 extern void irq_chip_unmask_parent(struct irq_data *data); 668 extern void irq_chip_eoi_parent(struct irq_data *data); 669 extern int irq_chip_set_affinity_parent(struct irq_data *data, 670 const struct cpumask *dest, 671 bool force); 672 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); 673 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, 674 void *vcpu_info); 675 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); 676 extern int irq_chip_request_resources_parent(struct irq_data *data); 677 extern void irq_chip_release_resources_parent(struct irq_data *data); 678 #endif 679 680 /* Handling of unhandled and spurious interrupts: */ 681 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret); 682 683 684 /* Enable/disable irq debugging output: */ 685 extern int noirqdebug_setup(char *str); 686 687 /* Checks whether the interrupt can be requested by request_irq(): */ 688 extern int can_request_irq(unsigned int irq, unsigned long irqflags); 689 690 /* Dummy irq-chip implementations: */ 691 extern struct irq_chip no_irq_chip; 692 extern struct irq_chip dummy_irq_chip; 693 694 extern void 695 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, 696 irq_flow_handler_t handle, const char *name); 697 698 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, 699 irq_flow_handler_t handle) 700 { 701 irq_set_chip_and_handler_name(irq, chip, handle, NULL); 702 } 703 704 extern int irq_set_percpu_devid(unsigned int irq); 705 extern int irq_set_percpu_devid_partition(unsigned int irq, 706 const struct cpumask *affinity); 707 extern int irq_get_percpu_devid_partition(unsigned int irq, 708 struct cpumask *affinity); 709 710 extern void 711 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, 712 const char *name); 713 714 static inline void 715 irq_set_handler(unsigned int irq, irq_flow_handler_t handle) 716 { 717 __irq_set_handler(irq, handle, 0, NULL); 718 } 719 720 /* 721 * Set a highlevel chained flow handler for a given IRQ. 722 * (a chained handler is automatically enabled and set to 723 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 724 */ 725 static inline void 726 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) 727 { 728 __irq_set_handler(irq, handle, 1, NULL); 729 } 730 731 /* 732 * Set a highlevel chained flow handler and its data for a given IRQ. 733 * (a chained handler is automatically enabled and set to 734 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 735 */ 736 void 737 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, 738 void *data); 739 740 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); 741 742 static inline void irq_set_status_flags(unsigned int irq, unsigned long set) 743 { 744 irq_modify_status(irq, 0, set); 745 } 746 747 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) 748 { 749 irq_modify_status(irq, clr, 0); 750 } 751 752 static inline void irq_set_noprobe(unsigned int irq) 753 { 754 irq_modify_status(irq, 0, IRQ_NOPROBE); 755 } 756 757 static inline void irq_set_probe(unsigned int irq) 758 { 759 irq_modify_status(irq, IRQ_NOPROBE, 0); 760 } 761 762 static inline void irq_set_nothread(unsigned int irq) 763 { 764 irq_modify_status(irq, 0, IRQ_NOTHREAD); 765 } 766 767 static inline void irq_set_thread(unsigned int irq) 768 { 769 irq_modify_status(irq, IRQ_NOTHREAD, 0); 770 } 771 772 static inline void irq_set_nested_thread(unsigned int irq, bool nest) 773 { 774 if (nest) 775 irq_set_status_flags(irq, IRQ_NESTED_THREAD); 776 else 777 irq_clear_status_flags(irq, IRQ_NESTED_THREAD); 778 } 779 780 static inline void irq_set_percpu_devid_flags(unsigned int irq) 781 { 782 irq_set_status_flags(irq, 783 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | 784 IRQ_NOPROBE | IRQ_PER_CPU_DEVID); 785 } 786 787 /* Set/get chip/data for an IRQ: */ 788 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); 789 extern int irq_set_handler_data(unsigned int irq, void *data); 790 extern int irq_set_chip_data(unsigned int irq, void *data); 791 extern int irq_set_irq_type(unsigned int irq, unsigned int type); 792 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 793 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, 794 struct msi_desc *entry); 795 extern struct irq_data *irq_get_irq_data(unsigned int irq); 796 797 static inline struct irq_chip *irq_get_chip(unsigned int irq) 798 { 799 struct irq_data *d = irq_get_irq_data(irq); 800 return d ? d->chip : NULL; 801 } 802 803 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) 804 { 805 return d->chip; 806 } 807 808 static inline void *irq_get_chip_data(unsigned int irq) 809 { 810 struct irq_data *d = irq_get_irq_data(irq); 811 return d ? d->chip_data : NULL; 812 } 813 814 static inline void *irq_data_get_irq_chip_data(struct irq_data *d) 815 { 816 return d->chip_data; 817 } 818 819 static inline void *irq_get_handler_data(unsigned int irq) 820 { 821 struct irq_data *d = irq_get_irq_data(irq); 822 return d ? d->common->handler_data : NULL; 823 } 824 825 static inline void *irq_data_get_irq_handler_data(struct irq_data *d) 826 { 827 return d->common->handler_data; 828 } 829 830 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) 831 { 832 struct irq_data *d = irq_get_irq_data(irq); 833 return d ? d->common->msi_desc : NULL; 834 } 835 836 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d) 837 { 838 return d->common->msi_desc; 839 } 840 841 static inline u32 irq_get_trigger_type(unsigned int irq) 842 { 843 struct irq_data *d = irq_get_irq_data(irq); 844 return d ? irqd_get_trigger_type(d) : 0; 845 } 846 847 static inline int irq_common_data_get_node(struct irq_common_data *d) 848 { 849 #ifdef CONFIG_NUMA 850 return d->node; 851 #else 852 return 0; 853 #endif 854 } 855 856 static inline int irq_data_get_node(struct irq_data *d) 857 { 858 return irq_common_data_get_node(d->common); 859 } 860 861 static inline struct cpumask *irq_get_affinity_mask(int irq) 862 { 863 struct irq_data *d = irq_get_irq_data(irq); 864 865 return d ? d->common->affinity : NULL; 866 } 867 868 static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d) 869 { 870 return d->common->affinity; 871 } 872 873 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 874 static inline 875 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 876 { 877 return d->common->effective_affinity; 878 } 879 static inline void irq_data_update_effective_affinity(struct irq_data *d, 880 const struct cpumask *m) 881 { 882 cpumask_copy(d->common->effective_affinity, m); 883 } 884 #else 885 static inline void irq_data_update_effective_affinity(struct irq_data *d, 886 const struct cpumask *m) 887 { 888 } 889 static inline 890 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 891 { 892 return d->common->affinity; 893 } 894 #endif 895 896 unsigned int arch_dynirq_lower_bound(unsigned int from); 897 898 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, 899 struct module *owner, 900 const struct irq_affinity_desc *affinity); 901 902 int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from, 903 unsigned int cnt, int node, struct module *owner, 904 const struct irq_affinity_desc *affinity); 905 906 /* use macros to avoid needing export.h for THIS_MODULE */ 907 #define irq_alloc_descs(irq, from, cnt, node) \ 908 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL) 909 910 #define irq_alloc_desc(node) \ 911 irq_alloc_descs(-1, 0, 1, node) 912 913 #define irq_alloc_desc_at(at, node) \ 914 irq_alloc_descs(at, at, 1, node) 915 916 #define irq_alloc_desc_from(from, node) \ 917 irq_alloc_descs(-1, from, 1, node) 918 919 #define irq_alloc_descs_from(from, cnt, node) \ 920 irq_alloc_descs(-1, from, cnt, node) 921 922 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \ 923 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL) 924 925 #define devm_irq_alloc_desc(dev, node) \ 926 devm_irq_alloc_descs(dev, -1, 0, 1, node) 927 928 #define devm_irq_alloc_desc_at(dev, at, node) \ 929 devm_irq_alloc_descs(dev, at, at, 1, node) 930 931 #define devm_irq_alloc_desc_from(dev, from, node) \ 932 devm_irq_alloc_descs(dev, -1, from, 1, node) 933 934 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \ 935 devm_irq_alloc_descs(dev, -1, from, cnt, node) 936 937 void irq_free_descs(unsigned int irq, unsigned int cnt); 938 static inline void irq_free_desc(unsigned int irq) 939 { 940 irq_free_descs(irq, 1); 941 } 942 943 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ 944 unsigned int irq_alloc_hwirqs(int cnt, int node); 945 static inline unsigned int irq_alloc_hwirq(int node) 946 { 947 return irq_alloc_hwirqs(1, node); 948 } 949 void irq_free_hwirqs(unsigned int from, int cnt); 950 static inline void irq_free_hwirq(unsigned int irq) 951 { 952 return irq_free_hwirqs(irq, 1); 953 } 954 int arch_setup_hwirq(unsigned int irq, int node); 955 void arch_teardown_hwirq(unsigned int irq); 956 #endif 957 958 #ifdef CONFIG_GENERIC_IRQ_LEGACY 959 void irq_init_desc(unsigned int irq); 960 #endif 961 962 /** 963 * struct irq_chip_regs - register offsets for struct irq_gci 964 * @enable: Enable register offset to reg_base 965 * @disable: Disable register offset to reg_base 966 * @mask: Mask register offset to reg_base 967 * @ack: Ack register offset to reg_base 968 * @eoi: Eoi register offset to reg_base 969 * @type: Type configuration register offset to reg_base 970 * @polarity: Polarity configuration register offset to reg_base 971 */ 972 struct irq_chip_regs { 973 unsigned long enable; 974 unsigned long disable; 975 unsigned long mask; 976 unsigned long ack; 977 unsigned long eoi; 978 unsigned long type; 979 unsigned long polarity; 980 }; 981 982 /** 983 * struct irq_chip_type - Generic interrupt chip instance for a flow type 984 * @chip: The real interrupt chip which provides the callbacks 985 * @regs: Register offsets for this chip 986 * @handler: Flow handler associated with this chip 987 * @type: Chip can handle these flow types 988 * @mask_cache_priv: Cached mask register private to the chip type 989 * @mask_cache: Pointer to cached mask register 990 * 991 * A irq_generic_chip can have several instances of irq_chip_type when 992 * it requires different functions and register offsets for different 993 * flow types. 994 */ 995 struct irq_chip_type { 996 struct irq_chip chip; 997 struct irq_chip_regs regs; 998 irq_flow_handler_t handler; 999 u32 type; 1000 u32 mask_cache_priv; 1001 u32 *mask_cache; 1002 }; 1003 1004 /** 1005 * struct irq_chip_generic - Generic irq chip data structure 1006 * @lock: Lock to protect register and cache data access 1007 * @reg_base: Register base address (virtual) 1008 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL) 1009 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL) 1010 * @suspend: Function called from core code on suspend once per 1011 * chip; can be useful instead of irq_chip::suspend to 1012 * handle chip details even when no interrupts are in use 1013 * @resume: Function called from core code on resume once per chip; 1014 * can be useful instead of irq_chip::suspend to handle 1015 * chip details even when no interrupts are in use 1016 * @irq_base: Interrupt base nr for this chip 1017 * @irq_cnt: Number of interrupts handled by this chip 1018 * @mask_cache: Cached mask register shared between all chip types 1019 * @type_cache: Cached type register 1020 * @polarity_cache: Cached polarity register 1021 * @wake_enabled: Interrupt can wakeup from suspend 1022 * @wake_active: Interrupt is marked as an wakeup from suspend source 1023 * @num_ct: Number of available irq_chip_type instances (usually 1) 1024 * @private: Private data for non generic chip callbacks 1025 * @installed: bitfield to denote installed interrupts 1026 * @unused: bitfield to denote unused interrupts 1027 * @domain: irq domain pointer 1028 * @list: List head for keeping track of instances 1029 * @chip_types: Array of interrupt irq_chip_types 1030 * 1031 * Note, that irq_chip_generic can have multiple irq_chip_type 1032 * implementations which can be associated to a particular irq line of 1033 * an irq_chip_generic instance. That allows to share and protect 1034 * state in an irq_chip_generic instance when we need to implement 1035 * different flow mechanisms (level/edge) for it. 1036 */ 1037 struct irq_chip_generic { 1038 raw_spinlock_t lock; 1039 void __iomem *reg_base; 1040 u32 (*reg_readl)(void __iomem *addr); 1041 void (*reg_writel)(u32 val, void __iomem *addr); 1042 void (*suspend)(struct irq_chip_generic *gc); 1043 void (*resume)(struct irq_chip_generic *gc); 1044 unsigned int irq_base; 1045 unsigned int irq_cnt; 1046 u32 mask_cache; 1047 u32 type_cache; 1048 u32 polarity_cache; 1049 u32 wake_enabled; 1050 u32 wake_active; 1051 unsigned int num_ct; 1052 void *private; 1053 unsigned long installed; 1054 unsigned long unused; 1055 struct irq_domain *domain; 1056 struct list_head list; 1057 struct irq_chip_type chip_types[]; 1058 }; 1059 1060 /** 1061 * enum irq_gc_flags - Initialization flags for generic irq chips 1062 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg 1063 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for 1064 * irq chips which need to call irq_set_wake() on 1065 * the parent irq. Usually GPIO implementations 1066 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private 1067 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask 1068 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE) 1069 */ 1070 enum irq_gc_flags { 1071 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 1072 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 1073 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, 1074 IRQ_GC_NO_MASK = 1 << 3, 1075 IRQ_GC_BE_IO = 1 << 4, 1076 }; 1077 1078 /* 1079 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains 1080 * @irqs_per_chip: Number of interrupts per chip 1081 * @num_chips: Number of chips 1082 * @irq_flags_to_set: IRQ* flags to set on irq setup 1083 * @irq_flags_to_clear: IRQ* flags to clear on irq setup 1084 * @gc_flags: Generic chip specific setup flags 1085 * @gc: Array of pointers to generic interrupt chips 1086 */ 1087 struct irq_domain_chip_generic { 1088 unsigned int irqs_per_chip; 1089 unsigned int num_chips; 1090 unsigned int irq_flags_to_clear; 1091 unsigned int irq_flags_to_set; 1092 enum irq_gc_flags gc_flags; 1093 struct irq_chip_generic *gc[]; 1094 }; 1095 1096 /* Generic chip callback functions */ 1097 void irq_gc_noop(struct irq_data *d); 1098 void irq_gc_mask_disable_reg(struct irq_data *d); 1099 void irq_gc_mask_set_bit(struct irq_data *d); 1100 void irq_gc_mask_clr_bit(struct irq_data *d); 1101 void irq_gc_unmask_enable_reg(struct irq_data *d); 1102 void irq_gc_ack_set_bit(struct irq_data *d); 1103 void irq_gc_ack_clr_bit(struct irq_data *d); 1104 void irq_gc_mask_disable_and_ack_set(struct irq_data *d); 1105 void irq_gc_eoi(struct irq_data *d); 1106 int irq_gc_set_wake(struct irq_data *d, unsigned int on); 1107 1108 /* Setup functions for irq_chip_generic */ 1109 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, 1110 irq_hw_number_t hw_irq); 1111 struct irq_chip_generic * 1112 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, 1113 void __iomem *reg_base, irq_flow_handler_t handler); 1114 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 1115 enum irq_gc_flags flags, unsigned int clr, 1116 unsigned int set); 1117 int irq_setup_alt_chip(struct irq_data *d, unsigned int type); 1118 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 1119 unsigned int clr, unsigned int set); 1120 1121 struct irq_chip_generic * 1122 devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct, 1123 unsigned int irq_base, void __iomem *reg_base, 1124 irq_flow_handler_t handler); 1125 int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc, 1126 u32 msk, enum irq_gc_flags flags, 1127 unsigned int clr, unsigned int set); 1128 1129 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); 1130 1131 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, 1132 int num_ct, const char *name, 1133 irq_flow_handler_t handler, 1134 unsigned int clr, unsigned int set, 1135 enum irq_gc_flags flags); 1136 1137 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \ 1138 handler, clr, set, flags) \ 1139 ({ \ 1140 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \ 1141 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\ 1142 handler, clr, set, flags); \ 1143 }) 1144 1145 static inline void irq_free_generic_chip(struct irq_chip_generic *gc) 1146 { 1147 kfree(gc); 1148 } 1149 1150 static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc, 1151 u32 msk, unsigned int clr, 1152 unsigned int set) 1153 { 1154 irq_remove_generic_chip(gc, msk, clr, set); 1155 irq_free_generic_chip(gc); 1156 } 1157 1158 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) 1159 { 1160 return container_of(d->chip, struct irq_chip_type, chip); 1161 } 1162 1163 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) 1164 1165 #ifdef CONFIG_SMP 1166 static inline void irq_gc_lock(struct irq_chip_generic *gc) 1167 { 1168 raw_spin_lock(&gc->lock); 1169 } 1170 1171 static inline void irq_gc_unlock(struct irq_chip_generic *gc) 1172 { 1173 raw_spin_unlock(&gc->lock); 1174 } 1175 #else 1176 static inline void irq_gc_lock(struct irq_chip_generic *gc) { } 1177 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } 1178 #endif 1179 1180 /* 1181 * The irqsave variants are for usage in non interrupt code. Do not use 1182 * them in irq_chip callbacks. Use irq_gc_lock() instead. 1183 */ 1184 #define irq_gc_lock_irqsave(gc, flags) \ 1185 raw_spin_lock_irqsave(&(gc)->lock, flags) 1186 1187 #define irq_gc_unlock_irqrestore(gc, flags) \ 1188 raw_spin_unlock_irqrestore(&(gc)->lock, flags) 1189 1190 static inline void irq_reg_writel(struct irq_chip_generic *gc, 1191 u32 val, int reg_offset) 1192 { 1193 if (gc->reg_writel) 1194 gc->reg_writel(val, gc->reg_base + reg_offset); 1195 else 1196 writel(val, gc->reg_base + reg_offset); 1197 } 1198 1199 static inline u32 irq_reg_readl(struct irq_chip_generic *gc, 1200 int reg_offset) 1201 { 1202 if (gc->reg_readl) 1203 return gc->reg_readl(gc->reg_base + reg_offset); 1204 else 1205 return readl(gc->reg_base + reg_offset); 1206 } 1207 1208 struct irq_matrix; 1209 struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits, 1210 unsigned int alloc_start, 1211 unsigned int alloc_end); 1212 void irq_matrix_online(struct irq_matrix *m); 1213 void irq_matrix_offline(struct irq_matrix *m); 1214 void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace); 1215 int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk); 1216 void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk); 1217 int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk, 1218 unsigned int *mapped_cpu); 1219 void irq_matrix_reserve(struct irq_matrix *m); 1220 void irq_matrix_remove_reserved(struct irq_matrix *m); 1221 int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk, 1222 bool reserved, unsigned int *mapped_cpu); 1223 void irq_matrix_free(struct irq_matrix *m, unsigned int cpu, 1224 unsigned int bit, bool managed); 1225 void irq_matrix_assign(struct irq_matrix *m, unsigned int bit); 1226 unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown); 1227 unsigned int irq_matrix_allocated(struct irq_matrix *m); 1228 unsigned int irq_matrix_reserved(struct irq_matrix *m); 1229 void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind); 1230 1231 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */ 1232 #define INVALID_HWIRQ (~0UL) 1233 irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu); 1234 int __ipi_send_single(struct irq_desc *desc, unsigned int cpu); 1235 int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest); 1236 int ipi_send_single(unsigned int virq, unsigned int cpu); 1237 int ipi_send_mask(unsigned int virq, const struct cpumask *dest); 1238 1239 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER 1240 /* 1241 * Registers a generic IRQ handling function as the top-level IRQ handler in 1242 * the system, which is generally the first C code called from an assembly 1243 * architecture-specific interrupt handler. 1244 * 1245 * Returns 0 on success, or -EBUSY if an IRQ handler has already been 1246 * registered. 1247 */ 1248 int __init set_handle_irq(void (*handle_irq)(struct pt_regs *)); 1249 1250 /* 1251 * Allows interrupt handlers to find the irqchip that's been registered as the 1252 * top-level IRQ handler. 1253 */ 1254 extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init; 1255 #endif 1256 1257 #endif /* _LINUX_IRQ_H */ 1258