1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_IRQ_H 3 #define _LINUX_IRQ_H 4 5 /* 6 * Please do not include this file in generic code. There is currently 7 * no requirement for any architecture to implement anything held 8 * within this file. 9 * 10 * Thanks. --rmk 11 */ 12 13 #include <linux/cache.h> 14 #include <linux/spinlock.h> 15 #include <linux/cpumask.h> 16 #include <linux/irqhandler.h> 17 #include <linux/irqreturn.h> 18 #include <linux/irqnr.h> 19 #include <linux/topology.h> 20 #include <linux/io.h> 21 #include <linux/slab.h> 22 23 #include <asm/irq.h> 24 #include <asm/ptrace.h> 25 #include <asm/irq_regs.h> 26 27 struct seq_file; 28 struct module; 29 struct msi_msg; 30 struct irq_affinity_desc; 31 enum irqchip_irq_state; 32 33 /* 34 * IRQ line status. 35 * 36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h 37 * 38 * IRQ_TYPE_NONE - default, unspecified type 39 * IRQ_TYPE_EDGE_RISING - rising edge triggered 40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered 41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 42 * IRQ_TYPE_LEVEL_HIGH - high level triggered 43 * IRQ_TYPE_LEVEL_LOW - low level triggered 44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 45 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits 46 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type 47 * to setup the HW to a sane default (used 48 * by irqdomain map() callbacks to synchronize 49 * the HW state and SW flags for a newly 50 * allocated descriptor). 51 * 52 * IRQ_TYPE_PROBE - Special flag for probing in progress 53 * 54 * Bits which can be modified via irq_set/clear/modify_status_flags() 55 * IRQ_LEVEL - Interrupt is level type. Will be also 56 * updated in the code when the above trigger 57 * bits are modified via irq_set_irq_type() 58 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect 59 * it from affinity setting 60 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing 61 * IRQ_NOREQUEST - Interrupt cannot be requested via 62 * request_irq() 63 * IRQ_NOTHREAD - Interrupt cannot be threaded 64 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in 65 * request/setup_irq() 66 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) 67 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context 68 * IRQ_NESTED_THREAD - Interrupt nests into another thread 69 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable 70 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude 71 * it from the spurious interrupt detection 72 * mechanism and from core side polling. 73 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable 74 */ 75 enum { 76 IRQ_TYPE_NONE = 0x00000000, 77 IRQ_TYPE_EDGE_RISING = 0x00000001, 78 IRQ_TYPE_EDGE_FALLING = 0x00000002, 79 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), 80 IRQ_TYPE_LEVEL_HIGH = 0x00000004, 81 IRQ_TYPE_LEVEL_LOW = 0x00000008, 82 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), 83 IRQ_TYPE_SENSE_MASK = 0x0000000f, 84 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, 85 86 IRQ_TYPE_PROBE = 0x00000010, 87 88 IRQ_LEVEL = (1 << 8), 89 IRQ_PER_CPU = (1 << 9), 90 IRQ_NOPROBE = (1 << 10), 91 IRQ_NOREQUEST = (1 << 11), 92 IRQ_NOAUTOEN = (1 << 12), 93 IRQ_NO_BALANCING = (1 << 13), 94 IRQ_MOVE_PCNTXT = (1 << 14), 95 IRQ_NESTED_THREAD = (1 << 15), 96 IRQ_NOTHREAD = (1 << 16), 97 IRQ_PER_CPU_DEVID = (1 << 17), 98 IRQ_IS_POLLED = (1 << 18), 99 IRQ_DISABLE_UNLAZY = (1 << 19), 100 }; 101 102 #define IRQF_MODIFY_MASK \ 103 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ 104 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ 105 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ 106 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY) 107 108 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 109 110 /* 111 * Return value for chip->irq_set_affinity() 112 * 113 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity 114 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity 115 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to 116 * support stacked irqchips, which indicates skipping 117 * all descendent irqchips. 118 */ 119 enum { 120 IRQ_SET_MASK_OK = 0, 121 IRQ_SET_MASK_OK_NOCOPY, 122 IRQ_SET_MASK_OK_DONE, 123 }; 124 125 struct msi_desc; 126 struct irq_domain; 127 128 /** 129 * struct irq_common_data - per irq data shared by all irqchips 130 * @state_use_accessors: status information for irq chip functions. 131 * Use accessor functions to deal with it 132 * @node: node index useful for balancing 133 * @handler_data: per-IRQ data for the irq_chip methods 134 * @affinity: IRQ affinity on SMP. If this is an IPI 135 * related irq, then this is the mask of the 136 * CPUs to which an IPI can be sent. 137 * @effective_affinity: The effective IRQ affinity on SMP as some irq 138 * chips do not allow multi CPU destinations. 139 * A subset of @affinity. 140 * @msi_desc: MSI descriptor 141 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional. 142 */ 143 struct irq_common_data { 144 unsigned int __private state_use_accessors; 145 #ifdef CONFIG_NUMA 146 unsigned int node; 147 #endif 148 void *handler_data; 149 struct msi_desc *msi_desc; 150 cpumask_var_t affinity; 151 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 152 cpumask_var_t effective_affinity; 153 #endif 154 #ifdef CONFIG_GENERIC_IRQ_IPI 155 unsigned int ipi_offset; 156 #endif 157 }; 158 159 /** 160 * struct irq_data - per irq chip data passed down to chip functions 161 * @mask: precomputed bitmask for accessing the chip registers 162 * @irq: interrupt number 163 * @hwirq: hardware interrupt number, local to the interrupt domain 164 * @common: point to data shared by all irqchips 165 * @chip: low level interrupt hardware access 166 * @domain: Interrupt translation domain; responsible for mapping 167 * between hwirq number and linux irq number. 168 * @parent_data: pointer to parent struct irq_data to support hierarchy 169 * irq_domain 170 * @chip_data: platform-specific per-chip private data for the chip 171 * methods, to allow shared chip implementations 172 */ 173 struct irq_data { 174 u32 mask; 175 unsigned int irq; 176 unsigned long hwirq; 177 struct irq_common_data *common; 178 struct irq_chip *chip; 179 struct irq_domain *domain; 180 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 181 struct irq_data *parent_data; 182 #endif 183 void *chip_data; 184 }; 185 186 /* 187 * Bit masks for irq_common_data.state_use_accessors 188 * 189 * IRQD_TRIGGER_MASK - Mask for the trigger type bits 190 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 191 * IRQD_ACTIVATED - Interrupt has already been activated 192 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 193 * IRQD_PER_CPU - Interrupt is per cpu 194 * IRQD_AFFINITY_SET - Interrupt affinity was set 195 * IRQD_LEVEL - Interrupt is level triggered 196 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup 197 * from suspend 198 * IRQD_MOVE_PCNTXT - Interrupt can be moved in process 199 * context 200 * IRQD_IRQ_DISABLED - Disabled state of the interrupt 201 * IRQD_IRQ_MASKED - Masked state of the interrupt 202 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt 203 * IRQD_WAKEUP_ARMED - Wakeup mode armed 204 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU 205 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel 206 * IRQD_IRQ_STARTED - Startup state of the interrupt 207 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity 208 * mask. Applies only to affinity managed irqs. 209 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target 210 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set 211 * IRQD_CAN_RESERVE - Can use reservation mode 212 * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change 213 * required 214 */ 215 enum { 216 IRQD_TRIGGER_MASK = 0xf, 217 IRQD_SETAFFINITY_PENDING = (1 << 8), 218 IRQD_ACTIVATED = (1 << 9), 219 IRQD_NO_BALANCING = (1 << 10), 220 IRQD_PER_CPU = (1 << 11), 221 IRQD_AFFINITY_SET = (1 << 12), 222 IRQD_LEVEL = (1 << 13), 223 IRQD_WAKEUP_STATE = (1 << 14), 224 IRQD_MOVE_PCNTXT = (1 << 15), 225 IRQD_IRQ_DISABLED = (1 << 16), 226 IRQD_IRQ_MASKED = (1 << 17), 227 IRQD_IRQ_INPROGRESS = (1 << 18), 228 IRQD_WAKEUP_ARMED = (1 << 19), 229 IRQD_FORWARDED_TO_VCPU = (1 << 20), 230 IRQD_AFFINITY_MANAGED = (1 << 21), 231 IRQD_IRQ_STARTED = (1 << 22), 232 IRQD_MANAGED_SHUTDOWN = (1 << 23), 233 IRQD_SINGLE_TARGET = (1 << 24), 234 IRQD_DEFAULT_TRIGGER_SET = (1 << 25), 235 IRQD_CAN_RESERVE = (1 << 26), 236 IRQD_MSI_NOMASK_QUIRK = (1 << 27), 237 }; 238 239 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors) 240 241 static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 242 { 243 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING; 244 } 245 246 static inline bool irqd_is_per_cpu(struct irq_data *d) 247 { 248 return __irqd_to_state(d) & IRQD_PER_CPU; 249 } 250 251 static inline bool irqd_can_balance(struct irq_data *d) 252 { 253 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); 254 } 255 256 static inline bool irqd_affinity_was_set(struct irq_data *d) 257 { 258 return __irqd_to_state(d) & IRQD_AFFINITY_SET; 259 } 260 261 static inline void irqd_mark_affinity_was_set(struct irq_data *d) 262 { 263 __irqd_to_state(d) |= IRQD_AFFINITY_SET; 264 } 265 266 static inline bool irqd_trigger_type_was_set(struct irq_data *d) 267 { 268 return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET; 269 } 270 271 static inline u32 irqd_get_trigger_type(struct irq_data *d) 272 { 273 return __irqd_to_state(d) & IRQD_TRIGGER_MASK; 274 } 275 276 /* 277 * Must only be called inside irq_chip.irq_set_type() functions or 278 * from the DT/ACPI setup code. 279 */ 280 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) 281 { 282 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK; 283 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK; 284 __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET; 285 } 286 287 static inline bool irqd_is_level_type(struct irq_data *d) 288 { 289 return __irqd_to_state(d) & IRQD_LEVEL; 290 } 291 292 /* 293 * Must only be called of irqchip.irq_set_affinity() or low level 294 * hieararchy domain allocation functions. 295 */ 296 static inline void irqd_set_single_target(struct irq_data *d) 297 { 298 __irqd_to_state(d) |= IRQD_SINGLE_TARGET; 299 } 300 301 static inline bool irqd_is_single_target(struct irq_data *d) 302 { 303 return __irqd_to_state(d) & IRQD_SINGLE_TARGET; 304 } 305 306 static inline bool irqd_is_wakeup_set(struct irq_data *d) 307 { 308 return __irqd_to_state(d) & IRQD_WAKEUP_STATE; 309 } 310 311 static inline bool irqd_can_move_in_process_context(struct irq_data *d) 312 { 313 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT; 314 } 315 316 static inline bool irqd_irq_disabled(struct irq_data *d) 317 { 318 return __irqd_to_state(d) & IRQD_IRQ_DISABLED; 319 } 320 321 static inline bool irqd_irq_masked(struct irq_data *d) 322 { 323 return __irqd_to_state(d) & IRQD_IRQ_MASKED; 324 } 325 326 static inline bool irqd_irq_inprogress(struct irq_data *d) 327 { 328 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; 329 } 330 331 static inline bool irqd_is_wakeup_armed(struct irq_data *d) 332 { 333 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED; 334 } 335 336 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d) 337 { 338 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU; 339 } 340 341 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d) 342 { 343 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU; 344 } 345 346 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d) 347 { 348 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; 349 } 350 351 static inline bool irqd_affinity_is_managed(struct irq_data *d) 352 { 353 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED; 354 } 355 356 static inline bool irqd_is_activated(struct irq_data *d) 357 { 358 return __irqd_to_state(d) & IRQD_ACTIVATED; 359 } 360 361 static inline void irqd_set_activated(struct irq_data *d) 362 { 363 __irqd_to_state(d) |= IRQD_ACTIVATED; 364 } 365 366 static inline void irqd_clr_activated(struct irq_data *d) 367 { 368 __irqd_to_state(d) &= ~IRQD_ACTIVATED; 369 } 370 371 static inline bool irqd_is_started(struct irq_data *d) 372 { 373 return __irqd_to_state(d) & IRQD_IRQ_STARTED; 374 } 375 376 static inline bool irqd_is_managed_and_shutdown(struct irq_data *d) 377 { 378 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN; 379 } 380 381 static inline void irqd_set_can_reserve(struct irq_data *d) 382 { 383 __irqd_to_state(d) |= IRQD_CAN_RESERVE; 384 } 385 386 static inline void irqd_clr_can_reserve(struct irq_data *d) 387 { 388 __irqd_to_state(d) &= ~IRQD_CAN_RESERVE; 389 } 390 391 static inline bool irqd_can_reserve(struct irq_data *d) 392 { 393 return __irqd_to_state(d) & IRQD_CAN_RESERVE; 394 } 395 396 static inline void irqd_set_msi_nomask_quirk(struct irq_data *d) 397 { 398 __irqd_to_state(d) |= IRQD_MSI_NOMASK_QUIRK; 399 } 400 401 static inline void irqd_clr_msi_nomask_quirk(struct irq_data *d) 402 { 403 __irqd_to_state(d) &= ~IRQD_MSI_NOMASK_QUIRK; 404 } 405 406 static inline bool irqd_msi_nomask_quirk(struct irq_data *d) 407 { 408 return __irqd_to_state(d) & IRQD_MSI_NOMASK_QUIRK; 409 } 410 411 #undef __irqd_to_state 412 413 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) 414 { 415 return d->hwirq; 416 } 417 418 /** 419 * struct irq_chip - hardware interrupt chip descriptor 420 * 421 * @parent_device: pointer to parent device for irqchip 422 * @name: name for /proc/interrupts 423 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 424 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 425 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) 426 * @irq_disable: disable the interrupt 427 * @irq_ack: start of a new interrupt 428 * @irq_mask: mask an interrupt source 429 * @irq_mask_ack: ack and mask an interrupt source 430 * @irq_unmask: unmask an interrupt source 431 * @irq_eoi: end of interrupt 432 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force 433 * argument is true, it tells the driver to 434 * unconditionally apply the affinity setting. Sanity 435 * checks against the supplied affinity mask are not 436 * required. This is used for CPU hotplug where the 437 * target CPU is not yet set in the cpu_online_mask. 438 * @irq_retrigger: resend an IRQ to the CPU 439 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ 440 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 441 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 442 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 443 * @irq_cpu_online: configure an interrupt source for a secondary CPU 444 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU 445 * @irq_suspend: function called from core code on suspend once per 446 * chip, when one or more interrupts are installed 447 * @irq_resume: function called from core code on resume once per chip, 448 * when one ore more interrupts are installed 449 * @irq_pm_shutdown: function called from core code on shutdown once per chip 450 * @irq_calc_mask: Optional function to set irq_data.mask for special cases 451 * @irq_print_chip: optional to print special chip info in show_interrupts 452 * @irq_request_resources: optional to request resources before calling 453 * any other callback related to this irq 454 * @irq_release_resources: optional to release resources acquired with 455 * irq_request_resources 456 * @irq_compose_msi_msg: optional to compose message content for MSI 457 * @irq_write_msi_msg: optional to write message content for MSI 458 * @irq_get_irqchip_state: return the internal state of an interrupt 459 * @irq_set_irqchip_state: set the internal state of a interrupt 460 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine 461 * @ipi_send_single: send a single IPI to destination cpus 462 * @ipi_send_mask: send an IPI to destination cpus in cpumask 463 * @irq_nmi_setup: function called from core code before enabling an NMI 464 * @irq_nmi_teardown: function called from core code after disabling an NMI 465 * @flags: chip specific flags 466 */ 467 struct irq_chip { 468 struct device *parent_device; 469 const char *name; 470 unsigned int (*irq_startup)(struct irq_data *data); 471 void (*irq_shutdown)(struct irq_data *data); 472 void (*irq_enable)(struct irq_data *data); 473 void (*irq_disable)(struct irq_data *data); 474 475 void (*irq_ack)(struct irq_data *data); 476 void (*irq_mask)(struct irq_data *data); 477 void (*irq_mask_ack)(struct irq_data *data); 478 void (*irq_unmask)(struct irq_data *data); 479 void (*irq_eoi)(struct irq_data *data); 480 481 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); 482 int (*irq_retrigger)(struct irq_data *data); 483 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); 484 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 485 486 void (*irq_bus_lock)(struct irq_data *data); 487 void (*irq_bus_sync_unlock)(struct irq_data *data); 488 489 void (*irq_cpu_online)(struct irq_data *data); 490 void (*irq_cpu_offline)(struct irq_data *data); 491 492 void (*irq_suspend)(struct irq_data *data); 493 void (*irq_resume)(struct irq_data *data); 494 void (*irq_pm_shutdown)(struct irq_data *data); 495 496 void (*irq_calc_mask)(struct irq_data *data); 497 498 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 499 int (*irq_request_resources)(struct irq_data *data); 500 void (*irq_release_resources)(struct irq_data *data); 501 502 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); 503 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); 504 505 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); 506 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); 507 508 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); 509 510 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); 511 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); 512 513 int (*irq_nmi_setup)(struct irq_data *data); 514 void (*irq_nmi_teardown)(struct irq_data *data); 515 516 unsigned long flags; 517 }; 518 519 /* 520 * irq_chip specific flags 521 * 522 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() 523 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled 524 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path 525 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks 526 * when irq enabled 527 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip 528 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask 529 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode 530 * IRQCHIP_SUPPORTS_LEVEL_MSI Chip can provide two doorbells for Level MSIs 531 * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips 532 */ 533 enum { 534 IRQCHIP_SET_TYPE_MASKED = (1 << 0), 535 IRQCHIP_EOI_IF_HANDLED = (1 << 1), 536 IRQCHIP_MASK_ON_SUSPEND = (1 << 2), 537 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), 538 IRQCHIP_SKIP_SET_WAKE = (1 << 4), 539 IRQCHIP_ONESHOT_SAFE = (1 << 5), 540 IRQCHIP_EOI_THREADED = (1 << 6), 541 IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7), 542 IRQCHIP_SUPPORTS_NMI = (1 << 8), 543 }; 544 545 #include <linux/irqdesc.h> 546 547 /* 548 * Pick up the arch-dependent methods: 549 */ 550 #include <asm/hw_irq.h> 551 552 #ifndef NR_IRQS_LEGACY 553 # define NR_IRQS_LEGACY 0 554 #endif 555 556 #ifndef ARCH_IRQ_INIT_FLAGS 557 # define ARCH_IRQ_INIT_FLAGS 0 558 #endif 559 560 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS 561 562 struct irqaction; 563 extern int setup_irq(unsigned int irq, struct irqaction *new); 564 extern void remove_irq(unsigned int irq, struct irqaction *act); 565 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); 566 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); 567 568 extern void irq_cpu_online(void); 569 extern void irq_cpu_offline(void); 570 extern int irq_set_affinity_locked(struct irq_data *data, 571 const struct cpumask *cpumask, bool force); 572 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info); 573 574 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION) 575 extern void irq_migrate_all_off_this_cpu(void); 576 extern int irq_affinity_online_cpu(unsigned int cpu); 577 #else 578 # define irq_affinity_online_cpu NULL 579 #endif 580 581 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) 582 void __irq_move_irq(struct irq_data *data); 583 static inline void irq_move_irq(struct irq_data *data) 584 { 585 if (unlikely(irqd_is_setaffinity_pending(data))) 586 __irq_move_irq(data); 587 } 588 void irq_move_masked_irq(struct irq_data *data); 589 void irq_force_complete_move(struct irq_desc *desc); 590 #else 591 static inline void irq_move_irq(struct irq_data *data) { } 592 static inline void irq_move_masked_irq(struct irq_data *data) { } 593 static inline void irq_force_complete_move(struct irq_desc *desc) { } 594 #endif 595 596 extern int no_irq_affinity; 597 598 #ifdef CONFIG_HARDIRQS_SW_RESEND 599 int irq_set_parent(int irq, int parent_irq); 600 #else 601 static inline int irq_set_parent(int irq, int parent_irq) 602 { 603 return 0; 604 } 605 #endif 606 607 /* 608 * Built-in IRQ handlers for various IRQ types, 609 * callable via desc->handle_irq() 610 */ 611 extern void handle_level_irq(struct irq_desc *desc); 612 extern void handle_fasteoi_irq(struct irq_desc *desc); 613 extern void handle_edge_irq(struct irq_desc *desc); 614 extern void handle_edge_eoi_irq(struct irq_desc *desc); 615 extern void handle_simple_irq(struct irq_desc *desc); 616 extern void handle_untracked_irq(struct irq_desc *desc); 617 extern void handle_percpu_irq(struct irq_desc *desc); 618 extern void handle_percpu_devid_irq(struct irq_desc *desc); 619 extern void handle_bad_irq(struct irq_desc *desc); 620 extern void handle_nested_irq(unsigned int irq); 621 622 extern void handle_fasteoi_nmi(struct irq_desc *desc); 623 extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc); 624 625 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); 626 extern int irq_chip_pm_get(struct irq_data *data); 627 extern int irq_chip_pm_put(struct irq_data *data); 628 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 629 extern void handle_fasteoi_ack_irq(struct irq_desc *desc); 630 extern void handle_fasteoi_mask_irq(struct irq_desc *desc); 631 extern int irq_chip_set_parent_state(struct irq_data *data, 632 enum irqchip_irq_state which, 633 bool val); 634 extern int irq_chip_get_parent_state(struct irq_data *data, 635 enum irqchip_irq_state which, 636 bool *state); 637 extern void irq_chip_enable_parent(struct irq_data *data); 638 extern void irq_chip_disable_parent(struct irq_data *data); 639 extern void irq_chip_ack_parent(struct irq_data *data); 640 extern int irq_chip_retrigger_hierarchy(struct irq_data *data); 641 extern void irq_chip_mask_parent(struct irq_data *data); 642 extern void irq_chip_mask_ack_parent(struct irq_data *data); 643 extern void irq_chip_unmask_parent(struct irq_data *data); 644 extern void irq_chip_eoi_parent(struct irq_data *data); 645 extern int irq_chip_set_affinity_parent(struct irq_data *data, 646 const struct cpumask *dest, 647 bool force); 648 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); 649 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, 650 void *vcpu_info); 651 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); 652 extern int irq_chip_request_resources_parent(struct irq_data *data); 653 extern void irq_chip_release_resources_parent(struct irq_data *data); 654 #endif 655 656 /* Handling of unhandled and spurious interrupts: */ 657 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret); 658 659 660 /* Enable/disable irq debugging output: */ 661 extern int noirqdebug_setup(char *str); 662 663 /* Checks whether the interrupt can be requested by request_irq(): */ 664 extern int can_request_irq(unsigned int irq, unsigned long irqflags); 665 666 /* Dummy irq-chip implementations: */ 667 extern struct irq_chip no_irq_chip; 668 extern struct irq_chip dummy_irq_chip; 669 670 extern void 671 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, 672 irq_flow_handler_t handle, const char *name); 673 674 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, 675 irq_flow_handler_t handle) 676 { 677 irq_set_chip_and_handler_name(irq, chip, handle, NULL); 678 } 679 680 extern int irq_set_percpu_devid(unsigned int irq); 681 extern int irq_set_percpu_devid_partition(unsigned int irq, 682 const struct cpumask *affinity); 683 extern int irq_get_percpu_devid_partition(unsigned int irq, 684 struct cpumask *affinity); 685 686 extern void 687 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, 688 const char *name); 689 690 static inline void 691 irq_set_handler(unsigned int irq, irq_flow_handler_t handle) 692 { 693 __irq_set_handler(irq, handle, 0, NULL); 694 } 695 696 /* 697 * Set a highlevel chained flow handler for a given IRQ. 698 * (a chained handler is automatically enabled and set to 699 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 700 */ 701 static inline void 702 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) 703 { 704 __irq_set_handler(irq, handle, 1, NULL); 705 } 706 707 /* 708 * Set a highlevel chained flow handler and its data for a given IRQ. 709 * (a chained handler is automatically enabled and set to 710 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 711 */ 712 void 713 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, 714 void *data); 715 716 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); 717 718 static inline void irq_set_status_flags(unsigned int irq, unsigned long set) 719 { 720 irq_modify_status(irq, 0, set); 721 } 722 723 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) 724 { 725 irq_modify_status(irq, clr, 0); 726 } 727 728 static inline void irq_set_noprobe(unsigned int irq) 729 { 730 irq_modify_status(irq, 0, IRQ_NOPROBE); 731 } 732 733 static inline void irq_set_probe(unsigned int irq) 734 { 735 irq_modify_status(irq, IRQ_NOPROBE, 0); 736 } 737 738 static inline void irq_set_nothread(unsigned int irq) 739 { 740 irq_modify_status(irq, 0, IRQ_NOTHREAD); 741 } 742 743 static inline void irq_set_thread(unsigned int irq) 744 { 745 irq_modify_status(irq, IRQ_NOTHREAD, 0); 746 } 747 748 static inline void irq_set_nested_thread(unsigned int irq, bool nest) 749 { 750 if (nest) 751 irq_set_status_flags(irq, IRQ_NESTED_THREAD); 752 else 753 irq_clear_status_flags(irq, IRQ_NESTED_THREAD); 754 } 755 756 static inline void irq_set_percpu_devid_flags(unsigned int irq) 757 { 758 irq_set_status_flags(irq, 759 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | 760 IRQ_NOPROBE | IRQ_PER_CPU_DEVID); 761 } 762 763 /* Set/get chip/data for an IRQ: */ 764 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); 765 extern int irq_set_handler_data(unsigned int irq, void *data); 766 extern int irq_set_chip_data(unsigned int irq, void *data); 767 extern int irq_set_irq_type(unsigned int irq, unsigned int type); 768 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 769 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, 770 struct msi_desc *entry); 771 extern struct irq_data *irq_get_irq_data(unsigned int irq); 772 773 static inline struct irq_chip *irq_get_chip(unsigned int irq) 774 { 775 struct irq_data *d = irq_get_irq_data(irq); 776 return d ? d->chip : NULL; 777 } 778 779 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) 780 { 781 return d->chip; 782 } 783 784 static inline void *irq_get_chip_data(unsigned int irq) 785 { 786 struct irq_data *d = irq_get_irq_data(irq); 787 return d ? d->chip_data : NULL; 788 } 789 790 static inline void *irq_data_get_irq_chip_data(struct irq_data *d) 791 { 792 return d->chip_data; 793 } 794 795 static inline void *irq_get_handler_data(unsigned int irq) 796 { 797 struct irq_data *d = irq_get_irq_data(irq); 798 return d ? d->common->handler_data : NULL; 799 } 800 801 static inline void *irq_data_get_irq_handler_data(struct irq_data *d) 802 { 803 return d->common->handler_data; 804 } 805 806 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) 807 { 808 struct irq_data *d = irq_get_irq_data(irq); 809 return d ? d->common->msi_desc : NULL; 810 } 811 812 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d) 813 { 814 return d->common->msi_desc; 815 } 816 817 static inline u32 irq_get_trigger_type(unsigned int irq) 818 { 819 struct irq_data *d = irq_get_irq_data(irq); 820 return d ? irqd_get_trigger_type(d) : 0; 821 } 822 823 static inline int irq_common_data_get_node(struct irq_common_data *d) 824 { 825 #ifdef CONFIG_NUMA 826 return d->node; 827 #else 828 return 0; 829 #endif 830 } 831 832 static inline int irq_data_get_node(struct irq_data *d) 833 { 834 return irq_common_data_get_node(d->common); 835 } 836 837 static inline struct cpumask *irq_get_affinity_mask(int irq) 838 { 839 struct irq_data *d = irq_get_irq_data(irq); 840 841 return d ? d->common->affinity : NULL; 842 } 843 844 static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d) 845 { 846 return d->common->affinity; 847 } 848 849 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 850 static inline 851 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 852 { 853 return d->common->effective_affinity; 854 } 855 static inline void irq_data_update_effective_affinity(struct irq_data *d, 856 const struct cpumask *m) 857 { 858 cpumask_copy(d->common->effective_affinity, m); 859 } 860 #else 861 static inline void irq_data_update_effective_affinity(struct irq_data *d, 862 const struct cpumask *m) 863 { 864 } 865 static inline 866 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 867 { 868 return d->common->affinity; 869 } 870 #endif 871 872 unsigned int arch_dynirq_lower_bound(unsigned int from); 873 874 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, 875 struct module *owner, 876 const struct irq_affinity_desc *affinity); 877 878 int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from, 879 unsigned int cnt, int node, struct module *owner, 880 const struct irq_affinity_desc *affinity); 881 882 /* use macros to avoid needing export.h for THIS_MODULE */ 883 #define irq_alloc_descs(irq, from, cnt, node) \ 884 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL) 885 886 #define irq_alloc_desc(node) \ 887 irq_alloc_descs(-1, 0, 1, node) 888 889 #define irq_alloc_desc_at(at, node) \ 890 irq_alloc_descs(at, at, 1, node) 891 892 #define irq_alloc_desc_from(from, node) \ 893 irq_alloc_descs(-1, from, 1, node) 894 895 #define irq_alloc_descs_from(from, cnt, node) \ 896 irq_alloc_descs(-1, from, cnt, node) 897 898 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \ 899 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL) 900 901 #define devm_irq_alloc_desc(dev, node) \ 902 devm_irq_alloc_descs(dev, -1, 0, 1, node) 903 904 #define devm_irq_alloc_desc_at(dev, at, node) \ 905 devm_irq_alloc_descs(dev, at, at, 1, node) 906 907 #define devm_irq_alloc_desc_from(dev, from, node) \ 908 devm_irq_alloc_descs(dev, -1, from, 1, node) 909 910 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \ 911 devm_irq_alloc_descs(dev, -1, from, cnt, node) 912 913 void irq_free_descs(unsigned int irq, unsigned int cnt); 914 static inline void irq_free_desc(unsigned int irq) 915 { 916 irq_free_descs(irq, 1); 917 } 918 919 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ 920 unsigned int irq_alloc_hwirqs(int cnt, int node); 921 static inline unsigned int irq_alloc_hwirq(int node) 922 { 923 return irq_alloc_hwirqs(1, node); 924 } 925 void irq_free_hwirqs(unsigned int from, int cnt); 926 static inline void irq_free_hwirq(unsigned int irq) 927 { 928 return irq_free_hwirqs(irq, 1); 929 } 930 int arch_setup_hwirq(unsigned int irq, int node); 931 void arch_teardown_hwirq(unsigned int irq); 932 #endif 933 934 #ifdef CONFIG_GENERIC_IRQ_LEGACY 935 void irq_init_desc(unsigned int irq); 936 #endif 937 938 /** 939 * struct irq_chip_regs - register offsets for struct irq_gci 940 * @enable: Enable register offset to reg_base 941 * @disable: Disable register offset to reg_base 942 * @mask: Mask register offset to reg_base 943 * @ack: Ack register offset to reg_base 944 * @eoi: Eoi register offset to reg_base 945 * @type: Type configuration register offset to reg_base 946 * @polarity: Polarity configuration register offset to reg_base 947 */ 948 struct irq_chip_regs { 949 unsigned long enable; 950 unsigned long disable; 951 unsigned long mask; 952 unsigned long ack; 953 unsigned long eoi; 954 unsigned long type; 955 unsigned long polarity; 956 }; 957 958 /** 959 * struct irq_chip_type - Generic interrupt chip instance for a flow type 960 * @chip: The real interrupt chip which provides the callbacks 961 * @regs: Register offsets for this chip 962 * @handler: Flow handler associated with this chip 963 * @type: Chip can handle these flow types 964 * @mask_cache_priv: Cached mask register private to the chip type 965 * @mask_cache: Pointer to cached mask register 966 * 967 * A irq_generic_chip can have several instances of irq_chip_type when 968 * it requires different functions and register offsets for different 969 * flow types. 970 */ 971 struct irq_chip_type { 972 struct irq_chip chip; 973 struct irq_chip_regs regs; 974 irq_flow_handler_t handler; 975 u32 type; 976 u32 mask_cache_priv; 977 u32 *mask_cache; 978 }; 979 980 /** 981 * struct irq_chip_generic - Generic irq chip data structure 982 * @lock: Lock to protect register and cache data access 983 * @reg_base: Register base address (virtual) 984 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL) 985 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL) 986 * @suspend: Function called from core code on suspend once per 987 * chip; can be useful instead of irq_chip::suspend to 988 * handle chip details even when no interrupts are in use 989 * @resume: Function called from core code on resume once per chip; 990 * can be useful instead of irq_chip::suspend to handle 991 * chip details even when no interrupts are in use 992 * @irq_base: Interrupt base nr for this chip 993 * @irq_cnt: Number of interrupts handled by this chip 994 * @mask_cache: Cached mask register shared between all chip types 995 * @type_cache: Cached type register 996 * @polarity_cache: Cached polarity register 997 * @wake_enabled: Interrupt can wakeup from suspend 998 * @wake_active: Interrupt is marked as an wakeup from suspend source 999 * @num_ct: Number of available irq_chip_type instances (usually 1) 1000 * @private: Private data for non generic chip callbacks 1001 * @installed: bitfield to denote installed interrupts 1002 * @unused: bitfield to denote unused interrupts 1003 * @domain: irq domain pointer 1004 * @list: List head for keeping track of instances 1005 * @chip_types: Array of interrupt irq_chip_types 1006 * 1007 * Note, that irq_chip_generic can have multiple irq_chip_type 1008 * implementations which can be associated to a particular irq line of 1009 * an irq_chip_generic instance. That allows to share and protect 1010 * state in an irq_chip_generic instance when we need to implement 1011 * different flow mechanisms (level/edge) for it. 1012 */ 1013 struct irq_chip_generic { 1014 raw_spinlock_t lock; 1015 void __iomem *reg_base; 1016 u32 (*reg_readl)(void __iomem *addr); 1017 void (*reg_writel)(u32 val, void __iomem *addr); 1018 void (*suspend)(struct irq_chip_generic *gc); 1019 void (*resume)(struct irq_chip_generic *gc); 1020 unsigned int irq_base; 1021 unsigned int irq_cnt; 1022 u32 mask_cache; 1023 u32 type_cache; 1024 u32 polarity_cache; 1025 u32 wake_enabled; 1026 u32 wake_active; 1027 unsigned int num_ct; 1028 void *private; 1029 unsigned long installed; 1030 unsigned long unused; 1031 struct irq_domain *domain; 1032 struct list_head list; 1033 struct irq_chip_type chip_types[0]; 1034 }; 1035 1036 /** 1037 * enum irq_gc_flags - Initialization flags for generic irq chips 1038 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg 1039 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for 1040 * irq chips which need to call irq_set_wake() on 1041 * the parent irq. Usually GPIO implementations 1042 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private 1043 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask 1044 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE) 1045 */ 1046 enum irq_gc_flags { 1047 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 1048 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 1049 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, 1050 IRQ_GC_NO_MASK = 1 << 3, 1051 IRQ_GC_BE_IO = 1 << 4, 1052 }; 1053 1054 /* 1055 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains 1056 * @irqs_per_chip: Number of interrupts per chip 1057 * @num_chips: Number of chips 1058 * @irq_flags_to_set: IRQ* flags to set on irq setup 1059 * @irq_flags_to_clear: IRQ* flags to clear on irq setup 1060 * @gc_flags: Generic chip specific setup flags 1061 * @gc: Array of pointers to generic interrupt chips 1062 */ 1063 struct irq_domain_chip_generic { 1064 unsigned int irqs_per_chip; 1065 unsigned int num_chips; 1066 unsigned int irq_flags_to_clear; 1067 unsigned int irq_flags_to_set; 1068 enum irq_gc_flags gc_flags; 1069 struct irq_chip_generic *gc[0]; 1070 }; 1071 1072 /* Generic chip callback functions */ 1073 void irq_gc_noop(struct irq_data *d); 1074 void irq_gc_mask_disable_reg(struct irq_data *d); 1075 void irq_gc_mask_set_bit(struct irq_data *d); 1076 void irq_gc_mask_clr_bit(struct irq_data *d); 1077 void irq_gc_unmask_enable_reg(struct irq_data *d); 1078 void irq_gc_ack_set_bit(struct irq_data *d); 1079 void irq_gc_ack_clr_bit(struct irq_data *d); 1080 void irq_gc_mask_disable_and_ack_set(struct irq_data *d); 1081 void irq_gc_eoi(struct irq_data *d); 1082 int irq_gc_set_wake(struct irq_data *d, unsigned int on); 1083 1084 /* Setup functions for irq_chip_generic */ 1085 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, 1086 irq_hw_number_t hw_irq); 1087 struct irq_chip_generic * 1088 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, 1089 void __iomem *reg_base, irq_flow_handler_t handler); 1090 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 1091 enum irq_gc_flags flags, unsigned int clr, 1092 unsigned int set); 1093 int irq_setup_alt_chip(struct irq_data *d, unsigned int type); 1094 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 1095 unsigned int clr, unsigned int set); 1096 1097 struct irq_chip_generic * 1098 devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct, 1099 unsigned int irq_base, void __iomem *reg_base, 1100 irq_flow_handler_t handler); 1101 int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc, 1102 u32 msk, enum irq_gc_flags flags, 1103 unsigned int clr, unsigned int set); 1104 1105 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); 1106 1107 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, 1108 int num_ct, const char *name, 1109 irq_flow_handler_t handler, 1110 unsigned int clr, unsigned int set, 1111 enum irq_gc_flags flags); 1112 1113 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \ 1114 handler, clr, set, flags) \ 1115 ({ \ 1116 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \ 1117 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\ 1118 handler, clr, set, flags); \ 1119 }) 1120 1121 static inline void irq_free_generic_chip(struct irq_chip_generic *gc) 1122 { 1123 kfree(gc); 1124 } 1125 1126 static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc, 1127 u32 msk, unsigned int clr, 1128 unsigned int set) 1129 { 1130 irq_remove_generic_chip(gc, msk, clr, set); 1131 irq_free_generic_chip(gc); 1132 } 1133 1134 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) 1135 { 1136 return container_of(d->chip, struct irq_chip_type, chip); 1137 } 1138 1139 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) 1140 1141 #ifdef CONFIG_SMP 1142 static inline void irq_gc_lock(struct irq_chip_generic *gc) 1143 { 1144 raw_spin_lock(&gc->lock); 1145 } 1146 1147 static inline void irq_gc_unlock(struct irq_chip_generic *gc) 1148 { 1149 raw_spin_unlock(&gc->lock); 1150 } 1151 #else 1152 static inline void irq_gc_lock(struct irq_chip_generic *gc) { } 1153 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } 1154 #endif 1155 1156 /* 1157 * The irqsave variants are for usage in non interrupt code. Do not use 1158 * them in irq_chip callbacks. Use irq_gc_lock() instead. 1159 */ 1160 #define irq_gc_lock_irqsave(gc, flags) \ 1161 raw_spin_lock_irqsave(&(gc)->lock, flags) 1162 1163 #define irq_gc_unlock_irqrestore(gc, flags) \ 1164 raw_spin_unlock_irqrestore(&(gc)->lock, flags) 1165 1166 static inline void irq_reg_writel(struct irq_chip_generic *gc, 1167 u32 val, int reg_offset) 1168 { 1169 if (gc->reg_writel) 1170 gc->reg_writel(val, gc->reg_base + reg_offset); 1171 else 1172 writel(val, gc->reg_base + reg_offset); 1173 } 1174 1175 static inline u32 irq_reg_readl(struct irq_chip_generic *gc, 1176 int reg_offset) 1177 { 1178 if (gc->reg_readl) 1179 return gc->reg_readl(gc->reg_base + reg_offset); 1180 else 1181 return readl(gc->reg_base + reg_offset); 1182 } 1183 1184 struct irq_matrix; 1185 struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits, 1186 unsigned int alloc_start, 1187 unsigned int alloc_end); 1188 void irq_matrix_online(struct irq_matrix *m); 1189 void irq_matrix_offline(struct irq_matrix *m); 1190 void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace); 1191 int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk); 1192 void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk); 1193 int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk, 1194 unsigned int *mapped_cpu); 1195 void irq_matrix_reserve(struct irq_matrix *m); 1196 void irq_matrix_remove_reserved(struct irq_matrix *m); 1197 int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk, 1198 bool reserved, unsigned int *mapped_cpu); 1199 void irq_matrix_free(struct irq_matrix *m, unsigned int cpu, 1200 unsigned int bit, bool managed); 1201 void irq_matrix_assign(struct irq_matrix *m, unsigned int bit); 1202 unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown); 1203 unsigned int irq_matrix_allocated(struct irq_matrix *m); 1204 unsigned int irq_matrix_reserved(struct irq_matrix *m); 1205 void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind); 1206 1207 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */ 1208 #define INVALID_HWIRQ (~0UL) 1209 irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu); 1210 int __ipi_send_single(struct irq_desc *desc, unsigned int cpu); 1211 int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest); 1212 int ipi_send_single(unsigned int virq, unsigned int cpu); 1213 int ipi_send_mask(unsigned int virq, const struct cpumask *dest); 1214 1215 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER 1216 /* 1217 * Registers a generic IRQ handling function as the top-level IRQ handler in 1218 * the system, which is generally the first C code called from an assembly 1219 * architecture-specific interrupt handler. 1220 * 1221 * Returns 0 on success, or -EBUSY if an IRQ handler has already been 1222 * registered. 1223 */ 1224 int __init set_handle_irq(void (*handle_irq)(struct pt_regs *)); 1225 1226 /* 1227 * Allows interrupt handlers to find the irqchip that's been registered as the 1228 * top-level IRQ handler. 1229 */ 1230 extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init; 1231 #endif 1232 1233 #endif /* _LINUX_IRQ_H */ 1234