1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_IRQ_H 3 #define _LINUX_IRQ_H 4 5 /* 6 * Please do not include this file in generic code. There is currently 7 * no requirement for any architecture to implement anything held 8 * within this file. 9 * 10 * Thanks. --rmk 11 */ 12 13 #include <linux/cache.h> 14 #include <linux/spinlock.h> 15 #include <linux/cpumask.h> 16 #include <linux/irqhandler.h> 17 #include <linux/irqreturn.h> 18 #include <linux/irqnr.h> 19 #include <linux/topology.h> 20 #include <linux/io.h> 21 #include <linux/slab.h> 22 23 #include <asm/irq.h> 24 #include <asm/ptrace.h> 25 #include <asm/irq_regs.h> 26 27 struct seq_file; 28 struct module; 29 struct msi_msg; 30 struct irq_affinity_desc; 31 enum irqchip_irq_state; 32 33 /* 34 * IRQ line status. 35 * 36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h 37 * 38 * IRQ_TYPE_NONE - default, unspecified type 39 * IRQ_TYPE_EDGE_RISING - rising edge triggered 40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered 41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 42 * IRQ_TYPE_LEVEL_HIGH - high level triggered 43 * IRQ_TYPE_LEVEL_LOW - low level triggered 44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 45 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits 46 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type 47 * to setup the HW to a sane default (used 48 * by irqdomain map() callbacks to synchronize 49 * the HW state and SW flags for a newly 50 * allocated descriptor). 51 * 52 * IRQ_TYPE_PROBE - Special flag for probing in progress 53 * 54 * Bits which can be modified via irq_set/clear/modify_status_flags() 55 * IRQ_LEVEL - Interrupt is level type. Will be also 56 * updated in the code when the above trigger 57 * bits are modified via irq_set_irq_type() 58 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect 59 * it from affinity setting 60 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing 61 * IRQ_NOREQUEST - Interrupt cannot be requested via 62 * request_irq() 63 * IRQ_NOTHREAD - Interrupt cannot be threaded 64 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in 65 * request/setup_irq() 66 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) 67 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context 68 * IRQ_NESTED_THREAD - Interrupt nests into another thread 69 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable 70 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude 71 * it from the spurious interrupt detection 72 * mechanism and from core side polling. 73 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable 74 * IRQ_HIDDEN - Don't show up in /proc/interrupts 75 */ 76 enum { 77 IRQ_TYPE_NONE = 0x00000000, 78 IRQ_TYPE_EDGE_RISING = 0x00000001, 79 IRQ_TYPE_EDGE_FALLING = 0x00000002, 80 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), 81 IRQ_TYPE_LEVEL_HIGH = 0x00000004, 82 IRQ_TYPE_LEVEL_LOW = 0x00000008, 83 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), 84 IRQ_TYPE_SENSE_MASK = 0x0000000f, 85 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, 86 87 IRQ_TYPE_PROBE = 0x00000010, 88 89 IRQ_LEVEL = (1 << 8), 90 IRQ_PER_CPU = (1 << 9), 91 IRQ_NOPROBE = (1 << 10), 92 IRQ_NOREQUEST = (1 << 11), 93 IRQ_NOAUTOEN = (1 << 12), 94 IRQ_NO_BALANCING = (1 << 13), 95 IRQ_MOVE_PCNTXT = (1 << 14), 96 IRQ_NESTED_THREAD = (1 << 15), 97 IRQ_NOTHREAD = (1 << 16), 98 IRQ_PER_CPU_DEVID = (1 << 17), 99 IRQ_IS_POLLED = (1 << 18), 100 IRQ_DISABLE_UNLAZY = (1 << 19), 101 IRQ_HIDDEN = (1 << 20), 102 }; 103 104 #define IRQF_MODIFY_MASK \ 105 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ 106 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ 107 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ 108 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_HIDDEN) 109 110 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 111 112 /* 113 * Return value for chip->irq_set_affinity() 114 * 115 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity 116 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity 117 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to 118 * support stacked irqchips, which indicates skipping 119 * all descendent irqchips. 120 */ 121 enum { 122 IRQ_SET_MASK_OK = 0, 123 IRQ_SET_MASK_OK_NOCOPY, 124 IRQ_SET_MASK_OK_DONE, 125 }; 126 127 struct msi_desc; 128 struct irq_domain; 129 130 /** 131 * struct irq_common_data - per irq data shared by all irqchips 132 * @state_use_accessors: status information for irq chip functions. 133 * Use accessor functions to deal with it 134 * @node: node index useful for balancing 135 * @handler_data: per-IRQ data for the irq_chip methods 136 * @affinity: IRQ affinity on SMP. If this is an IPI 137 * related irq, then this is the mask of the 138 * CPUs to which an IPI can be sent. 139 * @effective_affinity: The effective IRQ affinity on SMP as some irq 140 * chips do not allow multi CPU destinations. 141 * A subset of @affinity. 142 * @msi_desc: MSI descriptor 143 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional. 144 */ 145 struct irq_common_data { 146 unsigned int __private state_use_accessors; 147 #ifdef CONFIG_NUMA 148 unsigned int node; 149 #endif 150 void *handler_data; 151 struct msi_desc *msi_desc; 152 cpumask_var_t affinity; 153 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 154 cpumask_var_t effective_affinity; 155 #endif 156 #ifdef CONFIG_GENERIC_IRQ_IPI 157 unsigned int ipi_offset; 158 #endif 159 }; 160 161 /** 162 * struct irq_data - per irq chip data passed down to chip functions 163 * @mask: precomputed bitmask for accessing the chip registers 164 * @irq: interrupt number 165 * @hwirq: hardware interrupt number, local to the interrupt domain 166 * @common: point to data shared by all irqchips 167 * @chip: low level interrupt hardware access 168 * @domain: Interrupt translation domain; responsible for mapping 169 * between hwirq number and linux irq number. 170 * @parent_data: pointer to parent struct irq_data to support hierarchy 171 * irq_domain 172 * @chip_data: platform-specific per-chip private data for the chip 173 * methods, to allow shared chip implementations 174 */ 175 struct irq_data { 176 u32 mask; 177 unsigned int irq; 178 unsigned long hwirq; 179 struct irq_common_data *common; 180 struct irq_chip *chip; 181 struct irq_domain *domain; 182 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 183 struct irq_data *parent_data; 184 #endif 185 void *chip_data; 186 }; 187 188 /* 189 * Bit masks for irq_common_data.state_use_accessors 190 * 191 * IRQD_TRIGGER_MASK - Mask for the trigger type bits 192 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 193 * IRQD_ACTIVATED - Interrupt has already been activated 194 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 195 * IRQD_PER_CPU - Interrupt is per cpu 196 * IRQD_AFFINITY_SET - Interrupt affinity was set 197 * IRQD_LEVEL - Interrupt is level triggered 198 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup 199 * from suspend 200 * IRQD_MOVE_PCNTXT - Interrupt can be moved in process 201 * context 202 * IRQD_IRQ_DISABLED - Disabled state of the interrupt 203 * IRQD_IRQ_MASKED - Masked state of the interrupt 204 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt 205 * IRQD_WAKEUP_ARMED - Wakeup mode armed 206 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU 207 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel 208 * IRQD_IRQ_STARTED - Startup state of the interrupt 209 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity 210 * mask. Applies only to affinity managed irqs. 211 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target 212 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set 213 * IRQD_CAN_RESERVE - Can use reservation mode 214 * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change 215 * required 216 * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked 217 * from actual interrupt context. 218 * IRQD_AFFINITY_ON_ACTIVATE - Affinity is set on activation. Don't call 219 * irq_chip::irq_set_affinity() when deactivated. 220 * IRQD_IRQ_ENABLED_ON_SUSPEND - Interrupt is enabled on suspend by irq pm if 221 * irqchip have flag IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND set. 222 */ 223 enum { 224 IRQD_TRIGGER_MASK = 0xf, 225 IRQD_SETAFFINITY_PENDING = (1 << 8), 226 IRQD_ACTIVATED = (1 << 9), 227 IRQD_NO_BALANCING = (1 << 10), 228 IRQD_PER_CPU = (1 << 11), 229 IRQD_AFFINITY_SET = (1 << 12), 230 IRQD_LEVEL = (1 << 13), 231 IRQD_WAKEUP_STATE = (1 << 14), 232 IRQD_MOVE_PCNTXT = (1 << 15), 233 IRQD_IRQ_DISABLED = (1 << 16), 234 IRQD_IRQ_MASKED = (1 << 17), 235 IRQD_IRQ_INPROGRESS = (1 << 18), 236 IRQD_WAKEUP_ARMED = (1 << 19), 237 IRQD_FORWARDED_TO_VCPU = (1 << 20), 238 IRQD_AFFINITY_MANAGED = (1 << 21), 239 IRQD_IRQ_STARTED = (1 << 22), 240 IRQD_MANAGED_SHUTDOWN = (1 << 23), 241 IRQD_SINGLE_TARGET = (1 << 24), 242 IRQD_DEFAULT_TRIGGER_SET = (1 << 25), 243 IRQD_CAN_RESERVE = (1 << 26), 244 IRQD_MSI_NOMASK_QUIRK = (1 << 27), 245 IRQD_HANDLE_ENFORCE_IRQCTX = (1 << 28), 246 IRQD_AFFINITY_ON_ACTIVATE = (1 << 29), 247 IRQD_IRQ_ENABLED_ON_SUSPEND = (1 << 30), 248 }; 249 250 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors) 251 252 static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 253 { 254 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING; 255 } 256 257 static inline bool irqd_is_per_cpu(struct irq_data *d) 258 { 259 return __irqd_to_state(d) & IRQD_PER_CPU; 260 } 261 262 static inline bool irqd_can_balance(struct irq_data *d) 263 { 264 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); 265 } 266 267 static inline bool irqd_affinity_was_set(struct irq_data *d) 268 { 269 return __irqd_to_state(d) & IRQD_AFFINITY_SET; 270 } 271 272 static inline void irqd_mark_affinity_was_set(struct irq_data *d) 273 { 274 __irqd_to_state(d) |= IRQD_AFFINITY_SET; 275 } 276 277 static inline bool irqd_trigger_type_was_set(struct irq_data *d) 278 { 279 return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET; 280 } 281 282 static inline u32 irqd_get_trigger_type(struct irq_data *d) 283 { 284 return __irqd_to_state(d) & IRQD_TRIGGER_MASK; 285 } 286 287 /* 288 * Must only be called inside irq_chip.irq_set_type() functions or 289 * from the DT/ACPI setup code. 290 */ 291 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) 292 { 293 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK; 294 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK; 295 __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET; 296 } 297 298 static inline bool irqd_is_level_type(struct irq_data *d) 299 { 300 return __irqd_to_state(d) & IRQD_LEVEL; 301 } 302 303 /* 304 * Must only be called of irqchip.irq_set_affinity() or low level 305 * hieararchy domain allocation functions. 306 */ 307 static inline void irqd_set_single_target(struct irq_data *d) 308 { 309 __irqd_to_state(d) |= IRQD_SINGLE_TARGET; 310 } 311 312 static inline bool irqd_is_single_target(struct irq_data *d) 313 { 314 return __irqd_to_state(d) & IRQD_SINGLE_TARGET; 315 } 316 317 static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d) 318 { 319 __irqd_to_state(d) |= IRQD_HANDLE_ENFORCE_IRQCTX; 320 } 321 322 static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d) 323 { 324 return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX; 325 } 326 327 static inline bool irqd_is_enabled_on_suspend(struct irq_data *d) 328 { 329 return __irqd_to_state(d) & IRQD_IRQ_ENABLED_ON_SUSPEND; 330 } 331 332 static inline bool irqd_is_wakeup_set(struct irq_data *d) 333 { 334 return __irqd_to_state(d) & IRQD_WAKEUP_STATE; 335 } 336 337 static inline bool irqd_can_move_in_process_context(struct irq_data *d) 338 { 339 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT; 340 } 341 342 static inline bool irqd_irq_disabled(struct irq_data *d) 343 { 344 return __irqd_to_state(d) & IRQD_IRQ_DISABLED; 345 } 346 347 static inline bool irqd_irq_masked(struct irq_data *d) 348 { 349 return __irqd_to_state(d) & IRQD_IRQ_MASKED; 350 } 351 352 static inline bool irqd_irq_inprogress(struct irq_data *d) 353 { 354 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; 355 } 356 357 static inline bool irqd_is_wakeup_armed(struct irq_data *d) 358 { 359 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED; 360 } 361 362 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d) 363 { 364 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU; 365 } 366 367 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d) 368 { 369 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU; 370 } 371 372 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d) 373 { 374 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; 375 } 376 377 static inline bool irqd_affinity_is_managed(struct irq_data *d) 378 { 379 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED; 380 } 381 382 static inline bool irqd_is_activated(struct irq_data *d) 383 { 384 return __irqd_to_state(d) & IRQD_ACTIVATED; 385 } 386 387 static inline void irqd_set_activated(struct irq_data *d) 388 { 389 __irqd_to_state(d) |= IRQD_ACTIVATED; 390 } 391 392 static inline void irqd_clr_activated(struct irq_data *d) 393 { 394 __irqd_to_state(d) &= ~IRQD_ACTIVATED; 395 } 396 397 static inline bool irqd_is_started(struct irq_data *d) 398 { 399 return __irqd_to_state(d) & IRQD_IRQ_STARTED; 400 } 401 402 static inline bool irqd_is_managed_and_shutdown(struct irq_data *d) 403 { 404 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN; 405 } 406 407 static inline void irqd_set_can_reserve(struct irq_data *d) 408 { 409 __irqd_to_state(d) |= IRQD_CAN_RESERVE; 410 } 411 412 static inline void irqd_clr_can_reserve(struct irq_data *d) 413 { 414 __irqd_to_state(d) &= ~IRQD_CAN_RESERVE; 415 } 416 417 static inline bool irqd_can_reserve(struct irq_data *d) 418 { 419 return __irqd_to_state(d) & IRQD_CAN_RESERVE; 420 } 421 422 static inline void irqd_set_msi_nomask_quirk(struct irq_data *d) 423 { 424 __irqd_to_state(d) |= IRQD_MSI_NOMASK_QUIRK; 425 } 426 427 static inline void irqd_clr_msi_nomask_quirk(struct irq_data *d) 428 { 429 __irqd_to_state(d) &= ~IRQD_MSI_NOMASK_QUIRK; 430 } 431 432 static inline bool irqd_msi_nomask_quirk(struct irq_data *d) 433 { 434 return __irqd_to_state(d) & IRQD_MSI_NOMASK_QUIRK; 435 } 436 437 static inline void irqd_set_affinity_on_activate(struct irq_data *d) 438 { 439 __irqd_to_state(d) |= IRQD_AFFINITY_ON_ACTIVATE; 440 } 441 442 static inline bool irqd_affinity_on_activate(struct irq_data *d) 443 { 444 return __irqd_to_state(d) & IRQD_AFFINITY_ON_ACTIVATE; 445 } 446 447 #undef __irqd_to_state 448 449 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) 450 { 451 return d->hwirq; 452 } 453 454 /** 455 * struct irq_chip - hardware interrupt chip descriptor 456 * 457 * @parent_device: pointer to parent device for irqchip 458 * @name: name for /proc/interrupts 459 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 460 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 461 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) 462 * @irq_disable: disable the interrupt 463 * @irq_ack: start of a new interrupt 464 * @irq_mask: mask an interrupt source 465 * @irq_mask_ack: ack and mask an interrupt source 466 * @irq_unmask: unmask an interrupt source 467 * @irq_eoi: end of interrupt 468 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force 469 * argument is true, it tells the driver to 470 * unconditionally apply the affinity setting. Sanity 471 * checks against the supplied affinity mask are not 472 * required. This is used for CPU hotplug where the 473 * target CPU is not yet set in the cpu_online_mask. 474 * @irq_retrigger: resend an IRQ to the CPU 475 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ 476 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 477 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 478 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 479 * @irq_cpu_online: configure an interrupt source for a secondary CPU 480 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU 481 * @irq_suspend: function called from core code on suspend once per 482 * chip, when one or more interrupts are installed 483 * @irq_resume: function called from core code on resume once per chip, 484 * when one ore more interrupts are installed 485 * @irq_pm_shutdown: function called from core code on shutdown once per chip 486 * @irq_calc_mask: Optional function to set irq_data.mask for special cases 487 * @irq_print_chip: optional to print special chip info in show_interrupts 488 * @irq_request_resources: optional to request resources before calling 489 * any other callback related to this irq 490 * @irq_release_resources: optional to release resources acquired with 491 * irq_request_resources 492 * @irq_compose_msi_msg: optional to compose message content for MSI 493 * @irq_write_msi_msg: optional to write message content for MSI 494 * @irq_get_irqchip_state: return the internal state of an interrupt 495 * @irq_set_irqchip_state: set the internal state of a interrupt 496 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine 497 * @ipi_send_single: send a single IPI to destination cpus 498 * @ipi_send_mask: send an IPI to destination cpus in cpumask 499 * @irq_nmi_setup: function called from core code before enabling an NMI 500 * @irq_nmi_teardown: function called from core code after disabling an NMI 501 * @flags: chip specific flags 502 */ 503 struct irq_chip { 504 struct device *parent_device; 505 const char *name; 506 unsigned int (*irq_startup)(struct irq_data *data); 507 void (*irq_shutdown)(struct irq_data *data); 508 void (*irq_enable)(struct irq_data *data); 509 void (*irq_disable)(struct irq_data *data); 510 511 void (*irq_ack)(struct irq_data *data); 512 void (*irq_mask)(struct irq_data *data); 513 void (*irq_mask_ack)(struct irq_data *data); 514 void (*irq_unmask)(struct irq_data *data); 515 void (*irq_eoi)(struct irq_data *data); 516 517 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); 518 int (*irq_retrigger)(struct irq_data *data); 519 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); 520 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 521 522 void (*irq_bus_lock)(struct irq_data *data); 523 void (*irq_bus_sync_unlock)(struct irq_data *data); 524 525 void (*irq_cpu_online)(struct irq_data *data); 526 void (*irq_cpu_offline)(struct irq_data *data); 527 528 void (*irq_suspend)(struct irq_data *data); 529 void (*irq_resume)(struct irq_data *data); 530 void (*irq_pm_shutdown)(struct irq_data *data); 531 532 void (*irq_calc_mask)(struct irq_data *data); 533 534 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 535 int (*irq_request_resources)(struct irq_data *data); 536 void (*irq_release_resources)(struct irq_data *data); 537 538 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); 539 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); 540 541 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); 542 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); 543 544 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); 545 546 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); 547 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); 548 549 int (*irq_nmi_setup)(struct irq_data *data); 550 void (*irq_nmi_teardown)(struct irq_data *data); 551 552 unsigned long flags; 553 }; 554 555 /* 556 * irq_chip specific flags 557 * 558 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() 559 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled 560 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path 561 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks 562 * when irq enabled 563 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip 564 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask 565 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode 566 * IRQCHIP_SUPPORTS_LEVEL_MSI: Chip can provide two doorbells for Level MSIs 567 * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips 568 * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs 569 * in the suspend path if they are in disabled state 570 */ 571 enum { 572 IRQCHIP_SET_TYPE_MASKED = (1 << 0), 573 IRQCHIP_EOI_IF_HANDLED = (1 << 1), 574 IRQCHIP_MASK_ON_SUSPEND = (1 << 2), 575 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), 576 IRQCHIP_SKIP_SET_WAKE = (1 << 4), 577 IRQCHIP_ONESHOT_SAFE = (1 << 5), 578 IRQCHIP_EOI_THREADED = (1 << 6), 579 IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7), 580 IRQCHIP_SUPPORTS_NMI = (1 << 8), 581 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9), 582 }; 583 584 #include <linux/irqdesc.h> 585 586 /* 587 * Pick up the arch-dependent methods: 588 */ 589 #include <asm/hw_irq.h> 590 591 #ifndef NR_IRQS_LEGACY 592 # define NR_IRQS_LEGACY 0 593 #endif 594 595 #ifndef ARCH_IRQ_INIT_FLAGS 596 # define ARCH_IRQ_INIT_FLAGS 0 597 #endif 598 599 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS 600 601 struct irqaction; 602 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); 603 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); 604 605 extern void irq_cpu_online(void); 606 extern void irq_cpu_offline(void); 607 extern int irq_set_affinity_locked(struct irq_data *data, 608 const struct cpumask *cpumask, bool force); 609 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info); 610 611 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION) 612 extern void irq_migrate_all_off_this_cpu(void); 613 extern int irq_affinity_online_cpu(unsigned int cpu); 614 #else 615 # define irq_affinity_online_cpu NULL 616 #endif 617 618 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) 619 void __irq_move_irq(struct irq_data *data); 620 static inline void irq_move_irq(struct irq_data *data) 621 { 622 if (unlikely(irqd_is_setaffinity_pending(data))) 623 __irq_move_irq(data); 624 } 625 void irq_move_masked_irq(struct irq_data *data); 626 void irq_force_complete_move(struct irq_desc *desc); 627 #else 628 static inline void irq_move_irq(struct irq_data *data) { } 629 static inline void irq_move_masked_irq(struct irq_data *data) { } 630 static inline void irq_force_complete_move(struct irq_desc *desc) { } 631 #endif 632 633 extern int no_irq_affinity; 634 635 #ifdef CONFIG_HARDIRQS_SW_RESEND 636 int irq_set_parent(int irq, int parent_irq); 637 #else 638 static inline int irq_set_parent(int irq, int parent_irq) 639 { 640 return 0; 641 } 642 #endif 643 644 /* 645 * Built-in IRQ handlers for various IRQ types, 646 * callable via desc->handle_irq() 647 */ 648 extern void handle_level_irq(struct irq_desc *desc); 649 extern void handle_fasteoi_irq(struct irq_desc *desc); 650 extern void handle_percpu_devid_fasteoi_ipi(struct irq_desc *desc); 651 extern void handle_edge_irq(struct irq_desc *desc); 652 extern void handle_edge_eoi_irq(struct irq_desc *desc); 653 extern void handle_simple_irq(struct irq_desc *desc); 654 extern void handle_untracked_irq(struct irq_desc *desc); 655 extern void handle_percpu_irq(struct irq_desc *desc); 656 extern void handle_percpu_devid_irq(struct irq_desc *desc); 657 extern void handle_bad_irq(struct irq_desc *desc); 658 extern void handle_nested_irq(unsigned int irq); 659 660 extern void handle_fasteoi_nmi(struct irq_desc *desc); 661 extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc); 662 663 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); 664 extern int irq_chip_pm_get(struct irq_data *data); 665 extern int irq_chip_pm_put(struct irq_data *data); 666 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 667 extern void handle_fasteoi_ack_irq(struct irq_desc *desc); 668 extern void handle_fasteoi_mask_irq(struct irq_desc *desc); 669 extern int irq_chip_set_parent_state(struct irq_data *data, 670 enum irqchip_irq_state which, 671 bool val); 672 extern int irq_chip_get_parent_state(struct irq_data *data, 673 enum irqchip_irq_state which, 674 bool *state); 675 extern void irq_chip_enable_parent(struct irq_data *data); 676 extern void irq_chip_disable_parent(struct irq_data *data); 677 extern void irq_chip_ack_parent(struct irq_data *data); 678 extern int irq_chip_retrigger_hierarchy(struct irq_data *data); 679 extern void irq_chip_mask_parent(struct irq_data *data); 680 extern void irq_chip_mask_ack_parent(struct irq_data *data); 681 extern void irq_chip_unmask_parent(struct irq_data *data); 682 extern void irq_chip_eoi_parent(struct irq_data *data); 683 extern int irq_chip_set_affinity_parent(struct irq_data *data, 684 const struct cpumask *dest, 685 bool force); 686 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); 687 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, 688 void *vcpu_info); 689 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); 690 extern int irq_chip_request_resources_parent(struct irq_data *data); 691 extern void irq_chip_release_resources_parent(struct irq_data *data); 692 #endif 693 694 /* Handling of unhandled and spurious interrupts: */ 695 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret); 696 697 698 /* Enable/disable irq debugging output: */ 699 extern int noirqdebug_setup(char *str); 700 701 /* Checks whether the interrupt can be requested by request_irq(): */ 702 extern int can_request_irq(unsigned int irq, unsigned long irqflags); 703 704 /* Dummy irq-chip implementations: */ 705 extern struct irq_chip no_irq_chip; 706 extern struct irq_chip dummy_irq_chip; 707 708 extern void 709 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, 710 irq_flow_handler_t handle, const char *name); 711 712 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, 713 irq_flow_handler_t handle) 714 { 715 irq_set_chip_and_handler_name(irq, chip, handle, NULL); 716 } 717 718 extern int irq_set_percpu_devid(unsigned int irq); 719 extern int irq_set_percpu_devid_partition(unsigned int irq, 720 const struct cpumask *affinity); 721 extern int irq_get_percpu_devid_partition(unsigned int irq, 722 struct cpumask *affinity); 723 724 extern void 725 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, 726 const char *name); 727 728 static inline void 729 irq_set_handler(unsigned int irq, irq_flow_handler_t handle) 730 { 731 __irq_set_handler(irq, handle, 0, NULL); 732 } 733 734 /* 735 * Set a highlevel chained flow handler for a given IRQ. 736 * (a chained handler is automatically enabled and set to 737 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 738 */ 739 static inline void 740 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) 741 { 742 __irq_set_handler(irq, handle, 1, NULL); 743 } 744 745 /* 746 * Set a highlevel chained flow handler and its data for a given IRQ. 747 * (a chained handler is automatically enabled and set to 748 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 749 */ 750 void 751 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, 752 void *data); 753 754 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); 755 756 static inline void irq_set_status_flags(unsigned int irq, unsigned long set) 757 { 758 irq_modify_status(irq, 0, set); 759 } 760 761 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) 762 { 763 irq_modify_status(irq, clr, 0); 764 } 765 766 static inline void irq_set_noprobe(unsigned int irq) 767 { 768 irq_modify_status(irq, 0, IRQ_NOPROBE); 769 } 770 771 static inline void irq_set_probe(unsigned int irq) 772 { 773 irq_modify_status(irq, IRQ_NOPROBE, 0); 774 } 775 776 static inline void irq_set_nothread(unsigned int irq) 777 { 778 irq_modify_status(irq, 0, IRQ_NOTHREAD); 779 } 780 781 static inline void irq_set_thread(unsigned int irq) 782 { 783 irq_modify_status(irq, IRQ_NOTHREAD, 0); 784 } 785 786 static inline void irq_set_nested_thread(unsigned int irq, bool nest) 787 { 788 if (nest) 789 irq_set_status_flags(irq, IRQ_NESTED_THREAD); 790 else 791 irq_clear_status_flags(irq, IRQ_NESTED_THREAD); 792 } 793 794 static inline void irq_set_percpu_devid_flags(unsigned int irq) 795 { 796 irq_set_status_flags(irq, 797 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | 798 IRQ_NOPROBE | IRQ_PER_CPU_DEVID); 799 } 800 801 /* Set/get chip/data for an IRQ: */ 802 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); 803 extern int irq_set_handler_data(unsigned int irq, void *data); 804 extern int irq_set_chip_data(unsigned int irq, void *data); 805 extern int irq_set_irq_type(unsigned int irq, unsigned int type); 806 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 807 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, 808 struct msi_desc *entry); 809 extern struct irq_data *irq_get_irq_data(unsigned int irq); 810 811 static inline struct irq_chip *irq_get_chip(unsigned int irq) 812 { 813 struct irq_data *d = irq_get_irq_data(irq); 814 return d ? d->chip : NULL; 815 } 816 817 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) 818 { 819 return d->chip; 820 } 821 822 static inline void *irq_get_chip_data(unsigned int irq) 823 { 824 struct irq_data *d = irq_get_irq_data(irq); 825 return d ? d->chip_data : NULL; 826 } 827 828 static inline void *irq_data_get_irq_chip_data(struct irq_data *d) 829 { 830 return d->chip_data; 831 } 832 833 static inline void *irq_get_handler_data(unsigned int irq) 834 { 835 struct irq_data *d = irq_get_irq_data(irq); 836 return d ? d->common->handler_data : NULL; 837 } 838 839 static inline void *irq_data_get_irq_handler_data(struct irq_data *d) 840 { 841 return d->common->handler_data; 842 } 843 844 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) 845 { 846 struct irq_data *d = irq_get_irq_data(irq); 847 return d ? d->common->msi_desc : NULL; 848 } 849 850 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d) 851 { 852 return d->common->msi_desc; 853 } 854 855 static inline u32 irq_get_trigger_type(unsigned int irq) 856 { 857 struct irq_data *d = irq_get_irq_data(irq); 858 return d ? irqd_get_trigger_type(d) : 0; 859 } 860 861 static inline int irq_common_data_get_node(struct irq_common_data *d) 862 { 863 #ifdef CONFIG_NUMA 864 return d->node; 865 #else 866 return 0; 867 #endif 868 } 869 870 static inline int irq_data_get_node(struct irq_data *d) 871 { 872 return irq_common_data_get_node(d->common); 873 } 874 875 static inline struct cpumask *irq_get_affinity_mask(int irq) 876 { 877 struct irq_data *d = irq_get_irq_data(irq); 878 879 return d ? d->common->affinity : NULL; 880 } 881 882 static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d) 883 { 884 return d->common->affinity; 885 } 886 887 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 888 static inline 889 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 890 { 891 return d->common->effective_affinity; 892 } 893 static inline void irq_data_update_effective_affinity(struct irq_data *d, 894 const struct cpumask *m) 895 { 896 cpumask_copy(d->common->effective_affinity, m); 897 } 898 #else 899 static inline void irq_data_update_effective_affinity(struct irq_data *d, 900 const struct cpumask *m) 901 { 902 } 903 static inline 904 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 905 { 906 return d->common->affinity; 907 } 908 #endif 909 910 unsigned int arch_dynirq_lower_bound(unsigned int from); 911 912 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, 913 struct module *owner, 914 const struct irq_affinity_desc *affinity); 915 916 int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from, 917 unsigned int cnt, int node, struct module *owner, 918 const struct irq_affinity_desc *affinity); 919 920 /* use macros to avoid needing export.h for THIS_MODULE */ 921 #define irq_alloc_descs(irq, from, cnt, node) \ 922 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL) 923 924 #define irq_alloc_desc(node) \ 925 irq_alloc_descs(-1, 0, 1, node) 926 927 #define irq_alloc_desc_at(at, node) \ 928 irq_alloc_descs(at, at, 1, node) 929 930 #define irq_alloc_desc_from(from, node) \ 931 irq_alloc_descs(-1, from, 1, node) 932 933 #define irq_alloc_descs_from(from, cnt, node) \ 934 irq_alloc_descs(-1, from, cnt, node) 935 936 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \ 937 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL) 938 939 #define devm_irq_alloc_desc(dev, node) \ 940 devm_irq_alloc_descs(dev, -1, 0, 1, node) 941 942 #define devm_irq_alloc_desc_at(dev, at, node) \ 943 devm_irq_alloc_descs(dev, at, at, 1, node) 944 945 #define devm_irq_alloc_desc_from(dev, from, node) \ 946 devm_irq_alloc_descs(dev, -1, from, 1, node) 947 948 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \ 949 devm_irq_alloc_descs(dev, -1, from, cnt, node) 950 951 void irq_free_descs(unsigned int irq, unsigned int cnt); 952 static inline void irq_free_desc(unsigned int irq) 953 { 954 irq_free_descs(irq, 1); 955 } 956 957 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ 958 unsigned int irq_alloc_hwirqs(int cnt, int node); 959 static inline unsigned int irq_alloc_hwirq(int node) 960 { 961 return irq_alloc_hwirqs(1, node); 962 } 963 void irq_free_hwirqs(unsigned int from, int cnt); 964 static inline void irq_free_hwirq(unsigned int irq) 965 { 966 return irq_free_hwirqs(irq, 1); 967 } 968 int arch_setup_hwirq(unsigned int irq, int node); 969 void arch_teardown_hwirq(unsigned int irq); 970 #endif 971 972 #ifdef CONFIG_GENERIC_IRQ_LEGACY 973 void irq_init_desc(unsigned int irq); 974 #endif 975 976 /** 977 * struct irq_chip_regs - register offsets for struct irq_gci 978 * @enable: Enable register offset to reg_base 979 * @disable: Disable register offset to reg_base 980 * @mask: Mask register offset to reg_base 981 * @ack: Ack register offset to reg_base 982 * @eoi: Eoi register offset to reg_base 983 * @type: Type configuration register offset to reg_base 984 * @polarity: Polarity configuration register offset to reg_base 985 */ 986 struct irq_chip_regs { 987 unsigned long enable; 988 unsigned long disable; 989 unsigned long mask; 990 unsigned long ack; 991 unsigned long eoi; 992 unsigned long type; 993 unsigned long polarity; 994 }; 995 996 /** 997 * struct irq_chip_type - Generic interrupt chip instance for a flow type 998 * @chip: The real interrupt chip which provides the callbacks 999 * @regs: Register offsets for this chip 1000 * @handler: Flow handler associated with this chip 1001 * @type: Chip can handle these flow types 1002 * @mask_cache_priv: Cached mask register private to the chip type 1003 * @mask_cache: Pointer to cached mask register 1004 * 1005 * A irq_generic_chip can have several instances of irq_chip_type when 1006 * it requires different functions and register offsets for different 1007 * flow types. 1008 */ 1009 struct irq_chip_type { 1010 struct irq_chip chip; 1011 struct irq_chip_regs regs; 1012 irq_flow_handler_t handler; 1013 u32 type; 1014 u32 mask_cache_priv; 1015 u32 *mask_cache; 1016 }; 1017 1018 /** 1019 * struct irq_chip_generic - Generic irq chip data structure 1020 * @lock: Lock to protect register and cache data access 1021 * @reg_base: Register base address (virtual) 1022 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL) 1023 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL) 1024 * @suspend: Function called from core code on suspend once per 1025 * chip; can be useful instead of irq_chip::suspend to 1026 * handle chip details even when no interrupts are in use 1027 * @resume: Function called from core code on resume once per chip; 1028 * can be useful instead of irq_chip::suspend to handle 1029 * chip details even when no interrupts are in use 1030 * @irq_base: Interrupt base nr for this chip 1031 * @irq_cnt: Number of interrupts handled by this chip 1032 * @mask_cache: Cached mask register shared between all chip types 1033 * @type_cache: Cached type register 1034 * @polarity_cache: Cached polarity register 1035 * @wake_enabled: Interrupt can wakeup from suspend 1036 * @wake_active: Interrupt is marked as an wakeup from suspend source 1037 * @num_ct: Number of available irq_chip_type instances (usually 1) 1038 * @private: Private data for non generic chip callbacks 1039 * @installed: bitfield to denote installed interrupts 1040 * @unused: bitfield to denote unused interrupts 1041 * @domain: irq domain pointer 1042 * @list: List head for keeping track of instances 1043 * @chip_types: Array of interrupt irq_chip_types 1044 * 1045 * Note, that irq_chip_generic can have multiple irq_chip_type 1046 * implementations which can be associated to a particular irq line of 1047 * an irq_chip_generic instance. That allows to share and protect 1048 * state in an irq_chip_generic instance when we need to implement 1049 * different flow mechanisms (level/edge) for it. 1050 */ 1051 struct irq_chip_generic { 1052 raw_spinlock_t lock; 1053 void __iomem *reg_base; 1054 u32 (*reg_readl)(void __iomem *addr); 1055 void (*reg_writel)(u32 val, void __iomem *addr); 1056 void (*suspend)(struct irq_chip_generic *gc); 1057 void (*resume)(struct irq_chip_generic *gc); 1058 unsigned int irq_base; 1059 unsigned int irq_cnt; 1060 u32 mask_cache; 1061 u32 type_cache; 1062 u32 polarity_cache; 1063 u32 wake_enabled; 1064 u32 wake_active; 1065 unsigned int num_ct; 1066 void *private; 1067 unsigned long installed; 1068 unsigned long unused; 1069 struct irq_domain *domain; 1070 struct list_head list; 1071 struct irq_chip_type chip_types[]; 1072 }; 1073 1074 /** 1075 * enum irq_gc_flags - Initialization flags for generic irq chips 1076 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg 1077 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for 1078 * irq chips which need to call irq_set_wake() on 1079 * the parent irq. Usually GPIO implementations 1080 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private 1081 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask 1082 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE) 1083 */ 1084 enum irq_gc_flags { 1085 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 1086 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 1087 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, 1088 IRQ_GC_NO_MASK = 1 << 3, 1089 IRQ_GC_BE_IO = 1 << 4, 1090 }; 1091 1092 /* 1093 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains 1094 * @irqs_per_chip: Number of interrupts per chip 1095 * @num_chips: Number of chips 1096 * @irq_flags_to_set: IRQ* flags to set on irq setup 1097 * @irq_flags_to_clear: IRQ* flags to clear on irq setup 1098 * @gc_flags: Generic chip specific setup flags 1099 * @gc: Array of pointers to generic interrupt chips 1100 */ 1101 struct irq_domain_chip_generic { 1102 unsigned int irqs_per_chip; 1103 unsigned int num_chips; 1104 unsigned int irq_flags_to_clear; 1105 unsigned int irq_flags_to_set; 1106 enum irq_gc_flags gc_flags; 1107 struct irq_chip_generic *gc[]; 1108 }; 1109 1110 /* Generic chip callback functions */ 1111 void irq_gc_noop(struct irq_data *d); 1112 void irq_gc_mask_disable_reg(struct irq_data *d); 1113 void irq_gc_mask_set_bit(struct irq_data *d); 1114 void irq_gc_mask_clr_bit(struct irq_data *d); 1115 void irq_gc_unmask_enable_reg(struct irq_data *d); 1116 void irq_gc_ack_set_bit(struct irq_data *d); 1117 void irq_gc_ack_clr_bit(struct irq_data *d); 1118 void irq_gc_mask_disable_and_ack_set(struct irq_data *d); 1119 void irq_gc_eoi(struct irq_data *d); 1120 int irq_gc_set_wake(struct irq_data *d, unsigned int on); 1121 1122 /* Setup functions for irq_chip_generic */ 1123 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, 1124 irq_hw_number_t hw_irq); 1125 struct irq_chip_generic * 1126 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, 1127 void __iomem *reg_base, irq_flow_handler_t handler); 1128 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 1129 enum irq_gc_flags flags, unsigned int clr, 1130 unsigned int set); 1131 int irq_setup_alt_chip(struct irq_data *d, unsigned int type); 1132 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 1133 unsigned int clr, unsigned int set); 1134 1135 struct irq_chip_generic * 1136 devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct, 1137 unsigned int irq_base, void __iomem *reg_base, 1138 irq_flow_handler_t handler); 1139 int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc, 1140 u32 msk, enum irq_gc_flags flags, 1141 unsigned int clr, unsigned int set); 1142 1143 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); 1144 1145 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, 1146 int num_ct, const char *name, 1147 irq_flow_handler_t handler, 1148 unsigned int clr, unsigned int set, 1149 enum irq_gc_flags flags); 1150 1151 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \ 1152 handler, clr, set, flags) \ 1153 ({ \ 1154 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \ 1155 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\ 1156 handler, clr, set, flags); \ 1157 }) 1158 1159 static inline void irq_free_generic_chip(struct irq_chip_generic *gc) 1160 { 1161 kfree(gc); 1162 } 1163 1164 static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc, 1165 u32 msk, unsigned int clr, 1166 unsigned int set) 1167 { 1168 irq_remove_generic_chip(gc, msk, clr, set); 1169 irq_free_generic_chip(gc); 1170 } 1171 1172 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) 1173 { 1174 return container_of(d->chip, struct irq_chip_type, chip); 1175 } 1176 1177 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) 1178 1179 #ifdef CONFIG_SMP 1180 static inline void irq_gc_lock(struct irq_chip_generic *gc) 1181 { 1182 raw_spin_lock(&gc->lock); 1183 } 1184 1185 static inline void irq_gc_unlock(struct irq_chip_generic *gc) 1186 { 1187 raw_spin_unlock(&gc->lock); 1188 } 1189 #else 1190 static inline void irq_gc_lock(struct irq_chip_generic *gc) { } 1191 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } 1192 #endif 1193 1194 /* 1195 * The irqsave variants are for usage in non interrupt code. Do not use 1196 * them in irq_chip callbacks. Use irq_gc_lock() instead. 1197 */ 1198 #define irq_gc_lock_irqsave(gc, flags) \ 1199 raw_spin_lock_irqsave(&(gc)->lock, flags) 1200 1201 #define irq_gc_unlock_irqrestore(gc, flags) \ 1202 raw_spin_unlock_irqrestore(&(gc)->lock, flags) 1203 1204 static inline void irq_reg_writel(struct irq_chip_generic *gc, 1205 u32 val, int reg_offset) 1206 { 1207 if (gc->reg_writel) 1208 gc->reg_writel(val, gc->reg_base + reg_offset); 1209 else 1210 writel(val, gc->reg_base + reg_offset); 1211 } 1212 1213 static inline u32 irq_reg_readl(struct irq_chip_generic *gc, 1214 int reg_offset) 1215 { 1216 if (gc->reg_readl) 1217 return gc->reg_readl(gc->reg_base + reg_offset); 1218 else 1219 return readl(gc->reg_base + reg_offset); 1220 } 1221 1222 struct irq_matrix; 1223 struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits, 1224 unsigned int alloc_start, 1225 unsigned int alloc_end); 1226 void irq_matrix_online(struct irq_matrix *m); 1227 void irq_matrix_offline(struct irq_matrix *m); 1228 void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace); 1229 int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk); 1230 void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk); 1231 int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk, 1232 unsigned int *mapped_cpu); 1233 void irq_matrix_reserve(struct irq_matrix *m); 1234 void irq_matrix_remove_reserved(struct irq_matrix *m); 1235 int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk, 1236 bool reserved, unsigned int *mapped_cpu); 1237 void irq_matrix_free(struct irq_matrix *m, unsigned int cpu, 1238 unsigned int bit, bool managed); 1239 void irq_matrix_assign(struct irq_matrix *m, unsigned int bit); 1240 unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown); 1241 unsigned int irq_matrix_allocated(struct irq_matrix *m); 1242 unsigned int irq_matrix_reserved(struct irq_matrix *m); 1243 void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind); 1244 1245 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */ 1246 #define INVALID_HWIRQ (~0UL) 1247 irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu); 1248 int __ipi_send_single(struct irq_desc *desc, unsigned int cpu); 1249 int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest); 1250 int ipi_send_single(unsigned int virq, unsigned int cpu); 1251 int ipi_send_mask(unsigned int virq, const struct cpumask *dest); 1252 1253 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER 1254 /* 1255 * Registers a generic IRQ handling function as the top-level IRQ handler in 1256 * the system, which is generally the first C code called from an assembly 1257 * architecture-specific interrupt handler. 1258 * 1259 * Returns 0 on success, or -EBUSY if an IRQ handler has already been 1260 * registered. 1261 */ 1262 int __init set_handle_irq(void (*handle_irq)(struct pt_regs *)); 1263 1264 /* 1265 * Allows interrupt handlers to find the irqchip that's been registered as the 1266 * top-level IRQ handler. 1267 */ 1268 extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init; 1269 #else 1270 #define set_handle_irq(handle_irq) \ 1271 do { \ 1272 (void)handle_irq; \ 1273 WARN_ON(1); \ 1274 } while (0) 1275 #endif 1276 1277 #endif /* _LINUX_IRQ_H */ 1278