1 #ifndef _LINUX_IRQ_H 2 #define _LINUX_IRQ_H 3 4 /* 5 * Please do not include this file in generic code. There is currently 6 * no requirement for any architecture to implement anything held 7 * within this file. 8 * 9 * Thanks. --rmk 10 */ 11 12 #include <linux/smp.h> 13 #include <linux/linkage.h> 14 #include <linux/cache.h> 15 #include <linux/spinlock.h> 16 #include <linux/cpumask.h> 17 #include <linux/gfp.h> 18 #include <linux/irqhandler.h> 19 #include <linux/irqreturn.h> 20 #include <linux/irqnr.h> 21 #include <linux/errno.h> 22 #include <linux/topology.h> 23 #include <linux/wait.h> 24 #include <linux/io.h> 25 26 #include <asm/irq.h> 27 #include <asm/ptrace.h> 28 #include <asm/irq_regs.h> 29 30 struct seq_file; 31 struct module; 32 struct msi_msg; 33 enum irqchip_irq_state; 34 35 /* 36 * IRQ line status. 37 * 38 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h 39 * 40 * IRQ_TYPE_NONE - default, unspecified type 41 * IRQ_TYPE_EDGE_RISING - rising edge triggered 42 * IRQ_TYPE_EDGE_FALLING - falling edge triggered 43 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 44 * IRQ_TYPE_LEVEL_HIGH - high level triggered 45 * IRQ_TYPE_LEVEL_LOW - low level triggered 46 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 47 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits 48 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type 49 * to setup the HW to a sane default (used 50 * by irqdomain map() callbacks to synchronize 51 * the HW state and SW flags for a newly 52 * allocated descriptor). 53 * 54 * IRQ_TYPE_PROBE - Special flag for probing in progress 55 * 56 * Bits which can be modified via irq_set/clear/modify_status_flags() 57 * IRQ_LEVEL - Interrupt is level type. Will be also 58 * updated in the code when the above trigger 59 * bits are modified via irq_set_irq_type() 60 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect 61 * it from affinity setting 62 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing 63 * IRQ_NOREQUEST - Interrupt cannot be requested via 64 * request_irq() 65 * IRQ_NOTHREAD - Interrupt cannot be threaded 66 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in 67 * request/setup_irq() 68 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) 69 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context 70 * IRQ_NESTED_TRHEAD - Interrupt nests into another thread 71 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable 72 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude 73 * it from the spurious interrupt detection 74 * mechanism and from core side polling. 75 */ 76 enum { 77 IRQ_TYPE_NONE = 0x00000000, 78 IRQ_TYPE_EDGE_RISING = 0x00000001, 79 IRQ_TYPE_EDGE_FALLING = 0x00000002, 80 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), 81 IRQ_TYPE_LEVEL_HIGH = 0x00000004, 82 IRQ_TYPE_LEVEL_LOW = 0x00000008, 83 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), 84 IRQ_TYPE_SENSE_MASK = 0x0000000f, 85 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, 86 87 IRQ_TYPE_PROBE = 0x00000010, 88 89 IRQ_LEVEL = (1 << 8), 90 IRQ_PER_CPU = (1 << 9), 91 IRQ_NOPROBE = (1 << 10), 92 IRQ_NOREQUEST = (1 << 11), 93 IRQ_NOAUTOEN = (1 << 12), 94 IRQ_NO_BALANCING = (1 << 13), 95 IRQ_MOVE_PCNTXT = (1 << 14), 96 IRQ_NESTED_THREAD = (1 << 15), 97 IRQ_NOTHREAD = (1 << 16), 98 IRQ_PER_CPU_DEVID = (1 << 17), 99 IRQ_IS_POLLED = (1 << 18), 100 }; 101 102 #define IRQF_MODIFY_MASK \ 103 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ 104 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ 105 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ 106 IRQ_IS_POLLED) 107 108 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 109 110 /* 111 * Return value for chip->irq_set_affinity() 112 * 113 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity 114 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity 115 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to 116 * support stacked irqchips, which indicates skipping 117 * all descendent irqchips. 118 */ 119 enum { 120 IRQ_SET_MASK_OK = 0, 121 IRQ_SET_MASK_OK_NOCOPY, 122 IRQ_SET_MASK_OK_DONE, 123 }; 124 125 struct msi_desc; 126 struct irq_domain; 127 128 /** 129 * struct irq_common_data - per irq data shared by all irqchips 130 * @state_use_accessors: status information for irq chip functions. 131 * Use accessor functions to deal with it 132 * @node: node index useful for balancing 133 * @handler_data: per-IRQ data for the irq_chip methods 134 * @affinity: IRQ affinity on SMP 135 * @msi_desc: MSI descriptor 136 */ 137 struct irq_common_data { 138 unsigned int state_use_accessors; 139 #ifdef CONFIG_NUMA 140 unsigned int node; 141 #endif 142 void *handler_data; 143 struct msi_desc *msi_desc; 144 cpumask_var_t affinity; 145 }; 146 147 /** 148 * struct irq_data - per irq chip data passed down to chip functions 149 * @mask: precomputed bitmask for accessing the chip registers 150 * @irq: interrupt number 151 * @hwirq: hardware interrupt number, local to the interrupt domain 152 * @common: point to data shared by all irqchips 153 * @chip: low level interrupt hardware access 154 * @domain: Interrupt translation domain; responsible for mapping 155 * between hwirq number and linux irq number. 156 * @parent_data: pointer to parent struct irq_data to support hierarchy 157 * irq_domain 158 * @chip_data: platform-specific per-chip private data for the chip 159 * methods, to allow shared chip implementations 160 */ 161 struct irq_data { 162 u32 mask; 163 unsigned int irq; 164 unsigned long hwirq; 165 struct irq_common_data *common; 166 struct irq_chip *chip; 167 struct irq_domain *domain; 168 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 169 struct irq_data *parent_data; 170 #endif 171 void *chip_data; 172 }; 173 174 /* 175 * Bit masks for irq_common_data.state_use_accessors 176 * 177 * IRQD_TRIGGER_MASK - Mask for the trigger type bits 178 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 179 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 180 * IRQD_PER_CPU - Interrupt is per cpu 181 * IRQD_AFFINITY_SET - Interrupt affinity was set 182 * IRQD_LEVEL - Interrupt is level triggered 183 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup 184 * from suspend 185 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process 186 * context 187 * IRQD_IRQ_DISABLED - Disabled state of the interrupt 188 * IRQD_IRQ_MASKED - Masked state of the interrupt 189 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt 190 * IRQD_WAKEUP_ARMED - Wakeup mode armed 191 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU 192 */ 193 enum { 194 IRQD_TRIGGER_MASK = 0xf, 195 IRQD_SETAFFINITY_PENDING = (1 << 8), 196 IRQD_NO_BALANCING = (1 << 10), 197 IRQD_PER_CPU = (1 << 11), 198 IRQD_AFFINITY_SET = (1 << 12), 199 IRQD_LEVEL = (1 << 13), 200 IRQD_WAKEUP_STATE = (1 << 14), 201 IRQD_MOVE_PCNTXT = (1 << 15), 202 IRQD_IRQ_DISABLED = (1 << 16), 203 IRQD_IRQ_MASKED = (1 << 17), 204 IRQD_IRQ_INPROGRESS = (1 << 18), 205 IRQD_WAKEUP_ARMED = (1 << 19), 206 IRQD_FORWARDED_TO_VCPU = (1 << 20), 207 }; 208 209 #define __irqd_to_state(d) ((d)->common->state_use_accessors) 210 211 static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 212 { 213 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING; 214 } 215 216 static inline bool irqd_is_per_cpu(struct irq_data *d) 217 { 218 return __irqd_to_state(d) & IRQD_PER_CPU; 219 } 220 221 static inline bool irqd_can_balance(struct irq_data *d) 222 { 223 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); 224 } 225 226 static inline bool irqd_affinity_was_set(struct irq_data *d) 227 { 228 return __irqd_to_state(d) & IRQD_AFFINITY_SET; 229 } 230 231 static inline void irqd_mark_affinity_was_set(struct irq_data *d) 232 { 233 __irqd_to_state(d) |= IRQD_AFFINITY_SET; 234 } 235 236 static inline u32 irqd_get_trigger_type(struct irq_data *d) 237 { 238 return __irqd_to_state(d) & IRQD_TRIGGER_MASK; 239 } 240 241 /* 242 * Must only be called inside irq_chip.irq_set_type() functions. 243 */ 244 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) 245 { 246 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK; 247 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK; 248 } 249 250 static inline bool irqd_is_level_type(struct irq_data *d) 251 { 252 return __irqd_to_state(d) & IRQD_LEVEL; 253 } 254 255 static inline bool irqd_is_wakeup_set(struct irq_data *d) 256 { 257 return __irqd_to_state(d) & IRQD_WAKEUP_STATE; 258 } 259 260 static inline bool irqd_can_move_in_process_context(struct irq_data *d) 261 { 262 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT; 263 } 264 265 static inline bool irqd_irq_disabled(struct irq_data *d) 266 { 267 return __irqd_to_state(d) & IRQD_IRQ_DISABLED; 268 } 269 270 static inline bool irqd_irq_masked(struct irq_data *d) 271 { 272 return __irqd_to_state(d) & IRQD_IRQ_MASKED; 273 } 274 275 static inline bool irqd_irq_inprogress(struct irq_data *d) 276 { 277 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; 278 } 279 280 static inline bool irqd_is_wakeup_armed(struct irq_data *d) 281 { 282 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED; 283 } 284 285 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d) 286 { 287 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU; 288 } 289 290 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d) 291 { 292 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU; 293 } 294 295 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d) 296 { 297 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; 298 } 299 300 /* 301 * Functions for chained handlers which can be enabled/disabled by the 302 * standard disable_irq/enable_irq calls. Must be called with 303 * irq_desc->lock held. 304 */ 305 static inline void irqd_set_chained_irq_inprogress(struct irq_data *d) 306 { 307 __irqd_to_state(d) |= IRQD_IRQ_INPROGRESS; 308 } 309 310 static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d) 311 { 312 __irqd_to_state(d) &= ~IRQD_IRQ_INPROGRESS; 313 } 314 315 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) 316 { 317 return d->hwirq; 318 } 319 320 /** 321 * struct irq_chip - hardware interrupt chip descriptor 322 * 323 * @name: name for /proc/interrupts 324 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 325 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 326 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) 327 * @irq_disable: disable the interrupt 328 * @irq_ack: start of a new interrupt 329 * @irq_mask: mask an interrupt source 330 * @irq_mask_ack: ack and mask an interrupt source 331 * @irq_unmask: unmask an interrupt source 332 * @irq_eoi: end of interrupt 333 * @irq_set_affinity: set the CPU affinity on SMP machines 334 * @irq_retrigger: resend an IRQ to the CPU 335 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ 336 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 337 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 338 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 339 * @irq_cpu_online: configure an interrupt source for a secondary CPU 340 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU 341 * @irq_suspend: function called from core code on suspend once per 342 * chip, when one or more interrupts are installed 343 * @irq_resume: function called from core code on resume once per chip, 344 * when one ore more interrupts are installed 345 * @irq_pm_shutdown: function called from core code on shutdown once per chip 346 * @irq_calc_mask: Optional function to set irq_data.mask for special cases 347 * @irq_print_chip: optional to print special chip info in show_interrupts 348 * @irq_request_resources: optional to request resources before calling 349 * any other callback related to this irq 350 * @irq_release_resources: optional to release resources acquired with 351 * irq_request_resources 352 * @irq_compose_msi_msg: optional to compose message content for MSI 353 * @irq_write_msi_msg: optional to write message content for MSI 354 * @irq_get_irqchip_state: return the internal state of an interrupt 355 * @irq_set_irqchip_state: set the internal state of a interrupt 356 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine 357 * @flags: chip specific flags 358 */ 359 struct irq_chip { 360 const char *name; 361 unsigned int (*irq_startup)(struct irq_data *data); 362 void (*irq_shutdown)(struct irq_data *data); 363 void (*irq_enable)(struct irq_data *data); 364 void (*irq_disable)(struct irq_data *data); 365 366 void (*irq_ack)(struct irq_data *data); 367 void (*irq_mask)(struct irq_data *data); 368 void (*irq_mask_ack)(struct irq_data *data); 369 void (*irq_unmask)(struct irq_data *data); 370 void (*irq_eoi)(struct irq_data *data); 371 372 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); 373 int (*irq_retrigger)(struct irq_data *data); 374 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); 375 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 376 377 void (*irq_bus_lock)(struct irq_data *data); 378 void (*irq_bus_sync_unlock)(struct irq_data *data); 379 380 void (*irq_cpu_online)(struct irq_data *data); 381 void (*irq_cpu_offline)(struct irq_data *data); 382 383 void (*irq_suspend)(struct irq_data *data); 384 void (*irq_resume)(struct irq_data *data); 385 void (*irq_pm_shutdown)(struct irq_data *data); 386 387 void (*irq_calc_mask)(struct irq_data *data); 388 389 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 390 int (*irq_request_resources)(struct irq_data *data); 391 void (*irq_release_resources)(struct irq_data *data); 392 393 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); 394 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); 395 396 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); 397 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); 398 399 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); 400 401 unsigned long flags; 402 }; 403 404 /* 405 * irq_chip specific flags 406 * 407 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() 408 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled 409 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path 410 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks 411 * when irq enabled 412 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip 413 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask 414 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode 415 */ 416 enum { 417 IRQCHIP_SET_TYPE_MASKED = (1 << 0), 418 IRQCHIP_EOI_IF_HANDLED = (1 << 1), 419 IRQCHIP_MASK_ON_SUSPEND = (1 << 2), 420 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), 421 IRQCHIP_SKIP_SET_WAKE = (1 << 4), 422 IRQCHIP_ONESHOT_SAFE = (1 << 5), 423 IRQCHIP_EOI_THREADED = (1 << 6), 424 }; 425 426 #include <linux/irqdesc.h> 427 428 /* 429 * Pick up the arch-dependent methods: 430 */ 431 #include <asm/hw_irq.h> 432 433 #ifndef NR_IRQS_LEGACY 434 # define NR_IRQS_LEGACY 0 435 #endif 436 437 #ifndef ARCH_IRQ_INIT_FLAGS 438 # define ARCH_IRQ_INIT_FLAGS 0 439 #endif 440 441 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS 442 443 struct irqaction; 444 extern int setup_irq(unsigned int irq, struct irqaction *new); 445 extern void remove_irq(unsigned int irq, struct irqaction *act); 446 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); 447 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); 448 449 extern void irq_cpu_online(void); 450 extern void irq_cpu_offline(void); 451 extern int irq_set_affinity_locked(struct irq_data *data, 452 const struct cpumask *cpumask, bool force); 453 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info); 454 455 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) 456 void irq_move_irq(struct irq_data *data); 457 void irq_move_masked_irq(struct irq_data *data); 458 #else 459 static inline void irq_move_irq(struct irq_data *data) { } 460 static inline void irq_move_masked_irq(struct irq_data *data) { } 461 #endif 462 463 extern int no_irq_affinity; 464 465 #ifdef CONFIG_HARDIRQS_SW_RESEND 466 int irq_set_parent(int irq, int parent_irq); 467 #else 468 static inline int irq_set_parent(int irq, int parent_irq) 469 { 470 return 0; 471 } 472 #endif 473 474 /* 475 * Built-in IRQ handlers for various IRQ types, 476 * callable via desc->handle_irq() 477 */ 478 extern void handle_level_irq(struct irq_desc *desc); 479 extern void handle_fasteoi_irq(struct irq_desc *desc); 480 extern void handle_edge_irq(struct irq_desc *desc); 481 extern void handle_edge_eoi_irq(struct irq_desc *desc); 482 extern void handle_simple_irq(struct irq_desc *desc); 483 extern void handle_percpu_irq(struct irq_desc *desc); 484 extern void handle_percpu_devid_irq(struct irq_desc *desc); 485 extern void handle_bad_irq(struct irq_desc *desc); 486 extern void handle_nested_irq(unsigned int irq); 487 488 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); 489 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 490 extern void irq_chip_enable_parent(struct irq_data *data); 491 extern void irq_chip_disable_parent(struct irq_data *data); 492 extern void irq_chip_ack_parent(struct irq_data *data); 493 extern int irq_chip_retrigger_hierarchy(struct irq_data *data); 494 extern void irq_chip_mask_parent(struct irq_data *data); 495 extern void irq_chip_unmask_parent(struct irq_data *data); 496 extern void irq_chip_eoi_parent(struct irq_data *data); 497 extern int irq_chip_set_affinity_parent(struct irq_data *data, 498 const struct cpumask *dest, 499 bool force); 500 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); 501 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, 502 void *vcpu_info); 503 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); 504 #endif 505 506 /* Handling of unhandled and spurious interrupts: */ 507 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret); 508 509 510 /* Enable/disable irq debugging output: */ 511 extern int noirqdebug_setup(char *str); 512 513 /* Checks whether the interrupt can be requested by request_irq(): */ 514 extern int can_request_irq(unsigned int irq, unsigned long irqflags); 515 516 /* Dummy irq-chip implementations: */ 517 extern struct irq_chip no_irq_chip; 518 extern struct irq_chip dummy_irq_chip; 519 520 extern void 521 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, 522 irq_flow_handler_t handle, const char *name); 523 524 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, 525 irq_flow_handler_t handle) 526 { 527 irq_set_chip_and_handler_name(irq, chip, handle, NULL); 528 } 529 530 extern int irq_set_percpu_devid(unsigned int irq); 531 532 extern void 533 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, 534 const char *name); 535 536 static inline void 537 irq_set_handler(unsigned int irq, irq_flow_handler_t handle) 538 { 539 __irq_set_handler(irq, handle, 0, NULL); 540 } 541 542 /* 543 * Set a highlevel chained flow handler for a given IRQ. 544 * (a chained handler is automatically enabled and set to 545 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 546 */ 547 static inline void 548 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) 549 { 550 __irq_set_handler(irq, handle, 1, NULL); 551 } 552 553 /* 554 * Set a highlevel chained flow handler and its data for a given IRQ. 555 * (a chained handler is automatically enabled and set to 556 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 557 */ 558 void 559 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, 560 void *data); 561 562 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); 563 564 static inline void irq_set_status_flags(unsigned int irq, unsigned long set) 565 { 566 irq_modify_status(irq, 0, set); 567 } 568 569 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) 570 { 571 irq_modify_status(irq, clr, 0); 572 } 573 574 static inline void irq_set_noprobe(unsigned int irq) 575 { 576 irq_modify_status(irq, 0, IRQ_NOPROBE); 577 } 578 579 static inline void irq_set_probe(unsigned int irq) 580 { 581 irq_modify_status(irq, IRQ_NOPROBE, 0); 582 } 583 584 static inline void irq_set_nothread(unsigned int irq) 585 { 586 irq_modify_status(irq, 0, IRQ_NOTHREAD); 587 } 588 589 static inline void irq_set_thread(unsigned int irq) 590 { 591 irq_modify_status(irq, IRQ_NOTHREAD, 0); 592 } 593 594 static inline void irq_set_nested_thread(unsigned int irq, bool nest) 595 { 596 if (nest) 597 irq_set_status_flags(irq, IRQ_NESTED_THREAD); 598 else 599 irq_clear_status_flags(irq, IRQ_NESTED_THREAD); 600 } 601 602 static inline void irq_set_percpu_devid_flags(unsigned int irq) 603 { 604 irq_set_status_flags(irq, 605 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | 606 IRQ_NOPROBE | IRQ_PER_CPU_DEVID); 607 } 608 609 /* Set/get chip/data for an IRQ: */ 610 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); 611 extern int irq_set_handler_data(unsigned int irq, void *data); 612 extern int irq_set_chip_data(unsigned int irq, void *data); 613 extern int irq_set_irq_type(unsigned int irq, unsigned int type); 614 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 615 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, 616 struct msi_desc *entry); 617 extern struct irq_data *irq_get_irq_data(unsigned int irq); 618 619 static inline struct irq_chip *irq_get_chip(unsigned int irq) 620 { 621 struct irq_data *d = irq_get_irq_data(irq); 622 return d ? d->chip : NULL; 623 } 624 625 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) 626 { 627 return d->chip; 628 } 629 630 static inline void *irq_get_chip_data(unsigned int irq) 631 { 632 struct irq_data *d = irq_get_irq_data(irq); 633 return d ? d->chip_data : NULL; 634 } 635 636 static inline void *irq_data_get_irq_chip_data(struct irq_data *d) 637 { 638 return d->chip_data; 639 } 640 641 static inline void *irq_get_handler_data(unsigned int irq) 642 { 643 struct irq_data *d = irq_get_irq_data(irq); 644 return d ? d->common->handler_data : NULL; 645 } 646 647 static inline void *irq_data_get_irq_handler_data(struct irq_data *d) 648 { 649 return d->common->handler_data; 650 } 651 652 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) 653 { 654 struct irq_data *d = irq_get_irq_data(irq); 655 return d ? d->common->msi_desc : NULL; 656 } 657 658 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d) 659 { 660 return d->common->msi_desc; 661 } 662 663 static inline u32 irq_get_trigger_type(unsigned int irq) 664 { 665 struct irq_data *d = irq_get_irq_data(irq); 666 return d ? irqd_get_trigger_type(d) : 0; 667 } 668 669 static inline int irq_common_data_get_node(struct irq_common_data *d) 670 { 671 #ifdef CONFIG_NUMA 672 return d->node; 673 #else 674 return 0; 675 #endif 676 } 677 678 static inline int irq_data_get_node(struct irq_data *d) 679 { 680 return irq_common_data_get_node(d->common); 681 } 682 683 static inline struct cpumask *irq_get_affinity_mask(int irq) 684 { 685 struct irq_data *d = irq_get_irq_data(irq); 686 687 return d ? d->common->affinity : NULL; 688 } 689 690 static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d) 691 { 692 return d->common->affinity; 693 } 694 695 unsigned int arch_dynirq_lower_bound(unsigned int from); 696 697 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, 698 struct module *owner); 699 700 /* use macros to avoid needing export.h for THIS_MODULE */ 701 #define irq_alloc_descs(irq, from, cnt, node) \ 702 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE) 703 704 #define irq_alloc_desc(node) \ 705 irq_alloc_descs(-1, 0, 1, node) 706 707 #define irq_alloc_desc_at(at, node) \ 708 irq_alloc_descs(at, at, 1, node) 709 710 #define irq_alloc_desc_from(from, node) \ 711 irq_alloc_descs(-1, from, 1, node) 712 713 #define irq_alloc_descs_from(from, cnt, node) \ 714 irq_alloc_descs(-1, from, cnt, node) 715 716 void irq_free_descs(unsigned int irq, unsigned int cnt); 717 static inline void irq_free_desc(unsigned int irq) 718 { 719 irq_free_descs(irq, 1); 720 } 721 722 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ 723 unsigned int irq_alloc_hwirqs(int cnt, int node); 724 static inline unsigned int irq_alloc_hwirq(int node) 725 { 726 return irq_alloc_hwirqs(1, node); 727 } 728 void irq_free_hwirqs(unsigned int from, int cnt); 729 static inline void irq_free_hwirq(unsigned int irq) 730 { 731 return irq_free_hwirqs(irq, 1); 732 } 733 int arch_setup_hwirq(unsigned int irq, int node); 734 void arch_teardown_hwirq(unsigned int irq); 735 #endif 736 737 #ifdef CONFIG_GENERIC_IRQ_LEGACY 738 void irq_init_desc(unsigned int irq); 739 #endif 740 741 /** 742 * struct irq_chip_regs - register offsets for struct irq_gci 743 * @enable: Enable register offset to reg_base 744 * @disable: Disable register offset to reg_base 745 * @mask: Mask register offset to reg_base 746 * @ack: Ack register offset to reg_base 747 * @eoi: Eoi register offset to reg_base 748 * @type: Type configuration register offset to reg_base 749 * @polarity: Polarity configuration register offset to reg_base 750 */ 751 struct irq_chip_regs { 752 unsigned long enable; 753 unsigned long disable; 754 unsigned long mask; 755 unsigned long ack; 756 unsigned long eoi; 757 unsigned long type; 758 unsigned long polarity; 759 }; 760 761 /** 762 * struct irq_chip_type - Generic interrupt chip instance for a flow type 763 * @chip: The real interrupt chip which provides the callbacks 764 * @regs: Register offsets for this chip 765 * @handler: Flow handler associated with this chip 766 * @type: Chip can handle these flow types 767 * @mask_cache_priv: Cached mask register private to the chip type 768 * @mask_cache: Pointer to cached mask register 769 * 770 * A irq_generic_chip can have several instances of irq_chip_type when 771 * it requires different functions and register offsets for different 772 * flow types. 773 */ 774 struct irq_chip_type { 775 struct irq_chip chip; 776 struct irq_chip_regs regs; 777 irq_flow_handler_t handler; 778 u32 type; 779 u32 mask_cache_priv; 780 u32 *mask_cache; 781 }; 782 783 /** 784 * struct irq_chip_generic - Generic irq chip data structure 785 * @lock: Lock to protect register and cache data access 786 * @reg_base: Register base address (virtual) 787 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL) 788 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL) 789 * @suspend: Function called from core code on suspend once per 790 * chip; can be useful instead of irq_chip::suspend to 791 * handle chip details even when no interrupts are in use 792 * @resume: Function called from core code on resume once per chip; 793 * can be useful instead of irq_chip::suspend to handle 794 * chip details even when no interrupts are in use 795 * @irq_base: Interrupt base nr for this chip 796 * @irq_cnt: Number of interrupts handled by this chip 797 * @mask_cache: Cached mask register shared between all chip types 798 * @type_cache: Cached type register 799 * @polarity_cache: Cached polarity register 800 * @wake_enabled: Interrupt can wakeup from suspend 801 * @wake_active: Interrupt is marked as an wakeup from suspend source 802 * @num_ct: Number of available irq_chip_type instances (usually 1) 803 * @private: Private data for non generic chip callbacks 804 * @installed: bitfield to denote installed interrupts 805 * @unused: bitfield to denote unused interrupts 806 * @domain: irq domain pointer 807 * @list: List head for keeping track of instances 808 * @chip_types: Array of interrupt irq_chip_types 809 * 810 * Note, that irq_chip_generic can have multiple irq_chip_type 811 * implementations which can be associated to a particular irq line of 812 * an irq_chip_generic instance. That allows to share and protect 813 * state in an irq_chip_generic instance when we need to implement 814 * different flow mechanisms (level/edge) for it. 815 */ 816 struct irq_chip_generic { 817 raw_spinlock_t lock; 818 void __iomem *reg_base; 819 u32 (*reg_readl)(void __iomem *addr); 820 void (*reg_writel)(u32 val, void __iomem *addr); 821 void (*suspend)(struct irq_chip_generic *gc); 822 void (*resume)(struct irq_chip_generic *gc); 823 unsigned int irq_base; 824 unsigned int irq_cnt; 825 u32 mask_cache; 826 u32 type_cache; 827 u32 polarity_cache; 828 u32 wake_enabled; 829 u32 wake_active; 830 unsigned int num_ct; 831 void *private; 832 unsigned long installed; 833 unsigned long unused; 834 struct irq_domain *domain; 835 struct list_head list; 836 struct irq_chip_type chip_types[0]; 837 }; 838 839 /** 840 * enum irq_gc_flags - Initialization flags for generic irq chips 841 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg 842 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for 843 * irq chips which need to call irq_set_wake() on 844 * the parent irq. Usually GPIO implementations 845 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private 846 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask 847 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE) 848 */ 849 enum irq_gc_flags { 850 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 851 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 852 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, 853 IRQ_GC_NO_MASK = 1 << 3, 854 IRQ_GC_BE_IO = 1 << 4, 855 }; 856 857 /* 858 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains 859 * @irqs_per_chip: Number of interrupts per chip 860 * @num_chips: Number of chips 861 * @irq_flags_to_set: IRQ* flags to set on irq setup 862 * @irq_flags_to_clear: IRQ* flags to clear on irq setup 863 * @gc_flags: Generic chip specific setup flags 864 * @gc: Array of pointers to generic interrupt chips 865 */ 866 struct irq_domain_chip_generic { 867 unsigned int irqs_per_chip; 868 unsigned int num_chips; 869 unsigned int irq_flags_to_clear; 870 unsigned int irq_flags_to_set; 871 enum irq_gc_flags gc_flags; 872 struct irq_chip_generic *gc[0]; 873 }; 874 875 /* Generic chip callback functions */ 876 void irq_gc_noop(struct irq_data *d); 877 void irq_gc_mask_disable_reg(struct irq_data *d); 878 void irq_gc_mask_set_bit(struct irq_data *d); 879 void irq_gc_mask_clr_bit(struct irq_data *d); 880 void irq_gc_unmask_enable_reg(struct irq_data *d); 881 void irq_gc_ack_set_bit(struct irq_data *d); 882 void irq_gc_ack_clr_bit(struct irq_data *d); 883 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); 884 void irq_gc_eoi(struct irq_data *d); 885 int irq_gc_set_wake(struct irq_data *d, unsigned int on); 886 887 /* Setup functions for irq_chip_generic */ 888 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, 889 irq_hw_number_t hw_irq); 890 struct irq_chip_generic * 891 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, 892 void __iomem *reg_base, irq_flow_handler_t handler); 893 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 894 enum irq_gc_flags flags, unsigned int clr, 895 unsigned int set); 896 int irq_setup_alt_chip(struct irq_data *d, unsigned int type); 897 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 898 unsigned int clr, unsigned int set); 899 900 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); 901 int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, 902 int num_ct, const char *name, 903 irq_flow_handler_t handler, 904 unsigned int clr, unsigned int set, 905 enum irq_gc_flags flags); 906 907 908 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) 909 { 910 return container_of(d->chip, struct irq_chip_type, chip); 911 } 912 913 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) 914 915 #ifdef CONFIG_SMP 916 static inline void irq_gc_lock(struct irq_chip_generic *gc) 917 { 918 raw_spin_lock(&gc->lock); 919 } 920 921 static inline void irq_gc_unlock(struct irq_chip_generic *gc) 922 { 923 raw_spin_unlock(&gc->lock); 924 } 925 #else 926 static inline void irq_gc_lock(struct irq_chip_generic *gc) { } 927 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } 928 #endif 929 930 static inline void irq_reg_writel(struct irq_chip_generic *gc, 931 u32 val, int reg_offset) 932 { 933 if (gc->reg_writel) 934 gc->reg_writel(val, gc->reg_base + reg_offset); 935 else 936 writel(val, gc->reg_base + reg_offset); 937 } 938 939 static inline u32 irq_reg_readl(struct irq_chip_generic *gc, 940 int reg_offset) 941 { 942 if (gc->reg_readl) 943 return gc->reg_readl(gc->reg_base + reg_offset); 944 else 945 return readl(gc->reg_base + reg_offset); 946 } 947 948 #endif /* _LINUX_IRQ_H */ 949