1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_IRQ_H 3 #define _LINUX_IRQ_H 4 5 /* 6 * Please do not include this file in generic code. There is currently 7 * no requirement for any architecture to implement anything held 8 * within this file. 9 * 10 * Thanks. --rmk 11 */ 12 13 #include <linux/smp.h> 14 #include <linux/linkage.h> 15 #include <linux/cache.h> 16 #include <linux/spinlock.h> 17 #include <linux/cpumask.h> 18 #include <linux/gfp.h> 19 #include <linux/irqhandler.h> 20 #include <linux/irqreturn.h> 21 #include <linux/irqnr.h> 22 #include <linux/errno.h> 23 #include <linux/topology.h> 24 #include <linux/wait.h> 25 #include <linux/io.h> 26 #include <linux/slab.h> 27 28 #include <asm/irq.h> 29 #include <asm/ptrace.h> 30 #include <asm/irq_regs.h> 31 32 struct seq_file; 33 struct module; 34 struct msi_msg; 35 enum irqchip_irq_state; 36 37 /* 38 * IRQ line status. 39 * 40 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h 41 * 42 * IRQ_TYPE_NONE - default, unspecified type 43 * IRQ_TYPE_EDGE_RISING - rising edge triggered 44 * IRQ_TYPE_EDGE_FALLING - falling edge triggered 45 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 46 * IRQ_TYPE_LEVEL_HIGH - high level triggered 47 * IRQ_TYPE_LEVEL_LOW - low level triggered 48 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 49 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits 50 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type 51 * to setup the HW to a sane default (used 52 * by irqdomain map() callbacks to synchronize 53 * the HW state and SW flags for a newly 54 * allocated descriptor). 55 * 56 * IRQ_TYPE_PROBE - Special flag for probing in progress 57 * 58 * Bits which can be modified via irq_set/clear/modify_status_flags() 59 * IRQ_LEVEL - Interrupt is level type. Will be also 60 * updated in the code when the above trigger 61 * bits are modified via irq_set_irq_type() 62 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect 63 * it from affinity setting 64 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing 65 * IRQ_NOREQUEST - Interrupt cannot be requested via 66 * request_irq() 67 * IRQ_NOTHREAD - Interrupt cannot be threaded 68 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in 69 * request/setup_irq() 70 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) 71 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context 72 * IRQ_NESTED_THREAD - Interrupt nests into another thread 73 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable 74 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude 75 * it from the spurious interrupt detection 76 * mechanism and from core side polling. 77 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable 78 */ 79 enum { 80 IRQ_TYPE_NONE = 0x00000000, 81 IRQ_TYPE_EDGE_RISING = 0x00000001, 82 IRQ_TYPE_EDGE_FALLING = 0x00000002, 83 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), 84 IRQ_TYPE_LEVEL_HIGH = 0x00000004, 85 IRQ_TYPE_LEVEL_LOW = 0x00000008, 86 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), 87 IRQ_TYPE_SENSE_MASK = 0x0000000f, 88 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, 89 90 IRQ_TYPE_PROBE = 0x00000010, 91 92 IRQ_LEVEL = (1 << 8), 93 IRQ_PER_CPU = (1 << 9), 94 IRQ_NOPROBE = (1 << 10), 95 IRQ_NOREQUEST = (1 << 11), 96 IRQ_NOAUTOEN = (1 << 12), 97 IRQ_NO_BALANCING = (1 << 13), 98 IRQ_MOVE_PCNTXT = (1 << 14), 99 IRQ_NESTED_THREAD = (1 << 15), 100 IRQ_NOTHREAD = (1 << 16), 101 IRQ_PER_CPU_DEVID = (1 << 17), 102 IRQ_IS_POLLED = (1 << 18), 103 IRQ_DISABLE_UNLAZY = (1 << 19), 104 }; 105 106 #define IRQF_MODIFY_MASK \ 107 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ 108 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ 109 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ 110 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY) 111 112 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 113 114 /* 115 * Return value for chip->irq_set_affinity() 116 * 117 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity 118 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity 119 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to 120 * support stacked irqchips, which indicates skipping 121 * all descendent irqchips. 122 */ 123 enum { 124 IRQ_SET_MASK_OK = 0, 125 IRQ_SET_MASK_OK_NOCOPY, 126 IRQ_SET_MASK_OK_DONE, 127 }; 128 129 struct msi_desc; 130 struct irq_domain; 131 132 /** 133 * struct irq_common_data - per irq data shared by all irqchips 134 * @state_use_accessors: status information for irq chip functions. 135 * Use accessor functions to deal with it 136 * @node: node index useful for balancing 137 * @handler_data: per-IRQ data for the irq_chip methods 138 * @affinity: IRQ affinity on SMP. If this is an IPI 139 * related irq, then this is the mask of the 140 * CPUs to which an IPI can be sent. 141 * @effective_affinity: The effective IRQ affinity on SMP as some irq 142 * chips do not allow multi CPU destinations. 143 * A subset of @affinity. 144 * @msi_desc: MSI descriptor 145 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional. 146 */ 147 struct irq_common_data { 148 unsigned int __private state_use_accessors; 149 #ifdef CONFIG_NUMA 150 unsigned int node; 151 #endif 152 void *handler_data; 153 struct msi_desc *msi_desc; 154 cpumask_var_t affinity; 155 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 156 cpumask_var_t effective_affinity; 157 #endif 158 #ifdef CONFIG_GENERIC_IRQ_IPI 159 unsigned int ipi_offset; 160 #endif 161 }; 162 163 /** 164 * struct irq_data - per irq chip data passed down to chip functions 165 * @mask: precomputed bitmask for accessing the chip registers 166 * @irq: interrupt number 167 * @hwirq: hardware interrupt number, local to the interrupt domain 168 * @common: point to data shared by all irqchips 169 * @chip: low level interrupt hardware access 170 * @domain: Interrupt translation domain; responsible for mapping 171 * between hwirq number and linux irq number. 172 * @parent_data: pointer to parent struct irq_data to support hierarchy 173 * irq_domain 174 * @chip_data: platform-specific per-chip private data for the chip 175 * methods, to allow shared chip implementations 176 */ 177 struct irq_data { 178 u32 mask; 179 unsigned int irq; 180 unsigned long hwirq; 181 struct irq_common_data *common; 182 struct irq_chip *chip; 183 struct irq_domain *domain; 184 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 185 struct irq_data *parent_data; 186 #endif 187 void *chip_data; 188 }; 189 190 /* 191 * Bit masks for irq_common_data.state_use_accessors 192 * 193 * IRQD_TRIGGER_MASK - Mask for the trigger type bits 194 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 195 * IRQD_ACTIVATED - Interrupt has already been activated 196 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 197 * IRQD_PER_CPU - Interrupt is per cpu 198 * IRQD_AFFINITY_SET - Interrupt affinity was set 199 * IRQD_LEVEL - Interrupt is level triggered 200 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup 201 * from suspend 202 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process 203 * context 204 * IRQD_IRQ_DISABLED - Disabled state of the interrupt 205 * IRQD_IRQ_MASKED - Masked state of the interrupt 206 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt 207 * IRQD_WAKEUP_ARMED - Wakeup mode armed 208 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU 209 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel 210 * IRQD_IRQ_STARTED - Startup state of the interrupt 211 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity 212 * mask. Applies only to affinity managed irqs. 213 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target 214 */ 215 enum { 216 IRQD_TRIGGER_MASK = 0xf, 217 IRQD_SETAFFINITY_PENDING = (1 << 8), 218 IRQD_ACTIVATED = (1 << 9), 219 IRQD_NO_BALANCING = (1 << 10), 220 IRQD_PER_CPU = (1 << 11), 221 IRQD_AFFINITY_SET = (1 << 12), 222 IRQD_LEVEL = (1 << 13), 223 IRQD_WAKEUP_STATE = (1 << 14), 224 IRQD_MOVE_PCNTXT = (1 << 15), 225 IRQD_IRQ_DISABLED = (1 << 16), 226 IRQD_IRQ_MASKED = (1 << 17), 227 IRQD_IRQ_INPROGRESS = (1 << 18), 228 IRQD_WAKEUP_ARMED = (1 << 19), 229 IRQD_FORWARDED_TO_VCPU = (1 << 20), 230 IRQD_AFFINITY_MANAGED = (1 << 21), 231 IRQD_IRQ_STARTED = (1 << 22), 232 IRQD_MANAGED_SHUTDOWN = (1 << 23), 233 IRQD_SINGLE_TARGET = (1 << 24), 234 }; 235 236 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors) 237 238 static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 239 { 240 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING; 241 } 242 243 static inline bool irqd_is_per_cpu(struct irq_data *d) 244 { 245 return __irqd_to_state(d) & IRQD_PER_CPU; 246 } 247 248 static inline bool irqd_can_balance(struct irq_data *d) 249 { 250 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); 251 } 252 253 static inline bool irqd_affinity_was_set(struct irq_data *d) 254 { 255 return __irqd_to_state(d) & IRQD_AFFINITY_SET; 256 } 257 258 static inline void irqd_mark_affinity_was_set(struct irq_data *d) 259 { 260 __irqd_to_state(d) |= IRQD_AFFINITY_SET; 261 } 262 263 static inline u32 irqd_get_trigger_type(struct irq_data *d) 264 { 265 return __irqd_to_state(d) & IRQD_TRIGGER_MASK; 266 } 267 268 /* 269 * Must only be called inside irq_chip.irq_set_type() functions. 270 */ 271 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) 272 { 273 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK; 274 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK; 275 } 276 277 static inline bool irqd_is_level_type(struct irq_data *d) 278 { 279 return __irqd_to_state(d) & IRQD_LEVEL; 280 } 281 282 /* 283 * Must only be called of irqchip.irq_set_affinity() or low level 284 * hieararchy domain allocation functions. 285 */ 286 static inline void irqd_set_single_target(struct irq_data *d) 287 { 288 __irqd_to_state(d) |= IRQD_SINGLE_TARGET; 289 } 290 291 static inline bool irqd_is_single_target(struct irq_data *d) 292 { 293 return __irqd_to_state(d) & IRQD_SINGLE_TARGET; 294 } 295 296 static inline bool irqd_is_wakeup_set(struct irq_data *d) 297 { 298 return __irqd_to_state(d) & IRQD_WAKEUP_STATE; 299 } 300 301 static inline bool irqd_can_move_in_process_context(struct irq_data *d) 302 { 303 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT; 304 } 305 306 static inline bool irqd_irq_disabled(struct irq_data *d) 307 { 308 return __irqd_to_state(d) & IRQD_IRQ_DISABLED; 309 } 310 311 static inline bool irqd_irq_masked(struct irq_data *d) 312 { 313 return __irqd_to_state(d) & IRQD_IRQ_MASKED; 314 } 315 316 static inline bool irqd_irq_inprogress(struct irq_data *d) 317 { 318 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; 319 } 320 321 static inline bool irqd_is_wakeup_armed(struct irq_data *d) 322 { 323 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED; 324 } 325 326 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d) 327 { 328 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU; 329 } 330 331 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d) 332 { 333 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU; 334 } 335 336 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d) 337 { 338 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; 339 } 340 341 static inline bool irqd_affinity_is_managed(struct irq_data *d) 342 { 343 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED; 344 } 345 346 static inline bool irqd_is_activated(struct irq_data *d) 347 { 348 return __irqd_to_state(d) & IRQD_ACTIVATED; 349 } 350 351 static inline void irqd_set_activated(struct irq_data *d) 352 { 353 __irqd_to_state(d) |= IRQD_ACTIVATED; 354 } 355 356 static inline void irqd_clr_activated(struct irq_data *d) 357 { 358 __irqd_to_state(d) &= ~IRQD_ACTIVATED; 359 } 360 361 static inline bool irqd_is_started(struct irq_data *d) 362 { 363 return __irqd_to_state(d) & IRQD_IRQ_STARTED; 364 } 365 366 static inline bool irqd_is_managed_and_shutdown(struct irq_data *d) 367 { 368 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN; 369 } 370 371 #undef __irqd_to_state 372 373 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) 374 { 375 return d->hwirq; 376 } 377 378 /** 379 * struct irq_chip - hardware interrupt chip descriptor 380 * 381 * @parent_device: pointer to parent device for irqchip 382 * @name: name for /proc/interrupts 383 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 384 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 385 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) 386 * @irq_disable: disable the interrupt 387 * @irq_ack: start of a new interrupt 388 * @irq_mask: mask an interrupt source 389 * @irq_mask_ack: ack and mask an interrupt source 390 * @irq_unmask: unmask an interrupt source 391 * @irq_eoi: end of interrupt 392 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force 393 * argument is true, it tells the driver to 394 * unconditionally apply the affinity setting. Sanity 395 * checks against the supplied affinity mask are not 396 * required. This is used for CPU hotplug where the 397 * target CPU is not yet set in the cpu_online_mask. 398 * @irq_retrigger: resend an IRQ to the CPU 399 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ 400 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 401 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 402 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 403 * @irq_cpu_online: configure an interrupt source for a secondary CPU 404 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU 405 * @irq_suspend: function called from core code on suspend once per 406 * chip, when one or more interrupts are installed 407 * @irq_resume: function called from core code on resume once per chip, 408 * when one ore more interrupts are installed 409 * @irq_pm_shutdown: function called from core code on shutdown once per chip 410 * @irq_calc_mask: Optional function to set irq_data.mask for special cases 411 * @irq_print_chip: optional to print special chip info in show_interrupts 412 * @irq_request_resources: optional to request resources before calling 413 * any other callback related to this irq 414 * @irq_release_resources: optional to release resources acquired with 415 * irq_request_resources 416 * @irq_compose_msi_msg: optional to compose message content for MSI 417 * @irq_write_msi_msg: optional to write message content for MSI 418 * @irq_get_irqchip_state: return the internal state of an interrupt 419 * @irq_set_irqchip_state: set the internal state of a interrupt 420 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine 421 * @ipi_send_single: send a single IPI to destination cpus 422 * @ipi_send_mask: send an IPI to destination cpus in cpumask 423 * @flags: chip specific flags 424 */ 425 struct irq_chip { 426 struct device *parent_device; 427 const char *name; 428 unsigned int (*irq_startup)(struct irq_data *data); 429 void (*irq_shutdown)(struct irq_data *data); 430 void (*irq_enable)(struct irq_data *data); 431 void (*irq_disable)(struct irq_data *data); 432 433 void (*irq_ack)(struct irq_data *data); 434 void (*irq_mask)(struct irq_data *data); 435 void (*irq_mask_ack)(struct irq_data *data); 436 void (*irq_unmask)(struct irq_data *data); 437 void (*irq_eoi)(struct irq_data *data); 438 439 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); 440 int (*irq_retrigger)(struct irq_data *data); 441 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); 442 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 443 444 void (*irq_bus_lock)(struct irq_data *data); 445 void (*irq_bus_sync_unlock)(struct irq_data *data); 446 447 void (*irq_cpu_online)(struct irq_data *data); 448 void (*irq_cpu_offline)(struct irq_data *data); 449 450 void (*irq_suspend)(struct irq_data *data); 451 void (*irq_resume)(struct irq_data *data); 452 void (*irq_pm_shutdown)(struct irq_data *data); 453 454 void (*irq_calc_mask)(struct irq_data *data); 455 456 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 457 int (*irq_request_resources)(struct irq_data *data); 458 void (*irq_release_resources)(struct irq_data *data); 459 460 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); 461 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); 462 463 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); 464 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); 465 466 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); 467 468 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); 469 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); 470 471 unsigned long flags; 472 }; 473 474 /* 475 * irq_chip specific flags 476 * 477 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() 478 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled 479 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path 480 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks 481 * when irq enabled 482 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip 483 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask 484 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode 485 */ 486 enum { 487 IRQCHIP_SET_TYPE_MASKED = (1 << 0), 488 IRQCHIP_EOI_IF_HANDLED = (1 << 1), 489 IRQCHIP_MASK_ON_SUSPEND = (1 << 2), 490 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), 491 IRQCHIP_SKIP_SET_WAKE = (1 << 4), 492 IRQCHIP_ONESHOT_SAFE = (1 << 5), 493 IRQCHIP_EOI_THREADED = (1 << 6), 494 }; 495 496 #include <linux/irqdesc.h> 497 498 /* 499 * Pick up the arch-dependent methods: 500 */ 501 #include <asm/hw_irq.h> 502 503 #ifndef NR_IRQS_LEGACY 504 # define NR_IRQS_LEGACY 0 505 #endif 506 507 #ifndef ARCH_IRQ_INIT_FLAGS 508 # define ARCH_IRQ_INIT_FLAGS 0 509 #endif 510 511 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS 512 513 struct irqaction; 514 extern int setup_irq(unsigned int irq, struct irqaction *new); 515 extern void remove_irq(unsigned int irq, struct irqaction *act); 516 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); 517 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); 518 519 extern void irq_cpu_online(void); 520 extern void irq_cpu_offline(void); 521 extern int irq_set_affinity_locked(struct irq_data *data, 522 const struct cpumask *cpumask, bool force); 523 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info); 524 525 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION) 526 extern void irq_migrate_all_off_this_cpu(void); 527 extern int irq_affinity_online_cpu(unsigned int cpu); 528 #else 529 # define irq_affinity_online_cpu NULL 530 #endif 531 532 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) 533 void irq_move_irq(struct irq_data *data); 534 void irq_move_masked_irq(struct irq_data *data); 535 void irq_force_complete_move(struct irq_desc *desc); 536 #else 537 static inline void irq_move_irq(struct irq_data *data) { } 538 static inline void irq_move_masked_irq(struct irq_data *data) { } 539 static inline void irq_force_complete_move(struct irq_desc *desc) { } 540 #endif 541 542 extern int no_irq_affinity; 543 544 #ifdef CONFIG_HARDIRQS_SW_RESEND 545 int irq_set_parent(int irq, int parent_irq); 546 #else 547 static inline int irq_set_parent(int irq, int parent_irq) 548 { 549 return 0; 550 } 551 #endif 552 553 /* 554 * Built-in IRQ handlers for various IRQ types, 555 * callable via desc->handle_irq() 556 */ 557 extern void handle_level_irq(struct irq_desc *desc); 558 extern void handle_fasteoi_irq(struct irq_desc *desc); 559 extern void handle_edge_irq(struct irq_desc *desc); 560 extern void handle_edge_eoi_irq(struct irq_desc *desc); 561 extern void handle_simple_irq(struct irq_desc *desc); 562 extern void handle_untracked_irq(struct irq_desc *desc); 563 extern void handle_percpu_irq(struct irq_desc *desc); 564 extern void handle_percpu_devid_irq(struct irq_desc *desc); 565 extern void handle_bad_irq(struct irq_desc *desc); 566 extern void handle_nested_irq(unsigned int irq); 567 568 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); 569 extern int irq_chip_pm_get(struct irq_data *data); 570 extern int irq_chip_pm_put(struct irq_data *data); 571 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 572 extern void handle_fasteoi_ack_irq(struct irq_desc *desc); 573 extern void handle_fasteoi_mask_irq(struct irq_desc *desc); 574 extern void irq_chip_enable_parent(struct irq_data *data); 575 extern void irq_chip_disable_parent(struct irq_data *data); 576 extern void irq_chip_ack_parent(struct irq_data *data); 577 extern int irq_chip_retrigger_hierarchy(struct irq_data *data); 578 extern void irq_chip_mask_parent(struct irq_data *data); 579 extern void irq_chip_unmask_parent(struct irq_data *data); 580 extern void irq_chip_eoi_parent(struct irq_data *data); 581 extern int irq_chip_set_affinity_parent(struct irq_data *data, 582 const struct cpumask *dest, 583 bool force); 584 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); 585 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, 586 void *vcpu_info); 587 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); 588 #endif 589 590 /* Handling of unhandled and spurious interrupts: */ 591 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret); 592 593 594 /* Enable/disable irq debugging output: */ 595 extern int noirqdebug_setup(char *str); 596 597 /* Checks whether the interrupt can be requested by request_irq(): */ 598 extern int can_request_irq(unsigned int irq, unsigned long irqflags); 599 600 /* Dummy irq-chip implementations: */ 601 extern struct irq_chip no_irq_chip; 602 extern struct irq_chip dummy_irq_chip; 603 604 extern void 605 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, 606 irq_flow_handler_t handle, const char *name); 607 608 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, 609 irq_flow_handler_t handle) 610 { 611 irq_set_chip_and_handler_name(irq, chip, handle, NULL); 612 } 613 614 extern int irq_set_percpu_devid(unsigned int irq); 615 extern int irq_set_percpu_devid_partition(unsigned int irq, 616 const struct cpumask *affinity); 617 extern int irq_get_percpu_devid_partition(unsigned int irq, 618 struct cpumask *affinity); 619 620 extern void 621 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, 622 const char *name); 623 624 static inline void 625 irq_set_handler(unsigned int irq, irq_flow_handler_t handle) 626 { 627 __irq_set_handler(irq, handle, 0, NULL); 628 } 629 630 /* 631 * Set a highlevel chained flow handler for a given IRQ. 632 * (a chained handler is automatically enabled and set to 633 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 634 */ 635 static inline void 636 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) 637 { 638 __irq_set_handler(irq, handle, 1, NULL); 639 } 640 641 /* 642 * Set a highlevel chained flow handler and its data for a given IRQ. 643 * (a chained handler is automatically enabled and set to 644 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 645 */ 646 void 647 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, 648 void *data); 649 650 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); 651 652 static inline void irq_set_status_flags(unsigned int irq, unsigned long set) 653 { 654 irq_modify_status(irq, 0, set); 655 } 656 657 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) 658 { 659 irq_modify_status(irq, clr, 0); 660 } 661 662 static inline void irq_set_noprobe(unsigned int irq) 663 { 664 irq_modify_status(irq, 0, IRQ_NOPROBE); 665 } 666 667 static inline void irq_set_probe(unsigned int irq) 668 { 669 irq_modify_status(irq, IRQ_NOPROBE, 0); 670 } 671 672 static inline void irq_set_nothread(unsigned int irq) 673 { 674 irq_modify_status(irq, 0, IRQ_NOTHREAD); 675 } 676 677 static inline void irq_set_thread(unsigned int irq) 678 { 679 irq_modify_status(irq, IRQ_NOTHREAD, 0); 680 } 681 682 static inline void irq_set_nested_thread(unsigned int irq, bool nest) 683 { 684 if (nest) 685 irq_set_status_flags(irq, IRQ_NESTED_THREAD); 686 else 687 irq_clear_status_flags(irq, IRQ_NESTED_THREAD); 688 } 689 690 static inline void irq_set_percpu_devid_flags(unsigned int irq) 691 { 692 irq_set_status_flags(irq, 693 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | 694 IRQ_NOPROBE | IRQ_PER_CPU_DEVID); 695 } 696 697 /* Set/get chip/data for an IRQ: */ 698 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); 699 extern int irq_set_handler_data(unsigned int irq, void *data); 700 extern int irq_set_chip_data(unsigned int irq, void *data); 701 extern int irq_set_irq_type(unsigned int irq, unsigned int type); 702 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 703 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, 704 struct msi_desc *entry); 705 extern struct irq_data *irq_get_irq_data(unsigned int irq); 706 707 static inline struct irq_chip *irq_get_chip(unsigned int irq) 708 { 709 struct irq_data *d = irq_get_irq_data(irq); 710 return d ? d->chip : NULL; 711 } 712 713 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) 714 { 715 return d->chip; 716 } 717 718 static inline void *irq_get_chip_data(unsigned int irq) 719 { 720 struct irq_data *d = irq_get_irq_data(irq); 721 return d ? d->chip_data : NULL; 722 } 723 724 static inline void *irq_data_get_irq_chip_data(struct irq_data *d) 725 { 726 return d->chip_data; 727 } 728 729 static inline void *irq_get_handler_data(unsigned int irq) 730 { 731 struct irq_data *d = irq_get_irq_data(irq); 732 return d ? d->common->handler_data : NULL; 733 } 734 735 static inline void *irq_data_get_irq_handler_data(struct irq_data *d) 736 { 737 return d->common->handler_data; 738 } 739 740 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) 741 { 742 struct irq_data *d = irq_get_irq_data(irq); 743 return d ? d->common->msi_desc : NULL; 744 } 745 746 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d) 747 { 748 return d->common->msi_desc; 749 } 750 751 static inline u32 irq_get_trigger_type(unsigned int irq) 752 { 753 struct irq_data *d = irq_get_irq_data(irq); 754 return d ? irqd_get_trigger_type(d) : 0; 755 } 756 757 static inline int irq_common_data_get_node(struct irq_common_data *d) 758 { 759 #ifdef CONFIG_NUMA 760 return d->node; 761 #else 762 return 0; 763 #endif 764 } 765 766 static inline int irq_data_get_node(struct irq_data *d) 767 { 768 return irq_common_data_get_node(d->common); 769 } 770 771 static inline struct cpumask *irq_get_affinity_mask(int irq) 772 { 773 struct irq_data *d = irq_get_irq_data(irq); 774 775 return d ? d->common->affinity : NULL; 776 } 777 778 static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d) 779 { 780 return d->common->affinity; 781 } 782 783 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 784 static inline 785 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 786 { 787 return d->common->effective_affinity; 788 } 789 static inline void irq_data_update_effective_affinity(struct irq_data *d, 790 const struct cpumask *m) 791 { 792 cpumask_copy(d->common->effective_affinity, m); 793 } 794 #else 795 static inline void irq_data_update_effective_affinity(struct irq_data *d, 796 const struct cpumask *m) 797 { 798 } 799 static inline 800 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 801 { 802 return d->common->affinity; 803 } 804 #endif 805 806 unsigned int arch_dynirq_lower_bound(unsigned int from); 807 808 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, 809 struct module *owner, const struct cpumask *affinity); 810 811 int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from, 812 unsigned int cnt, int node, struct module *owner, 813 const struct cpumask *affinity); 814 815 /* use macros to avoid needing export.h for THIS_MODULE */ 816 #define irq_alloc_descs(irq, from, cnt, node) \ 817 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL) 818 819 #define irq_alloc_desc(node) \ 820 irq_alloc_descs(-1, 0, 1, node) 821 822 #define irq_alloc_desc_at(at, node) \ 823 irq_alloc_descs(at, at, 1, node) 824 825 #define irq_alloc_desc_from(from, node) \ 826 irq_alloc_descs(-1, from, 1, node) 827 828 #define irq_alloc_descs_from(from, cnt, node) \ 829 irq_alloc_descs(-1, from, cnt, node) 830 831 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \ 832 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL) 833 834 #define devm_irq_alloc_desc(dev, node) \ 835 devm_irq_alloc_descs(dev, -1, 0, 1, node) 836 837 #define devm_irq_alloc_desc_at(dev, at, node) \ 838 devm_irq_alloc_descs(dev, at, at, 1, node) 839 840 #define devm_irq_alloc_desc_from(dev, from, node) \ 841 devm_irq_alloc_descs(dev, -1, from, 1, node) 842 843 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \ 844 devm_irq_alloc_descs(dev, -1, from, cnt, node) 845 846 void irq_free_descs(unsigned int irq, unsigned int cnt); 847 static inline void irq_free_desc(unsigned int irq) 848 { 849 irq_free_descs(irq, 1); 850 } 851 852 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ 853 unsigned int irq_alloc_hwirqs(int cnt, int node); 854 static inline unsigned int irq_alloc_hwirq(int node) 855 { 856 return irq_alloc_hwirqs(1, node); 857 } 858 void irq_free_hwirqs(unsigned int from, int cnt); 859 static inline void irq_free_hwirq(unsigned int irq) 860 { 861 return irq_free_hwirqs(irq, 1); 862 } 863 int arch_setup_hwirq(unsigned int irq, int node); 864 void arch_teardown_hwirq(unsigned int irq); 865 #endif 866 867 #ifdef CONFIG_GENERIC_IRQ_LEGACY 868 void irq_init_desc(unsigned int irq); 869 #endif 870 871 /** 872 * struct irq_chip_regs - register offsets for struct irq_gci 873 * @enable: Enable register offset to reg_base 874 * @disable: Disable register offset to reg_base 875 * @mask: Mask register offset to reg_base 876 * @ack: Ack register offset to reg_base 877 * @eoi: Eoi register offset to reg_base 878 * @type: Type configuration register offset to reg_base 879 * @polarity: Polarity configuration register offset to reg_base 880 */ 881 struct irq_chip_regs { 882 unsigned long enable; 883 unsigned long disable; 884 unsigned long mask; 885 unsigned long ack; 886 unsigned long eoi; 887 unsigned long type; 888 unsigned long polarity; 889 }; 890 891 /** 892 * struct irq_chip_type - Generic interrupt chip instance for a flow type 893 * @chip: The real interrupt chip which provides the callbacks 894 * @regs: Register offsets for this chip 895 * @handler: Flow handler associated with this chip 896 * @type: Chip can handle these flow types 897 * @mask_cache_priv: Cached mask register private to the chip type 898 * @mask_cache: Pointer to cached mask register 899 * 900 * A irq_generic_chip can have several instances of irq_chip_type when 901 * it requires different functions and register offsets for different 902 * flow types. 903 */ 904 struct irq_chip_type { 905 struct irq_chip chip; 906 struct irq_chip_regs regs; 907 irq_flow_handler_t handler; 908 u32 type; 909 u32 mask_cache_priv; 910 u32 *mask_cache; 911 }; 912 913 /** 914 * struct irq_chip_generic - Generic irq chip data structure 915 * @lock: Lock to protect register and cache data access 916 * @reg_base: Register base address (virtual) 917 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL) 918 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL) 919 * @suspend: Function called from core code on suspend once per 920 * chip; can be useful instead of irq_chip::suspend to 921 * handle chip details even when no interrupts are in use 922 * @resume: Function called from core code on resume once per chip; 923 * can be useful instead of irq_chip::suspend to handle 924 * chip details even when no interrupts are in use 925 * @irq_base: Interrupt base nr for this chip 926 * @irq_cnt: Number of interrupts handled by this chip 927 * @mask_cache: Cached mask register shared between all chip types 928 * @type_cache: Cached type register 929 * @polarity_cache: Cached polarity register 930 * @wake_enabled: Interrupt can wakeup from suspend 931 * @wake_active: Interrupt is marked as an wakeup from suspend source 932 * @num_ct: Number of available irq_chip_type instances (usually 1) 933 * @private: Private data for non generic chip callbacks 934 * @installed: bitfield to denote installed interrupts 935 * @unused: bitfield to denote unused interrupts 936 * @domain: irq domain pointer 937 * @list: List head for keeping track of instances 938 * @chip_types: Array of interrupt irq_chip_types 939 * 940 * Note, that irq_chip_generic can have multiple irq_chip_type 941 * implementations which can be associated to a particular irq line of 942 * an irq_chip_generic instance. That allows to share and protect 943 * state in an irq_chip_generic instance when we need to implement 944 * different flow mechanisms (level/edge) for it. 945 */ 946 struct irq_chip_generic { 947 raw_spinlock_t lock; 948 void __iomem *reg_base; 949 u32 (*reg_readl)(void __iomem *addr); 950 void (*reg_writel)(u32 val, void __iomem *addr); 951 void (*suspend)(struct irq_chip_generic *gc); 952 void (*resume)(struct irq_chip_generic *gc); 953 unsigned int irq_base; 954 unsigned int irq_cnt; 955 u32 mask_cache; 956 u32 type_cache; 957 u32 polarity_cache; 958 u32 wake_enabled; 959 u32 wake_active; 960 unsigned int num_ct; 961 void *private; 962 unsigned long installed; 963 unsigned long unused; 964 struct irq_domain *domain; 965 struct list_head list; 966 struct irq_chip_type chip_types[0]; 967 }; 968 969 /** 970 * enum irq_gc_flags - Initialization flags for generic irq chips 971 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg 972 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for 973 * irq chips which need to call irq_set_wake() on 974 * the parent irq. Usually GPIO implementations 975 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private 976 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask 977 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE) 978 */ 979 enum irq_gc_flags { 980 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 981 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 982 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, 983 IRQ_GC_NO_MASK = 1 << 3, 984 IRQ_GC_BE_IO = 1 << 4, 985 }; 986 987 /* 988 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains 989 * @irqs_per_chip: Number of interrupts per chip 990 * @num_chips: Number of chips 991 * @irq_flags_to_set: IRQ* flags to set on irq setup 992 * @irq_flags_to_clear: IRQ* flags to clear on irq setup 993 * @gc_flags: Generic chip specific setup flags 994 * @gc: Array of pointers to generic interrupt chips 995 */ 996 struct irq_domain_chip_generic { 997 unsigned int irqs_per_chip; 998 unsigned int num_chips; 999 unsigned int irq_flags_to_clear; 1000 unsigned int irq_flags_to_set; 1001 enum irq_gc_flags gc_flags; 1002 struct irq_chip_generic *gc[0]; 1003 }; 1004 1005 /* Generic chip callback functions */ 1006 void irq_gc_noop(struct irq_data *d); 1007 void irq_gc_mask_disable_reg(struct irq_data *d); 1008 void irq_gc_mask_set_bit(struct irq_data *d); 1009 void irq_gc_mask_clr_bit(struct irq_data *d); 1010 void irq_gc_unmask_enable_reg(struct irq_data *d); 1011 void irq_gc_ack_set_bit(struct irq_data *d); 1012 void irq_gc_ack_clr_bit(struct irq_data *d); 1013 void irq_gc_mask_disable_and_ack_set(struct irq_data *d); 1014 void irq_gc_eoi(struct irq_data *d); 1015 int irq_gc_set_wake(struct irq_data *d, unsigned int on); 1016 1017 /* Setup functions for irq_chip_generic */ 1018 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, 1019 irq_hw_number_t hw_irq); 1020 struct irq_chip_generic * 1021 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, 1022 void __iomem *reg_base, irq_flow_handler_t handler); 1023 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 1024 enum irq_gc_flags flags, unsigned int clr, 1025 unsigned int set); 1026 int irq_setup_alt_chip(struct irq_data *d, unsigned int type); 1027 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 1028 unsigned int clr, unsigned int set); 1029 1030 struct irq_chip_generic * 1031 devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct, 1032 unsigned int irq_base, void __iomem *reg_base, 1033 irq_flow_handler_t handler); 1034 int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc, 1035 u32 msk, enum irq_gc_flags flags, 1036 unsigned int clr, unsigned int set); 1037 1038 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); 1039 1040 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, 1041 int num_ct, const char *name, 1042 irq_flow_handler_t handler, 1043 unsigned int clr, unsigned int set, 1044 enum irq_gc_flags flags); 1045 1046 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \ 1047 handler, clr, set, flags) \ 1048 ({ \ 1049 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \ 1050 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\ 1051 handler, clr, set, flags); \ 1052 }) 1053 1054 static inline void irq_free_generic_chip(struct irq_chip_generic *gc) 1055 { 1056 kfree(gc); 1057 } 1058 1059 static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc, 1060 u32 msk, unsigned int clr, 1061 unsigned int set) 1062 { 1063 irq_remove_generic_chip(gc, msk, clr, set); 1064 irq_free_generic_chip(gc); 1065 } 1066 1067 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) 1068 { 1069 return container_of(d->chip, struct irq_chip_type, chip); 1070 } 1071 1072 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) 1073 1074 #ifdef CONFIG_SMP 1075 static inline void irq_gc_lock(struct irq_chip_generic *gc) 1076 { 1077 raw_spin_lock(&gc->lock); 1078 } 1079 1080 static inline void irq_gc_unlock(struct irq_chip_generic *gc) 1081 { 1082 raw_spin_unlock(&gc->lock); 1083 } 1084 #else 1085 static inline void irq_gc_lock(struct irq_chip_generic *gc) { } 1086 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } 1087 #endif 1088 1089 /* 1090 * The irqsave variants are for usage in non interrupt code. Do not use 1091 * them in irq_chip callbacks. Use irq_gc_lock() instead. 1092 */ 1093 #define irq_gc_lock_irqsave(gc, flags) \ 1094 raw_spin_lock_irqsave(&(gc)->lock, flags) 1095 1096 #define irq_gc_unlock_irqrestore(gc, flags) \ 1097 raw_spin_unlock_irqrestore(&(gc)->lock, flags) 1098 1099 static inline void irq_reg_writel(struct irq_chip_generic *gc, 1100 u32 val, int reg_offset) 1101 { 1102 if (gc->reg_writel) 1103 gc->reg_writel(val, gc->reg_base + reg_offset); 1104 else 1105 writel(val, gc->reg_base + reg_offset); 1106 } 1107 1108 static inline u32 irq_reg_readl(struct irq_chip_generic *gc, 1109 int reg_offset) 1110 { 1111 if (gc->reg_readl) 1112 return gc->reg_readl(gc->reg_base + reg_offset); 1113 else 1114 return readl(gc->reg_base + reg_offset); 1115 } 1116 1117 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */ 1118 #define INVALID_HWIRQ (~0UL) 1119 irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu); 1120 int __ipi_send_single(struct irq_desc *desc, unsigned int cpu); 1121 int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest); 1122 int ipi_send_single(unsigned int virq, unsigned int cpu); 1123 int ipi_send_mask(unsigned int virq, const struct cpumask *dest); 1124 1125 #endif /* _LINUX_IRQ_H */ 1126