1 #ifndef _LINUX_IRQ_H 2 #define _LINUX_IRQ_H 3 4 /* 5 * Please do not include this file in generic code. There is currently 6 * no requirement for any architecture to implement anything held 7 * within this file. 8 * 9 * Thanks. --rmk 10 */ 11 12 #include <linux/smp.h> 13 14 #ifndef CONFIG_S390 15 16 #include <linux/linkage.h> 17 #include <linux/cache.h> 18 #include <linux/spinlock.h> 19 #include <linux/cpumask.h> 20 #include <linux/gfp.h> 21 #include <linux/irqreturn.h> 22 #include <linux/irqnr.h> 23 #include <linux/errno.h> 24 #include <linux/topology.h> 25 #include <linux/wait.h> 26 27 #include <asm/irq.h> 28 #include <asm/ptrace.h> 29 #include <asm/irq_regs.h> 30 31 struct seq_file; 32 struct module; 33 struct irq_desc; 34 struct irq_data; 35 typedef void (*irq_flow_handler_t)(unsigned int irq, 36 struct irq_desc *desc); 37 typedef void (*irq_preflow_handler_t)(struct irq_data *data); 38 39 /* 40 * IRQ line status. 41 * 42 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h 43 * 44 * IRQ_TYPE_NONE - default, unspecified type 45 * IRQ_TYPE_EDGE_RISING - rising edge triggered 46 * IRQ_TYPE_EDGE_FALLING - falling edge triggered 47 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 48 * IRQ_TYPE_LEVEL_HIGH - high level triggered 49 * IRQ_TYPE_LEVEL_LOW - low level triggered 50 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 51 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits 52 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type 53 * to setup the HW to a sane default (used 54 * by irqdomain map() callbacks to synchronize 55 * the HW state and SW flags for a newly 56 * allocated descriptor). 57 * 58 * IRQ_TYPE_PROBE - Special flag for probing in progress 59 * 60 * Bits which can be modified via irq_set/clear/modify_status_flags() 61 * IRQ_LEVEL - Interrupt is level type. Will be also 62 * updated in the code when the above trigger 63 * bits are modified via irq_set_irq_type() 64 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect 65 * it from affinity setting 66 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing 67 * IRQ_NOREQUEST - Interrupt cannot be requested via 68 * request_irq() 69 * IRQ_NOTHREAD - Interrupt cannot be threaded 70 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in 71 * request/setup_irq() 72 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) 73 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context 74 * IRQ_NESTED_TRHEAD - Interrupt nests into another thread 75 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable 76 */ 77 enum { 78 IRQ_TYPE_NONE = 0x00000000, 79 IRQ_TYPE_EDGE_RISING = 0x00000001, 80 IRQ_TYPE_EDGE_FALLING = 0x00000002, 81 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), 82 IRQ_TYPE_LEVEL_HIGH = 0x00000004, 83 IRQ_TYPE_LEVEL_LOW = 0x00000008, 84 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), 85 IRQ_TYPE_SENSE_MASK = 0x0000000f, 86 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, 87 88 IRQ_TYPE_PROBE = 0x00000010, 89 90 IRQ_LEVEL = (1 << 8), 91 IRQ_PER_CPU = (1 << 9), 92 IRQ_NOPROBE = (1 << 10), 93 IRQ_NOREQUEST = (1 << 11), 94 IRQ_NOAUTOEN = (1 << 12), 95 IRQ_NO_BALANCING = (1 << 13), 96 IRQ_MOVE_PCNTXT = (1 << 14), 97 IRQ_NESTED_THREAD = (1 << 15), 98 IRQ_NOTHREAD = (1 << 16), 99 IRQ_PER_CPU_DEVID = (1 << 17), 100 }; 101 102 #define IRQF_MODIFY_MASK \ 103 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ 104 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ 105 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID) 106 107 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 108 109 /* 110 * Return value for chip->irq_set_affinity() 111 * 112 * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity 113 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity 114 */ 115 enum { 116 IRQ_SET_MASK_OK = 0, 117 IRQ_SET_MASK_OK_NOCOPY, 118 }; 119 120 struct msi_desc; 121 struct irq_domain; 122 123 /** 124 * struct irq_data - per irq and irq chip data passed down to chip functions 125 * @irq: interrupt number 126 * @hwirq: hardware interrupt number, local to the interrupt domain 127 * @node: node index useful for balancing 128 * @state_use_accessors: status information for irq chip functions. 129 * Use accessor functions to deal with it 130 * @chip: low level interrupt hardware access 131 * @domain: Interrupt translation domain; responsible for mapping 132 * between hwirq number and linux irq number. 133 * @handler_data: per-IRQ data for the irq_chip methods 134 * @chip_data: platform-specific per-chip private data for the chip 135 * methods, to allow shared chip implementations 136 * @msi_desc: MSI descriptor 137 * @affinity: IRQ affinity on SMP 138 * 139 * The fields here need to overlay the ones in irq_desc until we 140 * cleaned up the direct references and switched everything over to 141 * irq_data. 142 */ 143 struct irq_data { 144 unsigned int irq; 145 unsigned long hwirq; 146 unsigned int node; 147 unsigned int state_use_accessors; 148 struct irq_chip *chip; 149 struct irq_domain *domain; 150 void *handler_data; 151 void *chip_data; 152 struct msi_desc *msi_desc; 153 cpumask_var_t affinity; 154 }; 155 156 /* 157 * Bit masks for irq_data.state 158 * 159 * IRQD_TRIGGER_MASK - Mask for the trigger type bits 160 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 161 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 162 * IRQD_PER_CPU - Interrupt is per cpu 163 * IRQD_AFFINITY_SET - Interrupt affinity was set 164 * IRQD_LEVEL - Interrupt is level triggered 165 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup 166 * from suspend 167 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process 168 * context 169 * IRQD_IRQ_DISABLED - Disabled state of the interrupt 170 * IRQD_IRQ_MASKED - Masked state of the interrupt 171 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt 172 */ 173 enum { 174 IRQD_TRIGGER_MASK = 0xf, 175 IRQD_SETAFFINITY_PENDING = (1 << 8), 176 IRQD_NO_BALANCING = (1 << 10), 177 IRQD_PER_CPU = (1 << 11), 178 IRQD_AFFINITY_SET = (1 << 12), 179 IRQD_LEVEL = (1 << 13), 180 IRQD_WAKEUP_STATE = (1 << 14), 181 IRQD_MOVE_PCNTXT = (1 << 15), 182 IRQD_IRQ_DISABLED = (1 << 16), 183 IRQD_IRQ_MASKED = (1 << 17), 184 IRQD_IRQ_INPROGRESS = (1 << 18), 185 }; 186 187 static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 188 { 189 return d->state_use_accessors & IRQD_SETAFFINITY_PENDING; 190 } 191 192 static inline bool irqd_is_per_cpu(struct irq_data *d) 193 { 194 return d->state_use_accessors & IRQD_PER_CPU; 195 } 196 197 static inline bool irqd_can_balance(struct irq_data *d) 198 { 199 return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING)); 200 } 201 202 static inline bool irqd_affinity_was_set(struct irq_data *d) 203 { 204 return d->state_use_accessors & IRQD_AFFINITY_SET; 205 } 206 207 static inline void irqd_mark_affinity_was_set(struct irq_data *d) 208 { 209 d->state_use_accessors |= IRQD_AFFINITY_SET; 210 } 211 212 static inline u32 irqd_get_trigger_type(struct irq_data *d) 213 { 214 return d->state_use_accessors & IRQD_TRIGGER_MASK; 215 } 216 217 /* 218 * Must only be called inside irq_chip.irq_set_type() functions. 219 */ 220 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) 221 { 222 d->state_use_accessors &= ~IRQD_TRIGGER_MASK; 223 d->state_use_accessors |= type & IRQD_TRIGGER_MASK; 224 } 225 226 static inline bool irqd_is_level_type(struct irq_data *d) 227 { 228 return d->state_use_accessors & IRQD_LEVEL; 229 } 230 231 static inline bool irqd_is_wakeup_set(struct irq_data *d) 232 { 233 return d->state_use_accessors & IRQD_WAKEUP_STATE; 234 } 235 236 static inline bool irqd_can_move_in_process_context(struct irq_data *d) 237 { 238 return d->state_use_accessors & IRQD_MOVE_PCNTXT; 239 } 240 241 static inline bool irqd_irq_disabled(struct irq_data *d) 242 { 243 return d->state_use_accessors & IRQD_IRQ_DISABLED; 244 } 245 246 static inline bool irqd_irq_masked(struct irq_data *d) 247 { 248 return d->state_use_accessors & IRQD_IRQ_MASKED; 249 } 250 251 static inline bool irqd_irq_inprogress(struct irq_data *d) 252 { 253 return d->state_use_accessors & IRQD_IRQ_INPROGRESS; 254 } 255 256 /* 257 * Functions for chained handlers which can be enabled/disabled by the 258 * standard disable_irq/enable_irq calls. Must be called with 259 * irq_desc->lock held. 260 */ 261 static inline void irqd_set_chained_irq_inprogress(struct irq_data *d) 262 { 263 d->state_use_accessors |= IRQD_IRQ_INPROGRESS; 264 } 265 266 static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d) 267 { 268 d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS; 269 } 270 271 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) 272 { 273 return d->hwirq; 274 } 275 276 /** 277 * struct irq_chip - hardware interrupt chip descriptor 278 * 279 * @name: name for /proc/interrupts 280 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 281 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 282 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) 283 * @irq_disable: disable the interrupt 284 * @irq_ack: start of a new interrupt 285 * @irq_mask: mask an interrupt source 286 * @irq_mask_ack: ack and mask an interrupt source 287 * @irq_unmask: unmask an interrupt source 288 * @irq_eoi: end of interrupt 289 * @irq_set_affinity: set the CPU affinity on SMP machines 290 * @irq_retrigger: resend an IRQ to the CPU 291 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ 292 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 293 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 294 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 295 * @irq_cpu_online: configure an interrupt source for a secondary CPU 296 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU 297 * @irq_suspend: function called from core code on suspend once per chip 298 * @irq_resume: function called from core code on resume once per chip 299 * @irq_pm_shutdown: function called from core code on shutdown once per chip 300 * @irq_print_chip: optional to print special chip info in show_interrupts 301 * @flags: chip specific flags 302 */ 303 struct irq_chip { 304 const char *name; 305 unsigned int (*irq_startup)(struct irq_data *data); 306 void (*irq_shutdown)(struct irq_data *data); 307 void (*irq_enable)(struct irq_data *data); 308 void (*irq_disable)(struct irq_data *data); 309 310 void (*irq_ack)(struct irq_data *data); 311 void (*irq_mask)(struct irq_data *data); 312 void (*irq_mask_ack)(struct irq_data *data); 313 void (*irq_unmask)(struct irq_data *data); 314 void (*irq_eoi)(struct irq_data *data); 315 316 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); 317 int (*irq_retrigger)(struct irq_data *data); 318 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); 319 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 320 321 void (*irq_bus_lock)(struct irq_data *data); 322 void (*irq_bus_sync_unlock)(struct irq_data *data); 323 324 void (*irq_cpu_online)(struct irq_data *data); 325 void (*irq_cpu_offline)(struct irq_data *data); 326 327 void (*irq_suspend)(struct irq_data *data); 328 void (*irq_resume)(struct irq_data *data); 329 void (*irq_pm_shutdown)(struct irq_data *data); 330 331 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 332 333 unsigned long flags; 334 }; 335 336 /* 337 * irq_chip specific flags 338 * 339 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() 340 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled 341 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path 342 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks 343 * when irq enabled 344 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip 345 */ 346 enum { 347 IRQCHIP_SET_TYPE_MASKED = (1 << 0), 348 IRQCHIP_EOI_IF_HANDLED = (1 << 1), 349 IRQCHIP_MASK_ON_SUSPEND = (1 << 2), 350 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), 351 IRQCHIP_SKIP_SET_WAKE = (1 << 4), 352 IRQCHIP_ONESHOT_SAFE = (1 << 5), 353 }; 354 355 /* This include will go away once we isolated irq_desc usage to core code */ 356 #include <linux/irqdesc.h> 357 358 /* 359 * Pick up the arch-dependent methods: 360 */ 361 #include <asm/hw_irq.h> 362 363 #ifndef NR_IRQS_LEGACY 364 # define NR_IRQS_LEGACY 0 365 #endif 366 367 #ifndef ARCH_IRQ_INIT_FLAGS 368 # define ARCH_IRQ_INIT_FLAGS 0 369 #endif 370 371 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS 372 373 struct irqaction; 374 extern int setup_irq(unsigned int irq, struct irqaction *new); 375 extern void remove_irq(unsigned int irq, struct irqaction *act); 376 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); 377 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); 378 379 extern void irq_cpu_online(void); 380 extern void irq_cpu_offline(void); 381 extern int __irq_set_affinity_locked(struct irq_data *data, const struct cpumask *cpumask); 382 383 #ifdef CONFIG_GENERIC_HARDIRQS 384 385 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) 386 void irq_move_irq(struct irq_data *data); 387 void irq_move_masked_irq(struct irq_data *data); 388 #else 389 static inline void irq_move_irq(struct irq_data *data) { } 390 static inline void irq_move_masked_irq(struct irq_data *data) { } 391 #endif 392 393 extern int no_irq_affinity; 394 395 #ifdef CONFIG_HARDIRQS_SW_RESEND 396 int irq_set_parent(int irq, int parent_irq); 397 #else 398 static inline int irq_set_parent(int irq, int parent_irq) 399 { 400 return 0; 401 } 402 #endif 403 404 /* 405 * Built-in IRQ handlers for various IRQ types, 406 * callable via desc->handle_irq() 407 */ 408 extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); 409 extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); 410 extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); 411 extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc); 412 extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); 413 extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); 414 extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc); 415 extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); 416 extern void handle_nested_irq(unsigned int irq); 417 418 /* Handling of unhandled and spurious interrupts: */ 419 extern void note_interrupt(unsigned int irq, struct irq_desc *desc, 420 irqreturn_t action_ret); 421 422 423 /* Enable/disable irq debugging output: */ 424 extern int noirqdebug_setup(char *str); 425 426 /* Checks whether the interrupt can be requested by request_irq(): */ 427 extern int can_request_irq(unsigned int irq, unsigned long irqflags); 428 429 /* Dummy irq-chip implementations: */ 430 extern struct irq_chip no_irq_chip; 431 extern struct irq_chip dummy_irq_chip; 432 433 extern void 434 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, 435 irq_flow_handler_t handle, const char *name); 436 437 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, 438 irq_flow_handler_t handle) 439 { 440 irq_set_chip_and_handler_name(irq, chip, handle, NULL); 441 } 442 443 extern int irq_set_percpu_devid(unsigned int irq); 444 445 extern void 446 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, 447 const char *name); 448 449 static inline void 450 irq_set_handler(unsigned int irq, irq_flow_handler_t handle) 451 { 452 __irq_set_handler(irq, handle, 0, NULL); 453 } 454 455 /* 456 * Set a highlevel chained flow handler for a given IRQ. 457 * (a chained handler is automatically enabled and set to 458 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 459 */ 460 static inline void 461 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) 462 { 463 __irq_set_handler(irq, handle, 1, NULL); 464 } 465 466 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); 467 468 static inline void irq_set_status_flags(unsigned int irq, unsigned long set) 469 { 470 irq_modify_status(irq, 0, set); 471 } 472 473 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) 474 { 475 irq_modify_status(irq, clr, 0); 476 } 477 478 static inline void irq_set_noprobe(unsigned int irq) 479 { 480 irq_modify_status(irq, 0, IRQ_NOPROBE); 481 } 482 483 static inline void irq_set_probe(unsigned int irq) 484 { 485 irq_modify_status(irq, IRQ_NOPROBE, 0); 486 } 487 488 static inline void irq_set_nothread(unsigned int irq) 489 { 490 irq_modify_status(irq, 0, IRQ_NOTHREAD); 491 } 492 493 static inline void irq_set_thread(unsigned int irq) 494 { 495 irq_modify_status(irq, IRQ_NOTHREAD, 0); 496 } 497 498 static inline void irq_set_nested_thread(unsigned int irq, bool nest) 499 { 500 if (nest) 501 irq_set_status_flags(irq, IRQ_NESTED_THREAD); 502 else 503 irq_clear_status_flags(irq, IRQ_NESTED_THREAD); 504 } 505 506 static inline void irq_set_percpu_devid_flags(unsigned int irq) 507 { 508 irq_set_status_flags(irq, 509 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | 510 IRQ_NOPROBE | IRQ_PER_CPU_DEVID); 511 } 512 513 /* Handle dynamic irq creation and destruction */ 514 extern unsigned int create_irq_nr(unsigned int irq_want, int node); 515 extern int create_irq(void); 516 extern void destroy_irq(unsigned int irq); 517 518 /* 519 * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and 520 * irq_free_desc instead. 521 */ 522 extern void dynamic_irq_cleanup(unsigned int irq); 523 static inline void dynamic_irq_init(unsigned int irq) 524 { 525 dynamic_irq_cleanup(irq); 526 } 527 528 /* Set/get chip/data for an IRQ: */ 529 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); 530 extern int irq_set_handler_data(unsigned int irq, void *data); 531 extern int irq_set_chip_data(unsigned int irq, void *data); 532 extern int irq_set_irq_type(unsigned int irq, unsigned int type); 533 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 534 extern struct irq_data *irq_get_irq_data(unsigned int irq); 535 536 static inline struct irq_chip *irq_get_chip(unsigned int irq) 537 { 538 struct irq_data *d = irq_get_irq_data(irq); 539 return d ? d->chip : NULL; 540 } 541 542 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) 543 { 544 return d->chip; 545 } 546 547 static inline void *irq_get_chip_data(unsigned int irq) 548 { 549 struct irq_data *d = irq_get_irq_data(irq); 550 return d ? d->chip_data : NULL; 551 } 552 553 static inline void *irq_data_get_irq_chip_data(struct irq_data *d) 554 { 555 return d->chip_data; 556 } 557 558 static inline void *irq_get_handler_data(unsigned int irq) 559 { 560 struct irq_data *d = irq_get_irq_data(irq); 561 return d ? d->handler_data : NULL; 562 } 563 564 static inline void *irq_data_get_irq_handler_data(struct irq_data *d) 565 { 566 return d->handler_data; 567 } 568 569 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) 570 { 571 struct irq_data *d = irq_get_irq_data(irq); 572 return d ? d->msi_desc : NULL; 573 } 574 575 static inline struct msi_desc *irq_data_get_msi(struct irq_data *d) 576 { 577 return d->msi_desc; 578 } 579 580 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, 581 struct module *owner); 582 583 /* use macros to avoid needing export.h for THIS_MODULE */ 584 #define irq_alloc_descs(irq, from, cnt, node) \ 585 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE) 586 587 #define irq_alloc_desc(node) \ 588 irq_alloc_descs(-1, 0, 1, node) 589 590 #define irq_alloc_desc_at(at, node) \ 591 irq_alloc_descs(at, at, 1, node) 592 593 #define irq_alloc_desc_from(from, node) \ 594 irq_alloc_descs(-1, from, 1, node) 595 596 void irq_free_descs(unsigned int irq, unsigned int cnt); 597 int irq_reserve_irqs(unsigned int from, unsigned int cnt); 598 599 static inline void irq_free_desc(unsigned int irq) 600 { 601 irq_free_descs(irq, 1); 602 } 603 604 static inline int irq_reserve_irq(unsigned int irq) 605 { 606 return irq_reserve_irqs(irq, 1); 607 } 608 609 #ifndef irq_reg_writel 610 # define irq_reg_writel(val, addr) writel(val, addr) 611 #endif 612 #ifndef irq_reg_readl 613 # define irq_reg_readl(addr) readl(addr) 614 #endif 615 616 /** 617 * struct irq_chip_regs - register offsets for struct irq_gci 618 * @enable: Enable register offset to reg_base 619 * @disable: Disable register offset to reg_base 620 * @mask: Mask register offset to reg_base 621 * @ack: Ack register offset to reg_base 622 * @eoi: Eoi register offset to reg_base 623 * @type: Type configuration register offset to reg_base 624 * @polarity: Polarity configuration register offset to reg_base 625 */ 626 struct irq_chip_regs { 627 unsigned long enable; 628 unsigned long disable; 629 unsigned long mask; 630 unsigned long ack; 631 unsigned long eoi; 632 unsigned long type; 633 unsigned long polarity; 634 }; 635 636 /** 637 * struct irq_chip_type - Generic interrupt chip instance for a flow type 638 * @chip: The real interrupt chip which provides the callbacks 639 * @regs: Register offsets for this chip 640 * @handler: Flow handler associated with this chip 641 * @type: Chip can handle these flow types 642 * 643 * A irq_generic_chip can have several instances of irq_chip_type when 644 * it requires different functions and register offsets for different 645 * flow types. 646 */ 647 struct irq_chip_type { 648 struct irq_chip chip; 649 struct irq_chip_regs regs; 650 irq_flow_handler_t handler; 651 u32 type; 652 }; 653 654 /** 655 * struct irq_chip_generic - Generic irq chip data structure 656 * @lock: Lock to protect register and cache data access 657 * @reg_base: Register base address (virtual) 658 * @irq_base: Interrupt base nr for this chip 659 * @irq_cnt: Number of interrupts handled by this chip 660 * @mask_cache: Cached mask register 661 * @type_cache: Cached type register 662 * @polarity_cache: Cached polarity register 663 * @wake_enabled: Interrupt can wakeup from suspend 664 * @wake_active: Interrupt is marked as an wakeup from suspend source 665 * @num_ct: Number of available irq_chip_type instances (usually 1) 666 * @private: Private data for non generic chip callbacks 667 * @list: List head for keeping track of instances 668 * @chip_types: Array of interrupt irq_chip_types 669 * 670 * Note, that irq_chip_generic can have multiple irq_chip_type 671 * implementations which can be associated to a particular irq line of 672 * an irq_chip_generic instance. That allows to share and protect 673 * state in an irq_chip_generic instance when we need to implement 674 * different flow mechanisms (level/edge) for it. 675 */ 676 struct irq_chip_generic { 677 raw_spinlock_t lock; 678 void __iomem *reg_base; 679 unsigned int irq_base; 680 unsigned int irq_cnt; 681 u32 mask_cache; 682 u32 type_cache; 683 u32 polarity_cache; 684 u32 wake_enabled; 685 u32 wake_active; 686 unsigned int num_ct; 687 void *private; 688 struct list_head list; 689 struct irq_chip_type chip_types[0]; 690 }; 691 692 /** 693 * enum irq_gc_flags - Initialization flags for generic irq chips 694 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg 695 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for 696 * irq chips which need to call irq_set_wake() on 697 * the parent irq. Usually GPIO implementations 698 */ 699 enum irq_gc_flags { 700 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 701 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 702 }; 703 704 /* Generic chip callback functions */ 705 void irq_gc_noop(struct irq_data *d); 706 void irq_gc_mask_disable_reg(struct irq_data *d); 707 void irq_gc_mask_set_bit(struct irq_data *d); 708 void irq_gc_mask_clr_bit(struct irq_data *d); 709 void irq_gc_unmask_enable_reg(struct irq_data *d); 710 void irq_gc_ack_set_bit(struct irq_data *d); 711 void irq_gc_ack_clr_bit(struct irq_data *d); 712 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); 713 void irq_gc_eoi(struct irq_data *d); 714 int irq_gc_set_wake(struct irq_data *d, unsigned int on); 715 716 /* Setup functions for irq_chip_generic */ 717 struct irq_chip_generic * 718 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, 719 void __iomem *reg_base, irq_flow_handler_t handler); 720 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 721 enum irq_gc_flags flags, unsigned int clr, 722 unsigned int set); 723 int irq_setup_alt_chip(struct irq_data *d, unsigned int type); 724 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 725 unsigned int clr, unsigned int set); 726 727 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) 728 { 729 return container_of(d->chip, struct irq_chip_type, chip); 730 } 731 732 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) 733 734 #ifdef CONFIG_SMP 735 static inline void irq_gc_lock(struct irq_chip_generic *gc) 736 { 737 raw_spin_lock(&gc->lock); 738 } 739 740 static inline void irq_gc_unlock(struct irq_chip_generic *gc) 741 { 742 raw_spin_unlock(&gc->lock); 743 } 744 #else 745 static inline void irq_gc_lock(struct irq_chip_generic *gc) { } 746 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } 747 #endif 748 749 #endif /* CONFIG_GENERIC_HARDIRQS */ 750 751 #endif /* !CONFIG_S390 */ 752 753 #endif /* _LINUX_IRQ_H */ 754