1 #ifndef _LINUX_IRQ_H 2 #define _LINUX_IRQ_H 3 4 /* 5 * Please do not include this file in generic code. There is currently 6 * no requirement for any architecture to implement anything held 7 * within this file. 8 * 9 * Thanks. --rmk 10 */ 11 12 #include <linux/smp.h> 13 14 #ifndef CONFIG_S390 15 16 #include <linux/linkage.h> 17 #include <linux/cache.h> 18 #include <linux/spinlock.h> 19 #include <linux/cpumask.h> 20 #include <linux/gfp.h> 21 #include <linux/irqreturn.h> 22 #include <linux/irqnr.h> 23 #include <linux/errno.h> 24 #include <linux/topology.h> 25 #include <linux/wait.h> 26 #include <linux/module.h> 27 28 #include <asm/irq.h> 29 #include <asm/ptrace.h> 30 #include <asm/irq_regs.h> 31 32 struct seq_file; 33 struct irq_desc; 34 struct irq_data; 35 typedef void (*irq_flow_handler_t)(unsigned int irq, 36 struct irq_desc *desc); 37 typedef void (*irq_preflow_handler_t)(struct irq_data *data); 38 39 /* 40 * IRQ line status. 41 * 42 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h 43 * 44 * IRQ_TYPE_NONE - default, unspecified type 45 * IRQ_TYPE_EDGE_RISING - rising edge triggered 46 * IRQ_TYPE_EDGE_FALLING - falling edge triggered 47 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 48 * IRQ_TYPE_LEVEL_HIGH - high level triggered 49 * IRQ_TYPE_LEVEL_LOW - low level triggered 50 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 51 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits 52 * IRQ_TYPE_PROBE - Special flag for probing in progress 53 * 54 * Bits which can be modified via irq_set/clear/modify_status_flags() 55 * IRQ_LEVEL - Interrupt is level type. Will be also 56 * updated in the code when the above trigger 57 * bits are modified via irq_set_irq_type() 58 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect 59 * it from affinity setting 60 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing 61 * IRQ_NOREQUEST - Interrupt cannot be requested via 62 * request_irq() 63 * IRQ_NOTHREAD - Interrupt cannot be threaded 64 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in 65 * request/setup_irq() 66 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) 67 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context 68 * IRQ_NESTED_TRHEAD - Interrupt nests into another thread 69 */ 70 enum { 71 IRQ_TYPE_NONE = 0x00000000, 72 IRQ_TYPE_EDGE_RISING = 0x00000001, 73 IRQ_TYPE_EDGE_FALLING = 0x00000002, 74 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), 75 IRQ_TYPE_LEVEL_HIGH = 0x00000004, 76 IRQ_TYPE_LEVEL_LOW = 0x00000008, 77 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), 78 IRQ_TYPE_SENSE_MASK = 0x0000000f, 79 80 IRQ_TYPE_PROBE = 0x00000010, 81 82 IRQ_LEVEL = (1 << 8), 83 IRQ_PER_CPU = (1 << 9), 84 IRQ_NOPROBE = (1 << 10), 85 IRQ_NOREQUEST = (1 << 11), 86 IRQ_NOAUTOEN = (1 << 12), 87 IRQ_NO_BALANCING = (1 << 13), 88 IRQ_MOVE_PCNTXT = (1 << 14), 89 IRQ_NESTED_THREAD = (1 << 15), 90 IRQ_NOTHREAD = (1 << 16), 91 }; 92 93 #define IRQF_MODIFY_MASK \ 94 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ 95 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ 96 IRQ_PER_CPU | IRQ_NESTED_THREAD) 97 98 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 99 100 /* 101 * Return value for chip->irq_set_affinity() 102 * 103 * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity 104 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity 105 */ 106 enum { 107 IRQ_SET_MASK_OK = 0, 108 IRQ_SET_MASK_OK_NOCOPY, 109 }; 110 111 struct msi_desc; 112 struct irq_domain; 113 114 /** 115 * struct irq_data - per irq and irq chip data passed down to chip functions 116 * @irq: interrupt number 117 * @hwirq: hardware interrupt number, local to the interrupt domain 118 * @node: node index useful for balancing 119 * @state_use_accessors: status information for irq chip functions. 120 * Use accessor functions to deal with it 121 * @chip: low level interrupt hardware access 122 * @domain: Interrupt translation domain; responsible for mapping 123 * between hwirq number and linux irq number. 124 * @handler_data: per-IRQ data for the irq_chip methods 125 * @chip_data: platform-specific per-chip private data for the chip 126 * methods, to allow shared chip implementations 127 * @msi_desc: MSI descriptor 128 * @affinity: IRQ affinity on SMP 129 * 130 * The fields here need to overlay the ones in irq_desc until we 131 * cleaned up the direct references and switched everything over to 132 * irq_data. 133 */ 134 struct irq_data { 135 unsigned int irq; 136 unsigned long hwirq; 137 unsigned int node; 138 unsigned int state_use_accessors; 139 struct irq_chip *chip; 140 struct irq_domain *domain; 141 void *handler_data; 142 void *chip_data; 143 struct msi_desc *msi_desc; 144 #ifdef CONFIG_SMP 145 cpumask_var_t affinity; 146 #endif 147 }; 148 149 /* 150 * Bit masks for irq_data.state 151 * 152 * IRQD_TRIGGER_MASK - Mask for the trigger type bits 153 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 154 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 155 * IRQD_PER_CPU - Interrupt is per cpu 156 * IRQD_AFFINITY_SET - Interrupt affinity was set 157 * IRQD_LEVEL - Interrupt is level triggered 158 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup 159 * from suspend 160 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process 161 * context 162 * IRQD_IRQ_DISABLED - Disabled state of the interrupt 163 * IRQD_IRQ_MASKED - Masked state of the interrupt 164 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt 165 */ 166 enum { 167 IRQD_TRIGGER_MASK = 0xf, 168 IRQD_SETAFFINITY_PENDING = (1 << 8), 169 IRQD_NO_BALANCING = (1 << 10), 170 IRQD_PER_CPU = (1 << 11), 171 IRQD_AFFINITY_SET = (1 << 12), 172 IRQD_LEVEL = (1 << 13), 173 IRQD_WAKEUP_STATE = (1 << 14), 174 IRQD_MOVE_PCNTXT = (1 << 15), 175 IRQD_IRQ_DISABLED = (1 << 16), 176 IRQD_IRQ_MASKED = (1 << 17), 177 IRQD_IRQ_INPROGRESS = (1 << 18), 178 }; 179 180 static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 181 { 182 return d->state_use_accessors & IRQD_SETAFFINITY_PENDING; 183 } 184 185 static inline bool irqd_is_per_cpu(struct irq_data *d) 186 { 187 return d->state_use_accessors & IRQD_PER_CPU; 188 } 189 190 static inline bool irqd_can_balance(struct irq_data *d) 191 { 192 return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING)); 193 } 194 195 static inline bool irqd_affinity_was_set(struct irq_data *d) 196 { 197 return d->state_use_accessors & IRQD_AFFINITY_SET; 198 } 199 200 static inline void irqd_mark_affinity_was_set(struct irq_data *d) 201 { 202 d->state_use_accessors |= IRQD_AFFINITY_SET; 203 } 204 205 static inline u32 irqd_get_trigger_type(struct irq_data *d) 206 { 207 return d->state_use_accessors & IRQD_TRIGGER_MASK; 208 } 209 210 /* 211 * Must only be called inside irq_chip.irq_set_type() functions. 212 */ 213 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) 214 { 215 d->state_use_accessors &= ~IRQD_TRIGGER_MASK; 216 d->state_use_accessors |= type & IRQD_TRIGGER_MASK; 217 } 218 219 static inline bool irqd_is_level_type(struct irq_data *d) 220 { 221 return d->state_use_accessors & IRQD_LEVEL; 222 } 223 224 static inline bool irqd_is_wakeup_set(struct irq_data *d) 225 { 226 return d->state_use_accessors & IRQD_WAKEUP_STATE; 227 } 228 229 static inline bool irqd_can_move_in_process_context(struct irq_data *d) 230 { 231 return d->state_use_accessors & IRQD_MOVE_PCNTXT; 232 } 233 234 static inline bool irqd_irq_disabled(struct irq_data *d) 235 { 236 return d->state_use_accessors & IRQD_IRQ_DISABLED; 237 } 238 239 static inline bool irqd_irq_masked(struct irq_data *d) 240 { 241 return d->state_use_accessors & IRQD_IRQ_MASKED; 242 } 243 244 static inline bool irqd_irq_inprogress(struct irq_data *d) 245 { 246 return d->state_use_accessors & IRQD_IRQ_INPROGRESS; 247 } 248 249 /* 250 * Functions for chained handlers which can be enabled/disabled by the 251 * standard disable_irq/enable_irq calls. Must be called with 252 * irq_desc->lock held. 253 */ 254 static inline void irqd_set_chained_irq_inprogress(struct irq_data *d) 255 { 256 d->state_use_accessors |= IRQD_IRQ_INPROGRESS; 257 } 258 259 static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d) 260 { 261 d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS; 262 } 263 264 /** 265 * struct irq_chip - hardware interrupt chip descriptor 266 * 267 * @name: name for /proc/interrupts 268 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 269 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 270 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) 271 * @irq_disable: disable the interrupt 272 * @irq_ack: start of a new interrupt 273 * @irq_mask: mask an interrupt source 274 * @irq_mask_ack: ack and mask an interrupt source 275 * @irq_unmask: unmask an interrupt source 276 * @irq_eoi: end of interrupt 277 * @irq_set_affinity: set the CPU affinity on SMP machines 278 * @irq_retrigger: resend an IRQ to the CPU 279 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ 280 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 281 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 282 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 283 * @irq_cpu_online: configure an interrupt source for a secondary CPU 284 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU 285 * @irq_suspend: function called from core code on suspend once per chip 286 * @irq_resume: function called from core code on resume once per chip 287 * @irq_pm_shutdown: function called from core code on shutdown once per chip 288 * @irq_print_chip: optional to print special chip info in show_interrupts 289 * @flags: chip specific flags 290 * 291 * @release: release function solely used by UML 292 */ 293 struct irq_chip { 294 const char *name; 295 unsigned int (*irq_startup)(struct irq_data *data); 296 void (*irq_shutdown)(struct irq_data *data); 297 void (*irq_enable)(struct irq_data *data); 298 void (*irq_disable)(struct irq_data *data); 299 300 void (*irq_ack)(struct irq_data *data); 301 void (*irq_mask)(struct irq_data *data); 302 void (*irq_mask_ack)(struct irq_data *data); 303 void (*irq_unmask)(struct irq_data *data); 304 void (*irq_eoi)(struct irq_data *data); 305 306 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); 307 int (*irq_retrigger)(struct irq_data *data); 308 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); 309 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 310 311 void (*irq_bus_lock)(struct irq_data *data); 312 void (*irq_bus_sync_unlock)(struct irq_data *data); 313 314 void (*irq_cpu_online)(struct irq_data *data); 315 void (*irq_cpu_offline)(struct irq_data *data); 316 317 void (*irq_suspend)(struct irq_data *data); 318 void (*irq_resume)(struct irq_data *data); 319 void (*irq_pm_shutdown)(struct irq_data *data); 320 321 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 322 323 unsigned long flags; 324 325 /* Currently used only by UML, might disappear one day.*/ 326 #ifdef CONFIG_IRQ_RELEASE_METHOD 327 void (*release)(unsigned int irq, void *dev_id); 328 #endif 329 }; 330 331 /* 332 * irq_chip specific flags 333 * 334 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() 335 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled 336 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path 337 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks 338 * when irq enabled 339 */ 340 enum { 341 IRQCHIP_SET_TYPE_MASKED = (1 << 0), 342 IRQCHIP_EOI_IF_HANDLED = (1 << 1), 343 IRQCHIP_MASK_ON_SUSPEND = (1 << 2), 344 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), 345 }; 346 347 /* This include will go away once we isolated irq_desc usage to core code */ 348 #include <linux/irqdesc.h> 349 350 /* 351 * Pick up the arch-dependent methods: 352 */ 353 #include <asm/hw_irq.h> 354 355 #ifndef NR_IRQS_LEGACY 356 # define NR_IRQS_LEGACY 0 357 #endif 358 359 #ifndef ARCH_IRQ_INIT_FLAGS 360 # define ARCH_IRQ_INIT_FLAGS 0 361 #endif 362 363 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS 364 365 struct irqaction; 366 extern int setup_irq(unsigned int irq, struct irqaction *new); 367 extern void remove_irq(unsigned int irq, struct irqaction *act); 368 369 extern void irq_cpu_online(void); 370 extern void irq_cpu_offline(void); 371 extern int __irq_set_affinity_locked(struct irq_data *data, const struct cpumask *cpumask); 372 373 #ifdef CONFIG_GENERIC_HARDIRQS 374 375 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) 376 void irq_move_irq(struct irq_data *data); 377 void irq_move_masked_irq(struct irq_data *data); 378 #else 379 static inline void irq_move_irq(struct irq_data *data) { } 380 static inline void irq_move_masked_irq(struct irq_data *data) { } 381 #endif 382 383 extern int no_irq_affinity; 384 385 /* 386 * Built-in IRQ handlers for various IRQ types, 387 * callable via desc->handle_irq() 388 */ 389 extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); 390 extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); 391 extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); 392 extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc); 393 extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); 394 extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); 395 extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); 396 extern void handle_nested_irq(unsigned int irq); 397 398 /* Handling of unhandled and spurious interrupts: */ 399 extern void note_interrupt(unsigned int irq, struct irq_desc *desc, 400 irqreturn_t action_ret); 401 402 403 /* Enable/disable irq debugging output: */ 404 extern int noirqdebug_setup(char *str); 405 406 /* Checks whether the interrupt can be requested by request_irq(): */ 407 extern int can_request_irq(unsigned int irq, unsigned long irqflags); 408 409 /* Dummy irq-chip implementations: */ 410 extern struct irq_chip no_irq_chip; 411 extern struct irq_chip dummy_irq_chip; 412 413 extern void 414 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, 415 irq_flow_handler_t handle, const char *name); 416 417 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, 418 irq_flow_handler_t handle) 419 { 420 irq_set_chip_and_handler_name(irq, chip, handle, NULL); 421 } 422 423 extern void 424 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, 425 const char *name); 426 427 static inline void 428 irq_set_handler(unsigned int irq, irq_flow_handler_t handle) 429 { 430 __irq_set_handler(irq, handle, 0, NULL); 431 } 432 433 /* 434 * Set a highlevel chained flow handler for a given IRQ. 435 * (a chained handler is automatically enabled and set to 436 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 437 */ 438 static inline void 439 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) 440 { 441 __irq_set_handler(irq, handle, 1, NULL); 442 } 443 444 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); 445 446 static inline void irq_set_status_flags(unsigned int irq, unsigned long set) 447 { 448 irq_modify_status(irq, 0, set); 449 } 450 451 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) 452 { 453 irq_modify_status(irq, clr, 0); 454 } 455 456 static inline void irq_set_noprobe(unsigned int irq) 457 { 458 irq_modify_status(irq, 0, IRQ_NOPROBE); 459 } 460 461 static inline void irq_set_probe(unsigned int irq) 462 { 463 irq_modify_status(irq, IRQ_NOPROBE, 0); 464 } 465 466 static inline void irq_set_nothread(unsigned int irq) 467 { 468 irq_modify_status(irq, 0, IRQ_NOTHREAD); 469 } 470 471 static inline void irq_set_thread(unsigned int irq) 472 { 473 irq_modify_status(irq, IRQ_NOTHREAD, 0); 474 } 475 476 static inline void irq_set_nested_thread(unsigned int irq, bool nest) 477 { 478 if (nest) 479 irq_set_status_flags(irq, IRQ_NESTED_THREAD); 480 else 481 irq_clear_status_flags(irq, IRQ_NESTED_THREAD); 482 } 483 484 /* Handle dynamic irq creation and destruction */ 485 extern unsigned int create_irq_nr(unsigned int irq_want, int node); 486 extern int create_irq(void); 487 extern void destroy_irq(unsigned int irq); 488 489 /* 490 * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and 491 * irq_free_desc instead. 492 */ 493 extern void dynamic_irq_cleanup(unsigned int irq); 494 static inline void dynamic_irq_init(unsigned int irq) 495 { 496 dynamic_irq_cleanup(irq); 497 } 498 499 /* Set/get chip/data for an IRQ: */ 500 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); 501 extern int irq_set_handler_data(unsigned int irq, void *data); 502 extern int irq_set_chip_data(unsigned int irq, void *data); 503 extern int irq_set_irq_type(unsigned int irq, unsigned int type); 504 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 505 extern struct irq_data *irq_get_irq_data(unsigned int irq); 506 507 static inline struct irq_chip *irq_get_chip(unsigned int irq) 508 { 509 struct irq_data *d = irq_get_irq_data(irq); 510 return d ? d->chip : NULL; 511 } 512 513 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) 514 { 515 return d->chip; 516 } 517 518 static inline void *irq_get_chip_data(unsigned int irq) 519 { 520 struct irq_data *d = irq_get_irq_data(irq); 521 return d ? d->chip_data : NULL; 522 } 523 524 static inline void *irq_data_get_irq_chip_data(struct irq_data *d) 525 { 526 return d->chip_data; 527 } 528 529 static inline void *irq_get_handler_data(unsigned int irq) 530 { 531 struct irq_data *d = irq_get_irq_data(irq); 532 return d ? d->handler_data : NULL; 533 } 534 535 static inline void *irq_data_get_irq_handler_data(struct irq_data *d) 536 { 537 return d->handler_data; 538 } 539 540 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) 541 { 542 struct irq_data *d = irq_get_irq_data(irq); 543 return d ? d->msi_desc : NULL; 544 } 545 546 static inline struct msi_desc *irq_data_get_msi(struct irq_data *d) 547 { 548 return d->msi_desc; 549 } 550 551 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, 552 struct module *owner); 553 554 static inline int irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, 555 int node) 556 { 557 return __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE); 558 } 559 560 void irq_free_descs(unsigned int irq, unsigned int cnt); 561 int irq_reserve_irqs(unsigned int from, unsigned int cnt); 562 563 static inline int irq_alloc_desc(int node) 564 { 565 return irq_alloc_descs(-1, 0, 1, node); 566 } 567 568 static inline int irq_alloc_desc_at(unsigned int at, int node) 569 { 570 return irq_alloc_descs(at, at, 1, node); 571 } 572 573 static inline int irq_alloc_desc_from(unsigned int from, int node) 574 { 575 return irq_alloc_descs(-1, from, 1, node); 576 } 577 578 static inline void irq_free_desc(unsigned int irq) 579 { 580 irq_free_descs(irq, 1); 581 } 582 583 static inline int irq_reserve_irq(unsigned int irq) 584 { 585 return irq_reserve_irqs(irq, 1); 586 } 587 588 #ifndef irq_reg_writel 589 # define irq_reg_writel(val, addr) writel(val, addr) 590 #endif 591 #ifndef irq_reg_readl 592 # define irq_reg_readl(addr) readl(addr) 593 #endif 594 595 /** 596 * struct irq_chip_regs - register offsets for struct irq_gci 597 * @enable: Enable register offset to reg_base 598 * @disable: Disable register offset to reg_base 599 * @mask: Mask register offset to reg_base 600 * @ack: Ack register offset to reg_base 601 * @eoi: Eoi register offset to reg_base 602 * @type: Type configuration register offset to reg_base 603 * @polarity: Polarity configuration register offset to reg_base 604 */ 605 struct irq_chip_regs { 606 unsigned long enable; 607 unsigned long disable; 608 unsigned long mask; 609 unsigned long ack; 610 unsigned long eoi; 611 unsigned long type; 612 unsigned long polarity; 613 }; 614 615 /** 616 * struct irq_chip_type - Generic interrupt chip instance for a flow type 617 * @chip: The real interrupt chip which provides the callbacks 618 * @regs: Register offsets for this chip 619 * @handler: Flow handler associated with this chip 620 * @type: Chip can handle these flow types 621 * 622 * A irq_generic_chip can have several instances of irq_chip_type when 623 * it requires different functions and register offsets for different 624 * flow types. 625 */ 626 struct irq_chip_type { 627 struct irq_chip chip; 628 struct irq_chip_regs regs; 629 irq_flow_handler_t handler; 630 u32 type; 631 }; 632 633 /** 634 * struct irq_chip_generic - Generic irq chip data structure 635 * @lock: Lock to protect register and cache data access 636 * @reg_base: Register base address (virtual) 637 * @irq_base: Interrupt base nr for this chip 638 * @irq_cnt: Number of interrupts handled by this chip 639 * @mask_cache: Cached mask register 640 * @type_cache: Cached type register 641 * @polarity_cache: Cached polarity register 642 * @wake_enabled: Interrupt can wakeup from suspend 643 * @wake_active: Interrupt is marked as an wakeup from suspend source 644 * @num_ct: Number of available irq_chip_type instances (usually 1) 645 * @private: Private data for non generic chip callbacks 646 * @list: List head for keeping track of instances 647 * @chip_types: Array of interrupt irq_chip_types 648 * 649 * Note, that irq_chip_generic can have multiple irq_chip_type 650 * implementations which can be associated to a particular irq line of 651 * an irq_chip_generic instance. That allows to share and protect 652 * state in an irq_chip_generic instance when we need to implement 653 * different flow mechanisms (level/edge) for it. 654 */ 655 struct irq_chip_generic { 656 raw_spinlock_t lock; 657 void __iomem *reg_base; 658 unsigned int irq_base; 659 unsigned int irq_cnt; 660 u32 mask_cache; 661 u32 type_cache; 662 u32 polarity_cache; 663 u32 wake_enabled; 664 u32 wake_active; 665 unsigned int num_ct; 666 void *private; 667 struct list_head list; 668 struct irq_chip_type chip_types[0]; 669 }; 670 671 /** 672 * enum irq_gc_flags - Initialization flags for generic irq chips 673 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg 674 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for 675 * irq chips which need to call irq_set_wake() on 676 * the parent irq. Usually GPIO implementations 677 */ 678 enum irq_gc_flags { 679 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 680 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 681 }; 682 683 /* Generic chip callback functions */ 684 void irq_gc_noop(struct irq_data *d); 685 void irq_gc_mask_disable_reg(struct irq_data *d); 686 void irq_gc_mask_set_bit(struct irq_data *d); 687 void irq_gc_mask_clr_bit(struct irq_data *d); 688 void irq_gc_unmask_enable_reg(struct irq_data *d); 689 void irq_gc_ack_set_bit(struct irq_data *d); 690 void irq_gc_ack_clr_bit(struct irq_data *d); 691 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); 692 void irq_gc_eoi(struct irq_data *d); 693 int irq_gc_set_wake(struct irq_data *d, unsigned int on); 694 695 /* Setup functions for irq_chip_generic */ 696 struct irq_chip_generic * 697 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, 698 void __iomem *reg_base, irq_flow_handler_t handler); 699 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 700 enum irq_gc_flags flags, unsigned int clr, 701 unsigned int set); 702 int irq_setup_alt_chip(struct irq_data *d, unsigned int type); 703 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 704 unsigned int clr, unsigned int set); 705 706 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) 707 { 708 return container_of(d->chip, struct irq_chip_type, chip); 709 } 710 711 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) 712 713 #ifdef CONFIG_SMP 714 static inline void irq_gc_lock(struct irq_chip_generic *gc) 715 { 716 raw_spin_lock(&gc->lock); 717 } 718 719 static inline void irq_gc_unlock(struct irq_chip_generic *gc) 720 { 721 raw_spin_unlock(&gc->lock); 722 } 723 #else 724 static inline void irq_gc_lock(struct irq_chip_generic *gc) { } 725 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } 726 #endif 727 728 #endif /* CONFIG_GENERIC_HARDIRQS */ 729 730 #endif /* !CONFIG_S390 */ 731 732 #endif /* _LINUX_IRQ_H */ 733