1 #ifndef _LINUX_IRQ_H 2 #define _LINUX_IRQ_H 3 4 /* 5 * Please do not include this file in generic code. There is currently 6 * no requirement for any architecture to implement anything held 7 * within this file. 8 * 9 * Thanks. --rmk 10 */ 11 12 #include <linux/smp.h> 13 #include <linux/linkage.h> 14 #include <linux/cache.h> 15 #include <linux/spinlock.h> 16 #include <linux/cpumask.h> 17 #include <linux/gfp.h> 18 #include <linux/irqreturn.h> 19 #include <linux/irqnr.h> 20 #include <linux/errno.h> 21 #include <linux/topology.h> 22 #include <linux/wait.h> 23 24 #include <asm/irq.h> 25 #include <asm/ptrace.h> 26 #include <asm/irq_regs.h> 27 28 struct seq_file; 29 struct module; 30 struct irq_desc; 31 struct irq_data; 32 typedef void (*irq_flow_handler_t)(unsigned int irq, 33 struct irq_desc *desc); 34 typedef void (*irq_preflow_handler_t)(struct irq_data *data); 35 36 /* 37 * IRQ line status. 38 * 39 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h 40 * 41 * IRQ_TYPE_NONE - default, unspecified type 42 * IRQ_TYPE_EDGE_RISING - rising edge triggered 43 * IRQ_TYPE_EDGE_FALLING - falling edge triggered 44 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 45 * IRQ_TYPE_LEVEL_HIGH - high level triggered 46 * IRQ_TYPE_LEVEL_LOW - low level triggered 47 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 48 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits 49 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type 50 * to setup the HW to a sane default (used 51 * by irqdomain map() callbacks to synchronize 52 * the HW state and SW flags for a newly 53 * allocated descriptor). 54 * 55 * IRQ_TYPE_PROBE - Special flag for probing in progress 56 * 57 * Bits which can be modified via irq_set/clear/modify_status_flags() 58 * IRQ_LEVEL - Interrupt is level type. Will be also 59 * updated in the code when the above trigger 60 * bits are modified via irq_set_irq_type() 61 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect 62 * it from affinity setting 63 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing 64 * IRQ_NOREQUEST - Interrupt cannot be requested via 65 * request_irq() 66 * IRQ_NOTHREAD - Interrupt cannot be threaded 67 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in 68 * request/setup_irq() 69 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) 70 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context 71 * IRQ_NESTED_TRHEAD - Interrupt nests into another thread 72 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable 73 */ 74 enum { 75 IRQ_TYPE_NONE = 0x00000000, 76 IRQ_TYPE_EDGE_RISING = 0x00000001, 77 IRQ_TYPE_EDGE_FALLING = 0x00000002, 78 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), 79 IRQ_TYPE_LEVEL_HIGH = 0x00000004, 80 IRQ_TYPE_LEVEL_LOW = 0x00000008, 81 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), 82 IRQ_TYPE_SENSE_MASK = 0x0000000f, 83 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, 84 85 IRQ_TYPE_PROBE = 0x00000010, 86 87 IRQ_LEVEL = (1 << 8), 88 IRQ_PER_CPU = (1 << 9), 89 IRQ_NOPROBE = (1 << 10), 90 IRQ_NOREQUEST = (1 << 11), 91 IRQ_NOAUTOEN = (1 << 12), 92 IRQ_NO_BALANCING = (1 << 13), 93 IRQ_MOVE_PCNTXT = (1 << 14), 94 IRQ_NESTED_THREAD = (1 << 15), 95 IRQ_NOTHREAD = (1 << 16), 96 IRQ_PER_CPU_DEVID = (1 << 17), 97 }; 98 99 #define IRQF_MODIFY_MASK \ 100 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ 101 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ 102 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID) 103 104 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 105 106 /* 107 * Return value for chip->irq_set_affinity() 108 * 109 * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity 110 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity 111 */ 112 enum { 113 IRQ_SET_MASK_OK = 0, 114 IRQ_SET_MASK_OK_NOCOPY, 115 }; 116 117 struct msi_desc; 118 struct irq_domain; 119 120 /** 121 * struct irq_data - per irq and irq chip data passed down to chip functions 122 * @irq: interrupt number 123 * @hwirq: hardware interrupt number, local to the interrupt domain 124 * @node: node index useful for balancing 125 * @state_use_accessors: status information for irq chip functions. 126 * Use accessor functions to deal with it 127 * @chip: low level interrupt hardware access 128 * @domain: Interrupt translation domain; responsible for mapping 129 * between hwirq number and linux irq number. 130 * @handler_data: per-IRQ data for the irq_chip methods 131 * @chip_data: platform-specific per-chip private data for the chip 132 * methods, to allow shared chip implementations 133 * @msi_desc: MSI descriptor 134 * @affinity: IRQ affinity on SMP 135 * 136 * The fields here need to overlay the ones in irq_desc until we 137 * cleaned up the direct references and switched everything over to 138 * irq_data. 139 */ 140 struct irq_data { 141 unsigned int irq; 142 unsigned long hwirq; 143 unsigned int node; 144 unsigned int state_use_accessors; 145 struct irq_chip *chip; 146 struct irq_domain *domain; 147 void *handler_data; 148 void *chip_data; 149 struct msi_desc *msi_desc; 150 cpumask_var_t affinity; 151 }; 152 153 /* 154 * Bit masks for irq_data.state 155 * 156 * IRQD_TRIGGER_MASK - Mask for the trigger type bits 157 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 158 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 159 * IRQD_PER_CPU - Interrupt is per cpu 160 * IRQD_AFFINITY_SET - Interrupt affinity was set 161 * IRQD_LEVEL - Interrupt is level triggered 162 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup 163 * from suspend 164 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process 165 * context 166 * IRQD_IRQ_DISABLED - Disabled state of the interrupt 167 * IRQD_IRQ_MASKED - Masked state of the interrupt 168 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt 169 */ 170 enum { 171 IRQD_TRIGGER_MASK = 0xf, 172 IRQD_SETAFFINITY_PENDING = (1 << 8), 173 IRQD_NO_BALANCING = (1 << 10), 174 IRQD_PER_CPU = (1 << 11), 175 IRQD_AFFINITY_SET = (1 << 12), 176 IRQD_LEVEL = (1 << 13), 177 IRQD_WAKEUP_STATE = (1 << 14), 178 IRQD_MOVE_PCNTXT = (1 << 15), 179 IRQD_IRQ_DISABLED = (1 << 16), 180 IRQD_IRQ_MASKED = (1 << 17), 181 IRQD_IRQ_INPROGRESS = (1 << 18), 182 }; 183 184 static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 185 { 186 return d->state_use_accessors & IRQD_SETAFFINITY_PENDING; 187 } 188 189 static inline bool irqd_is_per_cpu(struct irq_data *d) 190 { 191 return d->state_use_accessors & IRQD_PER_CPU; 192 } 193 194 static inline bool irqd_can_balance(struct irq_data *d) 195 { 196 return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING)); 197 } 198 199 static inline bool irqd_affinity_was_set(struct irq_data *d) 200 { 201 return d->state_use_accessors & IRQD_AFFINITY_SET; 202 } 203 204 static inline void irqd_mark_affinity_was_set(struct irq_data *d) 205 { 206 d->state_use_accessors |= IRQD_AFFINITY_SET; 207 } 208 209 static inline u32 irqd_get_trigger_type(struct irq_data *d) 210 { 211 return d->state_use_accessors & IRQD_TRIGGER_MASK; 212 } 213 214 /* 215 * Must only be called inside irq_chip.irq_set_type() functions. 216 */ 217 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) 218 { 219 d->state_use_accessors &= ~IRQD_TRIGGER_MASK; 220 d->state_use_accessors |= type & IRQD_TRIGGER_MASK; 221 } 222 223 static inline bool irqd_is_level_type(struct irq_data *d) 224 { 225 return d->state_use_accessors & IRQD_LEVEL; 226 } 227 228 static inline bool irqd_is_wakeup_set(struct irq_data *d) 229 { 230 return d->state_use_accessors & IRQD_WAKEUP_STATE; 231 } 232 233 static inline bool irqd_can_move_in_process_context(struct irq_data *d) 234 { 235 return d->state_use_accessors & IRQD_MOVE_PCNTXT; 236 } 237 238 static inline bool irqd_irq_disabled(struct irq_data *d) 239 { 240 return d->state_use_accessors & IRQD_IRQ_DISABLED; 241 } 242 243 static inline bool irqd_irq_masked(struct irq_data *d) 244 { 245 return d->state_use_accessors & IRQD_IRQ_MASKED; 246 } 247 248 static inline bool irqd_irq_inprogress(struct irq_data *d) 249 { 250 return d->state_use_accessors & IRQD_IRQ_INPROGRESS; 251 } 252 253 /* 254 * Functions for chained handlers which can be enabled/disabled by the 255 * standard disable_irq/enable_irq calls. Must be called with 256 * irq_desc->lock held. 257 */ 258 static inline void irqd_set_chained_irq_inprogress(struct irq_data *d) 259 { 260 d->state_use_accessors |= IRQD_IRQ_INPROGRESS; 261 } 262 263 static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d) 264 { 265 d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS; 266 } 267 268 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) 269 { 270 return d->hwirq; 271 } 272 273 /** 274 * struct irq_chip - hardware interrupt chip descriptor 275 * 276 * @name: name for /proc/interrupts 277 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 278 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 279 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) 280 * @irq_disable: disable the interrupt 281 * @irq_ack: start of a new interrupt 282 * @irq_mask: mask an interrupt source 283 * @irq_mask_ack: ack and mask an interrupt source 284 * @irq_unmask: unmask an interrupt source 285 * @irq_eoi: end of interrupt 286 * @irq_set_affinity: set the CPU affinity on SMP machines 287 * @irq_retrigger: resend an IRQ to the CPU 288 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ 289 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 290 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 291 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 292 * @irq_cpu_online: configure an interrupt source for a secondary CPU 293 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU 294 * @irq_suspend: function called from core code on suspend once per chip 295 * @irq_resume: function called from core code on resume once per chip 296 * @irq_pm_shutdown: function called from core code on shutdown once per chip 297 * @irq_print_chip: optional to print special chip info in show_interrupts 298 * @flags: chip specific flags 299 */ 300 struct irq_chip { 301 const char *name; 302 unsigned int (*irq_startup)(struct irq_data *data); 303 void (*irq_shutdown)(struct irq_data *data); 304 void (*irq_enable)(struct irq_data *data); 305 void (*irq_disable)(struct irq_data *data); 306 307 void (*irq_ack)(struct irq_data *data); 308 void (*irq_mask)(struct irq_data *data); 309 void (*irq_mask_ack)(struct irq_data *data); 310 void (*irq_unmask)(struct irq_data *data); 311 void (*irq_eoi)(struct irq_data *data); 312 313 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); 314 int (*irq_retrigger)(struct irq_data *data); 315 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); 316 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 317 318 void (*irq_bus_lock)(struct irq_data *data); 319 void (*irq_bus_sync_unlock)(struct irq_data *data); 320 321 void (*irq_cpu_online)(struct irq_data *data); 322 void (*irq_cpu_offline)(struct irq_data *data); 323 324 void (*irq_suspend)(struct irq_data *data); 325 void (*irq_resume)(struct irq_data *data); 326 void (*irq_pm_shutdown)(struct irq_data *data); 327 328 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 329 330 unsigned long flags; 331 }; 332 333 /* 334 * irq_chip specific flags 335 * 336 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() 337 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled 338 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path 339 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks 340 * when irq enabled 341 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip 342 */ 343 enum { 344 IRQCHIP_SET_TYPE_MASKED = (1 << 0), 345 IRQCHIP_EOI_IF_HANDLED = (1 << 1), 346 IRQCHIP_MASK_ON_SUSPEND = (1 << 2), 347 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), 348 IRQCHIP_SKIP_SET_WAKE = (1 << 4), 349 IRQCHIP_ONESHOT_SAFE = (1 << 5), 350 }; 351 352 /* This include will go away once we isolated irq_desc usage to core code */ 353 #include <linux/irqdesc.h> 354 355 /* 356 * Pick up the arch-dependent methods: 357 */ 358 #include <asm/hw_irq.h> 359 360 #ifndef NR_IRQS_LEGACY 361 # define NR_IRQS_LEGACY 0 362 #endif 363 364 #ifndef ARCH_IRQ_INIT_FLAGS 365 # define ARCH_IRQ_INIT_FLAGS 0 366 #endif 367 368 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS 369 370 struct irqaction; 371 extern int setup_irq(unsigned int irq, struct irqaction *new); 372 extern void remove_irq(unsigned int irq, struct irqaction *act); 373 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); 374 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); 375 376 extern void irq_cpu_online(void); 377 extern void irq_cpu_offline(void); 378 extern int __irq_set_affinity_locked(struct irq_data *data, const struct cpumask *cpumask); 379 380 #ifdef CONFIG_GENERIC_HARDIRQS 381 382 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) 383 void irq_move_irq(struct irq_data *data); 384 void irq_move_masked_irq(struct irq_data *data); 385 #else 386 static inline void irq_move_irq(struct irq_data *data) { } 387 static inline void irq_move_masked_irq(struct irq_data *data) { } 388 #endif 389 390 extern int no_irq_affinity; 391 392 #ifdef CONFIG_HARDIRQS_SW_RESEND 393 int irq_set_parent(int irq, int parent_irq); 394 #else 395 static inline int irq_set_parent(int irq, int parent_irq) 396 { 397 return 0; 398 } 399 #endif 400 401 /* 402 * Built-in IRQ handlers for various IRQ types, 403 * callable via desc->handle_irq() 404 */ 405 extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); 406 extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); 407 extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); 408 extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc); 409 extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); 410 extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); 411 extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc); 412 extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); 413 extern void handle_nested_irq(unsigned int irq); 414 415 /* Handling of unhandled and spurious interrupts: */ 416 extern void note_interrupt(unsigned int irq, struct irq_desc *desc, 417 irqreturn_t action_ret); 418 419 420 /* Enable/disable irq debugging output: */ 421 extern int noirqdebug_setup(char *str); 422 423 /* Checks whether the interrupt can be requested by request_irq(): */ 424 extern int can_request_irq(unsigned int irq, unsigned long irqflags); 425 426 /* Dummy irq-chip implementations: */ 427 extern struct irq_chip no_irq_chip; 428 extern struct irq_chip dummy_irq_chip; 429 430 extern void 431 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, 432 irq_flow_handler_t handle, const char *name); 433 434 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, 435 irq_flow_handler_t handle) 436 { 437 irq_set_chip_and_handler_name(irq, chip, handle, NULL); 438 } 439 440 extern int irq_set_percpu_devid(unsigned int irq); 441 442 extern void 443 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, 444 const char *name); 445 446 static inline void 447 irq_set_handler(unsigned int irq, irq_flow_handler_t handle) 448 { 449 __irq_set_handler(irq, handle, 0, NULL); 450 } 451 452 /* 453 * Set a highlevel chained flow handler for a given IRQ. 454 * (a chained handler is automatically enabled and set to 455 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 456 */ 457 static inline void 458 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) 459 { 460 __irq_set_handler(irq, handle, 1, NULL); 461 } 462 463 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); 464 465 static inline void irq_set_status_flags(unsigned int irq, unsigned long set) 466 { 467 irq_modify_status(irq, 0, set); 468 } 469 470 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) 471 { 472 irq_modify_status(irq, clr, 0); 473 } 474 475 static inline void irq_set_noprobe(unsigned int irq) 476 { 477 irq_modify_status(irq, 0, IRQ_NOPROBE); 478 } 479 480 static inline void irq_set_probe(unsigned int irq) 481 { 482 irq_modify_status(irq, IRQ_NOPROBE, 0); 483 } 484 485 static inline void irq_set_nothread(unsigned int irq) 486 { 487 irq_modify_status(irq, 0, IRQ_NOTHREAD); 488 } 489 490 static inline void irq_set_thread(unsigned int irq) 491 { 492 irq_modify_status(irq, IRQ_NOTHREAD, 0); 493 } 494 495 static inline void irq_set_nested_thread(unsigned int irq, bool nest) 496 { 497 if (nest) 498 irq_set_status_flags(irq, IRQ_NESTED_THREAD); 499 else 500 irq_clear_status_flags(irq, IRQ_NESTED_THREAD); 501 } 502 503 static inline void irq_set_percpu_devid_flags(unsigned int irq) 504 { 505 irq_set_status_flags(irq, 506 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | 507 IRQ_NOPROBE | IRQ_PER_CPU_DEVID); 508 } 509 510 /* Handle dynamic irq creation and destruction */ 511 extern unsigned int create_irq_nr(unsigned int irq_want, int node); 512 extern int create_irq(void); 513 extern void destroy_irq(unsigned int irq); 514 515 /* 516 * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and 517 * irq_free_desc instead. 518 */ 519 extern void dynamic_irq_cleanup(unsigned int irq); 520 static inline void dynamic_irq_init(unsigned int irq) 521 { 522 dynamic_irq_cleanup(irq); 523 } 524 525 /* Set/get chip/data for an IRQ: */ 526 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); 527 extern int irq_set_handler_data(unsigned int irq, void *data); 528 extern int irq_set_chip_data(unsigned int irq, void *data); 529 extern int irq_set_irq_type(unsigned int irq, unsigned int type); 530 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 531 extern struct irq_data *irq_get_irq_data(unsigned int irq); 532 533 static inline struct irq_chip *irq_get_chip(unsigned int irq) 534 { 535 struct irq_data *d = irq_get_irq_data(irq); 536 return d ? d->chip : NULL; 537 } 538 539 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) 540 { 541 return d->chip; 542 } 543 544 static inline void *irq_get_chip_data(unsigned int irq) 545 { 546 struct irq_data *d = irq_get_irq_data(irq); 547 return d ? d->chip_data : NULL; 548 } 549 550 static inline void *irq_data_get_irq_chip_data(struct irq_data *d) 551 { 552 return d->chip_data; 553 } 554 555 static inline void *irq_get_handler_data(unsigned int irq) 556 { 557 struct irq_data *d = irq_get_irq_data(irq); 558 return d ? d->handler_data : NULL; 559 } 560 561 static inline void *irq_data_get_irq_handler_data(struct irq_data *d) 562 { 563 return d->handler_data; 564 } 565 566 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) 567 { 568 struct irq_data *d = irq_get_irq_data(irq); 569 return d ? d->msi_desc : NULL; 570 } 571 572 static inline struct msi_desc *irq_data_get_msi(struct irq_data *d) 573 { 574 return d->msi_desc; 575 } 576 577 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, 578 struct module *owner); 579 580 /* use macros to avoid needing export.h for THIS_MODULE */ 581 #define irq_alloc_descs(irq, from, cnt, node) \ 582 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE) 583 584 #define irq_alloc_desc(node) \ 585 irq_alloc_descs(-1, 0, 1, node) 586 587 #define irq_alloc_desc_at(at, node) \ 588 irq_alloc_descs(at, at, 1, node) 589 590 #define irq_alloc_desc_from(from, node) \ 591 irq_alloc_descs(-1, from, 1, node) 592 593 void irq_free_descs(unsigned int irq, unsigned int cnt); 594 int irq_reserve_irqs(unsigned int from, unsigned int cnt); 595 596 static inline void irq_free_desc(unsigned int irq) 597 { 598 irq_free_descs(irq, 1); 599 } 600 601 static inline int irq_reserve_irq(unsigned int irq) 602 { 603 return irq_reserve_irqs(irq, 1); 604 } 605 606 #ifndef irq_reg_writel 607 # define irq_reg_writel(val, addr) writel(val, addr) 608 #endif 609 #ifndef irq_reg_readl 610 # define irq_reg_readl(addr) readl(addr) 611 #endif 612 613 /** 614 * struct irq_chip_regs - register offsets for struct irq_gci 615 * @enable: Enable register offset to reg_base 616 * @disable: Disable register offset to reg_base 617 * @mask: Mask register offset to reg_base 618 * @ack: Ack register offset to reg_base 619 * @eoi: Eoi register offset to reg_base 620 * @type: Type configuration register offset to reg_base 621 * @polarity: Polarity configuration register offset to reg_base 622 */ 623 struct irq_chip_regs { 624 unsigned long enable; 625 unsigned long disable; 626 unsigned long mask; 627 unsigned long ack; 628 unsigned long eoi; 629 unsigned long type; 630 unsigned long polarity; 631 }; 632 633 /** 634 * struct irq_chip_type - Generic interrupt chip instance for a flow type 635 * @chip: The real interrupt chip which provides the callbacks 636 * @regs: Register offsets for this chip 637 * @handler: Flow handler associated with this chip 638 * @type: Chip can handle these flow types 639 * 640 * A irq_generic_chip can have several instances of irq_chip_type when 641 * it requires different functions and register offsets for different 642 * flow types. 643 */ 644 struct irq_chip_type { 645 struct irq_chip chip; 646 struct irq_chip_regs regs; 647 irq_flow_handler_t handler; 648 u32 type; 649 }; 650 651 /** 652 * struct irq_chip_generic - Generic irq chip data structure 653 * @lock: Lock to protect register and cache data access 654 * @reg_base: Register base address (virtual) 655 * @irq_base: Interrupt base nr for this chip 656 * @irq_cnt: Number of interrupts handled by this chip 657 * @mask_cache: Cached mask register 658 * @type_cache: Cached type register 659 * @polarity_cache: Cached polarity register 660 * @wake_enabled: Interrupt can wakeup from suspend 661 * @wake_active: Interrupt is marked as an wakeup from suspend source 662 * @num_ct: Number of available irq_chip_type instances (usually 1) 663 * @private: Private data for non generic chip callbacks 664 * @list: List head for keeping track of instances 665 * @chip_types: Array of interrupt irq_chip_types 666 * 667 * Note, that irq_chip_generic can have multiple irq_chip_type 668 * implementations which can be associated to a particular irq line of 669 * an irq_chip_generic instance. That allows to share and protect 670 * state in an irq_chip_generic instance when we need to implement 671 * different flow mechanisms (level/edge) for it. 672 */ 673 struct irq_chip_generic { 674 raw_spinlock_t lock; 675 void __iomem *reg_base; 676 unsigned int irq_base; 677 unsigned int irq_cnt; 678 u32 mask_cache; 679 u32 type_cache; 680 u32 polarity_cache; 681 u32 wake_enabled; 682 u32 wake_active; 683 unsigned int num_ct; 684 void *private; 685 struct list_head list; 686 struct irq_chip_type chip_types[0]; 687 }; 688 689 /** 690 * enum irq_gc_flags - Initialization flags for generic irq chips 691 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg 692 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for 693 * irq chips which need to call irq_set_wake() on 694 * the parent irq. Usually GPIO implementations 695 */ 696 enum irq_gc_flags { 697 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 698 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 699 }; 700 701 /* Generic chip callback functions */ 702 void irq_gc_noop(struct irq_data *d); 703 void irq_gc_mask_disable_reg(struct irq_data *d); 704 void irq_gc_mask_set_bit(struct irq_data *d); 705 void irq_gc_mask_clr_bit(struct irq_data *d); 706 void irq_gc_unmask_enable_reg(struct irq_data *d); 707 void irq_gc_ack_set_bit(struct irq_data *d); 708 void irq_gc_ack_clr_bit(struct irq_data *d); 709 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); 710 void irq_gc_eoi(struct irq_data *d); 711 int irq_gc_set_wake(struct irq_data *d, unsigned int on); 712 713 /* Setup functions for irq_chip_generic */ 714 struct irq_chip_generic * 715 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, 716 void __iomem *reg_base, irq_flow_handler_t handler); 717 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 718 enum irq_gc_flags flags, unsigned int clr, 719 unsigned int set); 720 int irq_setup_alt_chip(struct irq_data *d, unsigned int type); 721 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 722 unsigned int clr, unsigned int set); 723 724 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) 725 { 726 return container_of(d->chip, struct irq_chip_type, chip); 727 } 728 729 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) 730 731 #ifdef CONFIG_SMP 732 static inline void irq_gc_lock(struct irq_chip_generic *gc) 733 { 734 raw_spin_lock(&gc->lock); 735 } 736 737 static inline void irq_gc_unlock(struct irq_chip_generic *gc) 738 { 739 raw_spin_unlock(&gc->lock); 740 } 741 #else 742 static inline void irq_gc_lock(struct irq_chip_generic *gc) { } 743 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } 744 #endif 745 746 #else /* !CONFIG_GENERIC_HARDIRQS */ 747 748 extern struct msi_desc *irq_get_msi_desc(unsigned int irq); 749 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 750 751 #endif /* CONFIG_GENERIC_HARDIRQS */ 752 753 #endif /* _LINUX_IRQ_H */ 754