1 #ifndef _LINUX_IRQ_H 2 #define _LINUX_IRQ_H 3 4 /* 5 * Please do not include this file in generic code. There is currently 6 * no requirement for any architecture to implement anything held 7 * within this file. 8 * 9 * Thanks. --rmk 10 */ 11 12 #include <linux/smp.h> 13 14 #ifndef CONFIG_S390 15 16 #include <linux/linkage.h> 17 #include <linux/cache.h> 18 #include <linux/spinlock.h> 19 #include <linux/cpumask.h> 20 #include <linux/gfp.h> 21 #include <linux/irqreturn.h> 22 #include <linux/irqnr.h> 23 #include <linux/errno.h> 24 #include <linux/topology.h> 25 #include <linux/wait.h> 26 27 #include <asm/irq.h> 28 #include <asm/ptrace.h> 29 #include <asm/irq_regs.h> 30 31 struct seq_file; 32 struct module; 33 struct irq_desc; 34 struct irq_data; 35 typedef void (*irq_flow_handler_t)(unsigned int irq, 36 struct irq_desc *desc); 37 typedef void (*irq_preflow_handler_t)(struct irq_data *data); 38 39 /* 40 * IRQ line status. 41 * 42 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h 43 * 44 * IRQ_TYPE_NONE - default, unspecified type 45 * IRQ_TYPE_EDGE_RISING - rising edge triggered 46 * IRQ_TYPE_EDGE_FALLING - falling edge triggered 47 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 48 * IRQ_TYPE_LEVEL_HIGH - high level triggered 49 * IRQ_TYPE_LEVEL_LOW - low level triggered 50 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 51 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits 52 * IRQ_TYPE_PROBE - Special flag for probing in progress 53 * 54 * Bits which can be modified via irq_set/clear/modify_status_flags() 55 * IRQ_LEVEL - Interrupt is level type. Will be also 56 * updated in the code when the above trigger 57 * bits are modified via irq_set_irq_type() 58 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect 59 * it from affinity setting 60 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing 61 * IRQ_NOREQUEST - Interrupt cannot be requested via 62 * request_irq() 63 * IRQ_NOTHREAD - Interrupt cannot be threaded 64 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in 65 * request/setup_irq() 66 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) 67 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context 68 * IRQ_NESTED_TRHEAD - Interrupt nests into another thread 69 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable 70 */ 71 enum { 72 IRQ_TYPE_NONE = 0x00000000, 73 IRQ_TYPE_EDGE_RISING = 0x00000001, 74 IRQ_TYPE_EDGE_FALLING = 0x00000002, 75 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), 76 IRQ_TYPE_LEVEL_HIGH = 0x00000004, 77 IRQ_TYPE_LEVEL_LOW = 0x00000008, 78 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), 79 IRQ_TYPE_SENSE_MASK = 0x0000000f, 80 81 IRQ_TYPE_PROBE = 0x00000010, 82 83 IRQ_LEVEL = (1 << 8), 84 IRQ_PER_CPU = (1 << 9), 85 IRQ_NOPROBE = (1 << 10), 86 IRQ_NOREQUEST = (1 << 11), 87 IRQ_NOAUTOEN = (1 << 12), 88 IRQ_NO_BALANCING = (1 << 13), 89 IRQ_MOVE_PCNTXT = (1 << 14), 90 IRQ_NESTED_THREAD = (1 << 15), 91 IRQ_NOTHREAD = (1 << 16), 92 IRQ_PER_CPU_DEVID = (1 << 17), 93 }; 94 95 #define IRQF_MODIFY_MASK \ 96 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ 97 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ 98 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID) 99 100 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 101 102 /* 103 * Return value for chip->irq_set_affinity() 104 * 105 * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity 106 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity 107 */ 108 enum { 109 IRQ_SET_MASK_OK = 0, 110 IRQ_SET_MASK_OK_NOCOPY, 111 }; 112 113 struct msi_desc; 114 struct irq_domain; 115 116 /** 117 * struct irq_data - per irq and irq chip data passed down to chip functions 118 * @irq: interrupt number 119 * @hwirq: hardware interrupt number, local to the interrupt domain 120 * @node: node index useful for balancing 121 * @state_use_accessors: status information for irq chip functions. 122 * Use accessor functions to deal with it 123 * @chip: low level interrupt hardware access 124 * @domain: Interrupt translation domain; responsible for mapping 125 * between hwirq number and linux irq number. 126 * @handler_data: per-IRQ data for the irq_chip methods 127 * @chip_data: platform-specific per-chip private data for the chip 128 * methods, to allow shared chip implementations 129 * @msi_desc: MSI descriptor 130 * @affinity: IRQ affinity on SMP 131 * 132 * The fields here need to overlay the ones in irq_desc until we 133 * cleaned up the direct references and switched everything over to 134 * irq_data. 135 */ 136 struct irq_data { 137 unsigned int irq; 138 unsigned long hwirq; 139 unsigned int node; 140 unsigned int state_use_accessors; 141 struct irq_chip *chip; 142 struct irq_domain *domain; 143 void *handler_data; 144 void *chip_data; 145 struct msi_desc *msi_desc; 146 #ifdef CONFIG_SMP 147 cpumask_var_t affinity; 148 #endif 149 }; 150 151 /* 152 * Bit masks for irq_data.state 153 * 154 * IRQD_TRIGGER_MASK - Mask for the trigger type bits 155 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 156 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 157 * IRQD_PER_CPU - Interrupt is per cpu 158 * IRQD_AFFINITY_SET - Interrupt affinity was set 159 * IRQD_LEVEL - Interrupt is level triggered 160 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup 161 * from suspend 162 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process 163 * context 164 * IRQD_IRQ_DISABLED - Disabled state of the interrupt 165 * IRQD_IRQ_MASKED - Masked state of the interrupt 166 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt 167 */ 168 enum { 169 IRQD_TRIGGER_MASK = 0xf, 170 IRQD_SETAFFINITY_PENDING = (1 << 8), 171 IRQD_NO_BALANCING = (1 << 10), 172 IRQD_PER_CPU = (1 << 11), 173 IRQD_AFFINITY_SET = (1 << 12), 174 IRQD_LEVEL = (1 << 13), 175 IRQD_WAKEUP_STATE = (1 << 14), 176 IRQD_MOVE_PCNTXT = (1 << 15), 177 IRQD_IRQ_DISABLED = (1 << 16), 178 IRQD_IRQ_MASKED = (1 << 17), 179 IRQD_IRQ_INPROGRESS = (1 << 18), 180 }; 181 182 static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 183 { 184 return d->state_use_accessors & IRQD_SETAFFINITY_PENDING; 185 } 186 187 static inline bool irqd_is_per_cpu(struct irq_data *d) 188 { 189 return d->state_use_accessors & IRQD_PER_CPU; 190 } 191 192 static inline bool irqd_can_balance(struct irq_data *d) 193 { 194 return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING)); 195 } 196 197 static inline bool irqd_affinity_was_set(struct irq_data *d) 198 { 199 return d->state_use_accessors & IRQD_AFFINITY_SET; 200 } 201 202 static inline void irqd_mark_affinity_was_set(struct irq_data *d) 203 { 204 d->state_use_accessors |= IRQD_AFFINITY_SET; 205 } 206 207 static inline u32 irqd_get_trigger_type(struct irq_data *d) 208 { 209 return d->state_use_accessors & IRQD_TRIGGER_MASK; 210 } 211 212 /* 213 * Must only be called inside irq_chip.irq_set_type() functions. 214 */ 215 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) 216 { 217 d->state_use_accessors &= ~IRQD_TRIGGER_MASK; 218 d->state_use_accessors |= type & IRQD_TRIGGER_MASK; 219 } 220 221 static inline bool irqd_is_level_type(struct irq_data *d) 222 { 223 return d->state_use_accessors & IRQD_LEVEL; 224 } 225 226 static inline bool irqd_is_wakeup_set(struct irq_data *d) 227 { 228 return d->state_use_accessors & IRQD_WAKEUP_STATE; 229 } 230 231 static inline bool irqd_can_move_in_process_context(struct irq_data *d) 232 { 233 return d->state_use_accessors & IRQD_MOVE_PCNTXT; 234 } 235 236 static inline bool irqd_irq_disabled(struct irq_data *d) 237 { 238 return d->state_use_accessors & IRQD_IRQ_DISABLED; 239 } 240 241 static inline bool irqd_irq_masked(struct irq_data *d) 242 { 243 return d->state_use_accessors & IRQD_IRQ_MASKED; 244 } 245 246 static inline bool irqd_irq_inprogress(struct irq_data *d) 247 { 248 return d->state_use_accessors & IRQD_IRQ_INPROGRESS; 249 } 250 251 /* 252 * Functions for chained handlers which can be enabled/disabled by the 253 * standard disable_irq/enable_irq calls. Must be called with 254 * irq_desc->lock held. 255 */ 256 static inline void irqd_set_chained_irq_inprogress(struct irq_data *d) 257 { 258 d->state_use_accessors |= IRQD_IRQ_INPROGRESS; 259 } 260 261 static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d) 262 { 263 d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS; 264 } 265 266 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) 267 { 268 return d->hwirq; 269 } 270 271 /** 272 * struct irq_chip - hardware interrupt chip descriptor 273 * 274 * @name: name for /proc/interrupts 275 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 276 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 277 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) 278 * @irq_disable: disable the interrupt 279 * @irq_ack: start of a new interrupt 280 * @irq_mask: mask an interrupt source 281 * @irq_mask_ack: ack and mask an interrupt source 282 * @irq_unmask: unmask an interrupt source 283 * @irq_eoi: end of interrupt 284 * @irq_set_affinity: set the CPU affinity on SMP machines 285 * @irq_retrigger: resend an IRQ to the CPU 286 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ 287 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 288 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 289 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 290 * @irq_cpu_online: configure an interrupt source for a secondary CPU 291 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU 292 * @irq_suspend: function called from core code on suspend once per chip 293 * @irq_resume: function called from core code on resume once per chip 294 * @irq_pm_shutdown: function called from core code on shutdown once per chip 295 * @irq_print_chip: optional to print special chip info in show_interrupts 296 * @flags: chip specific flags 297 * 298 * @release: release function solely used by UML 299 */ 300 struct irq_chip { 301 const char *name; 302 unsigned int (*irq_startup)(struct irq_data *data); 303 void (*irq_shutdown)(struct irq_data *data); 304 void (*irq_enable)(struct irq_data *data); 305 void (*irq_disable)(struct irq_data *data); 306 307 void (*irq_ack)(struct irq_data *data); 308 void (*irq_mask)(struct irq_data *data); 309 void (*irq_mask_ack)(struct irq_data *data); 310 void (*irq_unmask)(struct irq_data *data); 311 void (*irq_eoi)(struct irq_data *data); 312 313 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); 314 int (*irq_retrigger)(struct irq_data *data); 315 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); 316 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 317 318 void (*irq_bus_lock)(struct irq_data *data); 319 void (*irq_bus_sync_unlock)(struct irq_data *data); 320 321 void (*irq_cpu_online)(struct irq_data *data); 322 void (*irq_cpu_offline)(struct irq_data *data); 323 324 void (*irq_suspend)(struct irq_data *data); 325 void (*irq_resume)(struct irq_data *data); 326 void (*irq_pm_shutdown)(struct irq_data *data); 327 328 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 329 330 unsigned long flags; 331 332 /* Currently used only by UML, might disappear one day.*/ 333 #ifdef CONFIG_IRQ_RELEASE_METHOD 334 void (*release)(unsigned int irq, void *dev_id); 335 #endif 336 }; 337 338 /* 339 * irq_chip specific flags 340 * 341 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() 342 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled 343 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path 344 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks 345 * when irq enabled 346 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip 347 */ 348 enum { 349 IRQCHIP_SET_TYPE_MASKED = (1 << 0), 350 IRQCHIP_EOI_IF_HANDLED = (1 << 1), 351 IRQCHIP_MASK_ON_SUSPEND = (1 << 2), 352 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), 353 IRQCHIP_SKIP_SET_WAKE = (1 << 4), 354 }; 355 356 /* This include will go away once we isolated irq_desc usage to core code */ 357 #include <linux/irqdesc.h> 358 359 /* 360 * Pick up the arch-dependent methods: 361 */ 362 #include <asm/hw_irq.h> 363 364 #ifndef NR_IRQS_LEGACY 365 # define NR_IRQS_LEGACY 0 366 #endif 367 368 #ifndef ARCH_IRQ_INIT_FLAGS 369 # define ARCH_IRQ_INIT_FLAGS 0 370 #endif 371 372 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS 373 374 struct irqaction; 375 extern int setup_irq(unsigned int irq, struct irqaction *new); 376 extern void remove_irq(unsigned int irq, struct irqaction *act); 377 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); 378 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); 379 380 extern void irq_cpu_online(void); 381 extern void irq_cpu_offline(void); 382 extern int __irq_set_affinity_locked(struct irq_data *data, const struct cpumask *cpumask); 383 384 #ifdef CONFIG_GENERIC_HARDIRQS 385 386 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) 387 void irq_move_irq(struct irq_data *data); 388 void irq_move_masked_irq(struct irq_data *data); 389 #else 390 static inline void irq_move_irq(struct irq_data *data) { } 391 static inline void irq_move_masked_irq(struct irq_data *data) { } 392 #endif 393 394 extern int no_irq_affinity; 395 396 /* 397 * Built-in IRQ handlers for various IRQ types, 398 * callable via desc->handle_irq() 399 */ 400 extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); 401 extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); 402 extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); 403 extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc); 404 extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); 405 extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); 406 extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc); 407 extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); 408 extern void handle_nested_irq(unsigned int irq); 409 410 /* Handling of unhandled and spurious interrupts: */ 411 extern void note_interrupt(unsigned int irq, struct irq_desc *desc, 412 irqreturn_t action_ret); 413 414 415 /* Enable/disable irq debugging output: */ 416 extern int noirqdebug_setup(char *str); 417 418 /* Checks whether the interrupt can be requested by request_irq(): */ 419 extern int can_request_irq(unsigned int irq, unsigned long irqflags); 420 421 /* Dummy irq-chip implementations: */ 422 extern struct irq_chip no_irq_chip; 423 extern struct irq_chip dummy_irq_chip; 424 425 extern void 426 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, 427 irq_flow_handler_t handle, const char *name); 428 429 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, 430 irq_flow_handler_t handle) 431 { 432 irq_set_chip_and_handler_name(irq, chip, handle, NULL); 433 } 434 435 extern int irq_set_percpu_devid(unsigned int irq); 436 437 extern void 438 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, 439 const char *name); 440 441 static inline void 442 irq_set_handler(unsigned int irq, irq_flow_handler_t handle) 443 { 444 __irq_set_handler(irq, handle, 0, NULL); 445 } 446 447 /* 448 * Set a highlevel chained flow handler for a given IRQ. 449 * (a chained handler is automatically enabled and set to 450 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 451 */ 452 static inline void 453 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) 454 { 455 __irq_set_handler(irq, handle, 1, NULL); 456 } 457 458 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); 459 460 static inline void irq_set_status_flags(unsigned int irq, unsigned long set) 461 { 462 irq_modify_status(irq, 0, set); 463 } 464 465 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) 466 { 467 irq_modify_status(irq, clr, 0); 468 } 469 470 static inline void irq_set_noprobe(unsigned int irq) 471 { 472 irq_modify_status(irq, 0, IRQ_NOPROBE); 473 } 474 475 static inline void irq_set_probe(unsigned int irq) 476 { 477 irq_modify_status(irq, IRQ_NOPROBE, 0); 478 } 479 480 static inline void irq_set_nothread(unsigned int irq) 481 { 482 irq_modify_status(irq, 0, IRQ_NOTHREAD); 483 } 484 485 static inline void irq_set_thread(unsigned int irq) 486 { 487 irq_modify_status(irq, IRQ_NOTHREAD, 0); 488 } 489 490 static inline void irq_set_nested_thread(unsigned int irq, bool nest) 491 { 492 if (nest) 493 irq_set_status_flags(irq, IRQ_NESTED_THREAD); 494 else 495 irq_clear_status_flags(irq, IRQ_NESTED_THREAD); 496 } 497 498 static inline void irq_set_percpu_devid_flags(unsigned int irq) 499 { 500 irq_set_status_flags(irq, 501 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | 502 IRQ_NOPROBE | IRQ_PER_CPU_DEVID); 503 } 504 505 /* Handle dynamic irq creation and destruction */ 506 extern unsigned int create_irq_nr(unsigned int irq_want, int node); 507 extern int create_irq(void); 508 extern void destroy_irq(unsigned int irq); 509 510 /* 511 * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and 512 * irq_free_desc instead. 513 */ 514 extern void dynamic_irq_cleanup(unsigned int irq); 515 static inline void dynamic_irq_init(unsigned int irq) 516 { 517 dynamic_irq_cleanup(irq); 518 } 519 520 /* Set/get chip/data for an IRQ: */ 521 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); 522 extern int irq_set_handler_data(unsigned int irq, void *data); 523 extern int irq_set_chip_data(unsigned int irq, void *data); 524 extern int irq_set_irq_type(unsigned int irq, unsigned int type); 525 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 526 extern struct irq_data *irq_get_irq_data(unsigned int irq); 527 528 static inline struct irq_chip *irq_get_chip(unsigned int irq) 529 { 530 struct irq_data *d = irq_get_irq_data(irq); 531 return d ? d->chip : NULL; 532 } 533 534 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) 535 { 536 return d->chip; 537 } 538 539 static inline void *irq_get_chip_data(unsigned int irq) 540 { 541 struct irq_data *d = irq_get_irq_data(irq); 542 return d ? d->chip_data : NULL; 543 } 544 545 static inline void *irq_data_get_irq_chip_data(struct irq_data *d) 546 { 547 return d->chip_data; 548 } 549 550 static inline void *irq_get_handler_data(unsigned int irq) 551 { 552 struct irq_data *d = irq_get_irq_data(irq); 553 return d ? d->handler_data : NULL; 554 } 555 556 static inline void *irq_data_get_irq_handler_data(struct irq_data *d) 557 { 558 return d->handler_data; 559 } 560 561 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) 562 { 563 struct irq_data *d = irq_get_irq_data(irq); 564 return d ? d->msi_desc : NULL; 565 } 566 567 static inline struct msi_desc *irq_data_get_msi(struct irq_data *d) 568 { 569 return d->msi_desc; 570 } 571 572 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, 573 struct module *owner); 574 575 /* use macros to avoid needing export.h for THIS_MODULE */ 576 #define irq_alloc_descs(irq, from, cnt, node) \ 577 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE) 578 579 #define irq_alloc_desc(node) \ 580 irq_alloc_descs(-1, 0, 1, node) 581 582 #define irq_alloc_desc_at(at, node) \ 583 irq_alloc_descs(at, at, 1, node) 584 585 #define irq_alloc_desc_from(from, node) \ 586 irq_alloc_descs(-1, from, 1, node) 587 588 void irq_free_descs(unsigned int irq, unsigned int cnt); 589 int irq_reserve_irqs(unsigned int from, unsigned int cnt); 590 591 static inline void irq_free_desc(unsigned int irq) 592 { 593 irq_free_descs(irq, 1); 594 } 595 596 static inline int irq_reserve_irq(unsigned int irq) 597 { 598 return irq_reserve_irqs(irq, 1); 599 } 600 601 #ifndef irq_reg_writel 602 # define irq_reg_writel(val, addr) writel(val, addr) 603 #endif 604 #ifndef irq_reg_readl 605 # define irq_reg_readl(addr) readl(addr) 606 #endif 607 608 /** 609 * struct irq_chip_regs - register offsets for struct irq_gci 610 * @enable: Enable register offset to reg_base 611 * @disable: Disable register offset to reg_base 612 * @mask: Mask register offset to reg_base 613 * @ack: Ack register offset to reg_base 614 * @eoi: Eoi register offset to reg_base 615 * @type: Type configuration register offset to reg_base 616 * @polarity: Polarity configuration register offset to reg_base 617 */ 618 struct irq_chip_regs { 619 unsigned long enable; 620 unsigned long disable; 621 unsigned long mask; 622 unsigned long ack; 623 unsigned long eoi; 624 unsigned long type; 625 unsigned long polarity; 626 }; 627 628 /** 629 * struct irq_chip_type - Generic interrupt chip instance for a flow type 630 * @chip: The real interrupt chip which provides the callbacks 631 * @regs: Register offsets for this chip 632 * @handler: Flow handler associated with this chip 633 * @type: Chip can handle these flow types 634 * 635 * A irq_generic_chip can have several instances of irq_chip_type when 636 * it requires different functions and register offsets for different 637 * flow types. 638 */ 639 struct irq_chip_type { 640 struct irq_chip chip; 641 struct irq_chip_regs regs; 642 irq_flow_handler_t handler; 643 u32 type; 644 }; 645 646 /** 647 * struct irq_chip_generic - Generic irq chip data structure 648 * @lock: Lock to protect register and cache data access 649 * @reg_base: Register base address (virtual) 650 * @irq_base: Interrupt base nr for this chip 651 * @irq_cnt: Number of interrupts handled by this chip 652 * @mask_cache: Cached mask register 653 * @type_cache: Cached type register 654 * @polarity_cache: Cached polarity register 655 * @wake_enabled: Interrupt can wakeup from suspend 656 * @wake_active: Interrupt is marked as an wakeup from suspend source 657 * @num_ct: Number of available irq_chip_type instances (usually 1) 658 * @private: Private data for non generic chip callbacks 659 * @list: List head for keeping track of instances 660 * @chip_types: Array of interrupt irq_chip_types 661 * 662 * Note, that irq_chip_generic can have multiple irq_chip_type 663 * implementations which can be associated to a particular irq line of 664 * an irq_chip_generic instance. That allows to share and protect 665 * state in an irq_chip_generic instance when we need to implement 666 * different flow mechanisms (level/edge) for it. 667 */ 668 struct irq_chip_generic { 669 raw_spinlock_t lock; 670 void __iomem *reg_base; 671 unsigned int irq_base; 672 unsigned int irq_cnt; 673 u32 mask_cache; 674 u32 type_cache; 675 u32 polarity_cache; 676 u32 wake_enabled; 677 u32 wake_active; 678 unsigned int num_ct; 679 void *private; 680 struct list_head list; 681 struct irq_chip_type chip_types[0]; 682 }; 683 684 /** 685 * enum irq_gc_flags - Initialization flags for generic irq chips 686 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg 687 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for 688 * irq chips which need to call irq_set_wake() on 689 * the parent irq. Usually GPIO implementations 690 */ 691 enum irq_gc_flags { 692 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 693 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 694 }; 695 696 /* Generic chip callback functions */ 697 void irq_gc_noop(struct irq_data *d); 698 void irq_gc_mask_disable_reg(struct irq_data *d); 699 void irq_gc_mask_set_bit(struct irq_data *d); 700 void irq_gc_mask_clr_bit(struct irq_data *d); 701 void irq_gc_unmask_enable_reg(struct irq_data *d); 702 void irq_gc_ack_set_bit(struct irq_data *d); 703 void irq_gc_ack_clr_bit(struct irq_data *d); 704 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); 705 void irq_gc_eoi(struct irq_data *d); 706 int irq_gc_set_wake(struct irq_data *d, unsigned int on); 707 708 /* Setup functions for irq_chip_generic */ 709 struct irq_chip_generic * 710 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, 711 void __iomem *reg_base, irq_flow_handler_t handler); 712 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 713 enum irq_gc_flags flags, unsigned int clr, 714 unsigned int set); 715 int irq_setup_alt_chip(struct irq_data *d, unsigned int type); 716 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 717 unsigned int clr, unsigned int set); 718 719 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) 720 { 721 return container_of(d->chip, struct irq_chip_type, chip); 722 } 723 724 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) 725 726 #ifdef CONFIG_SMP 727 static inline void irq_gc_lock(struct irq_chip_generic *gc) 728 { 729 raw_spin_lock(&gc->lock); 730 } 731 732 static inline void irq_gc_unlock(struct irq_chip_generic *gc) 733 { 734 raw_spin_unlock(&gc->lock); 735 } 736 #else 737 static inline void irq_gc_lock(struct irq_chip_generic *gc) { } 738 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } 739 #endif 740 741 #endif /* CONFIG_GENERIC_HARDIRQS */ 742 743 #endif /* !CONFIG_S390 */ 744 745 #endif /* _LINUX_IRQ_H */ 746