1 #ifndef _LINUX_IRQ_H 2 #define _LINUX_IRQ_H 3 4 /* 5 * Please do not include this file in generic code. There is currently 6 * no requirement for any architecture to implement anything held 7 * within this file. 8 * 9 * Thanks. --rmk 10 */ 11 12 #include <linux/smp.h> 13 14 #ifndef CONFIG_S390 15 16 #include <linux/linkage.h> 17 #include <linux/cache.h> 18 #include <linux/spinlock.h> 19 #include <linux/cpumask.h> 20 #include <linux/gfp.h> 21 #include <linux/irqreturn.h> 22 #include <linux/irqnr.h> 23 #include <linux/errno.h> 24 #include <linux/topology.h> 25 #include <linux/wait.h> 26 27 #include <asm/irq.h> 28 #include <asm/ptrace.h> 29 #include <asm/irq_regs.h> 30 31 struct seq_file; 32 struct irq_desc; 33 struct irq_data; 34 typedef void (*irq_flow_handler_t)(unsigned int irq, 35 struct irq_desc *desc); 36 typedef void (*irq_preflow_handler_t)(struct irq_data *data); 37 38 /* 39 * IRQ line status. 40 * 41 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h 42 * 43 * IRQ_TYPE_NONE - default, unspecified type 44 * IRQ_TYPE_EDGE_RISING - rising edge triggered 45 * IRQ_TYPE_EDGE_FALLING - falling edge triggered 46 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 47 * IRQ_TYPE_LEVEL_HIGH - high level triggered 48 * IRQ_TYPE_LEVEL_LOW - low level triggered 49 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 50 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits 51 * IRQ_TYPE_PROBE - Special flag for probing in progress 52 * 53 * Bits which can be modified via irq_set/clear/modify_status_flags() 54 * IRQ_LEVEL - Interrupt is level type. Will be also 55 * updated in the code when the above trigger 56 * bits are modified via irq_set_irq_type() 57 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect 58 * it from affinity setting 59 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing 60 * IRQ_NOREQUEST - Interrupt cannot be requested via 61 * request_irq() 62 * IRQ_NOTHREAD - Interrupt cannot be threaded 63 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in 64 * request/setup_irq() 65 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) 66 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context 67 * IRQ_NESTED_TRHEAD - Interrupt nests into another thread 68 */ 69 enum { 70 IRQ_TYPE_NONE = 0x00000000, 71 IRQ_TYPE_EDGE_RISING = 0x00000001, 72 IRQ_TYPE_EDGE_FALLING = 0x00000002, 73 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), 74 IRQ_TYPE_LEVEL_HIGH = 0x00000004, 75 IRQ_TYPE_LEVEL_LOW = 0x00000008, 76 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), 77 IRQ_TYPE_SENSE_MASK = 0x0000000f, 78 79 IRQ_TYPE_PROBE = 0x00000010, 80 81 IRQ_LEVEL = (1 << 8), 82 IRQ_PER_CPU = (1 << 9), 83 IRQ_NOPROBE = (1 << 10), 84 IRQ_NOREQUEST = (1 << 11), 85 IRQ_NOAUTOEN = (1 << 12), 86 IRQ_NO_BALANCING = (1 << 13), 87 IRQ_MOVE_PCNTXT = (1 << 14), 88 IRQ_NESTED_THREAD = (1 << 15), 89 IRQ_NOTHREAD = (1 << 16), 90 }; 91 92 #define IRQF_MODIFY_MASK \ 93 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ 94 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ 95 IRQ_PER_CPU | IRQ_NESTED_THREAD) 96 97 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 98 99 static inline __deprecated bool CHECK_IRQ_PER_CPU(unsigned int status) 100 { 101 return status & IRQ_PER_CPU; 102 } 103 104 /* 105 * Return value for chip->irq_set_affinity() 106 * 107 * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity 108 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity 109 */ 110 enum { 111 IRQ_SET_MASK_OK = 0, 112 IRQ_SET_MASK_OK_NOCOPY, 113 }; 114 115 struct msi_desc; 116 117 /** 118 * struct irq_data - per irq and irq chip data passed down to chip functions 119 * @irq: interrupt number 120 * @node: node index useful for balancing 121 * @state_use_accessors: status information for irq chip functions. 122 * Use accessor functions to deal with it 123 * @chip: low level interrupt hardware access 124 * @handler_data: per-IRQ data for the irq_chip methods 125 * @chip_data: platform-specific per-chip private data for the chip 126 * methods, to allow shared chip implementations 127 * @msi_desc: MSI descriptor 128 * @affinity: IRQ affinity on SMP 129 * 130 * The fields here need to overlay the ones in irq_desc until we 131 * cleaned up the direct references and switched everything over to 132 * irq_data. 133 */ 134 struct irq_data { 135 unsigned int irq; 136 unsigned int node; 137 unsigned int state_use_accessors; 138 struct irq_chip *chip; 139 void *handler_data; 140 void *chip_data; 141 struct msi_desc *msi_desc; 142 #ifdef CONFIG_SMP 143 cpumask_var_t affinity; 144 #endif 145 }; 146 147 /* 148 * Bit masks for irq_data.state 149 * 150 * IRQD_TRIGGER_MASK - Mask for the trigger type bits 151 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 152 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 153 * IRQD_PER_CPU - Interrupt is per cpu 154 * IRQD_AFFINITY_SET - Interrupt affinity was set 155 * IRQD_LEVEL - Interrupt is level triggered 156 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup 157 * from suspend 158 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process 159 * context 160 * IRQD_IRQ_DISABLED - Disabled state of the interrupt 161 * IRQD_IRQ_MASKED - Masked state of the interrupt 162 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt 163 */ 164 enum { 165 IRQD_TRIGGER_MASK = 0xf, 166 IRQD_SETAFFINITY_PENDING = (1 << 8), 167 IRQD_NO_BALANCING = (1 << 10), 168 IRQD_PER_CPU = (1 << 11), 169 IRQD_AFFINITY_SET = (1 << 12), 170 IRQD_LEVEL = (1 << 13), 171 IRQD_WAKEUP_STATE = (1 << 14), 172 IRQD_MOVE_PCNTXT = (1 << 15), 173 IRQD_IRQ_DISABLED = (1 << 16), 174 IRQD_IRQ_MASKED = (1 << 17), 175 IRQD_IRQ_INPROGRESS = (1 << 18), 176 }; 177 178 static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 179 { 180 return d->state_use_accessors & IRQD_SETAFFINITY_PENDING; 181 } 182 183 static inline bool irqd_is_per_cpu(struct irq_data *d) 184 { 185 return d->state_use_accessors & IRQD_PER_CPU; 186 } 187 188 static inline bool irqd_can_balance(struct irq_data *d) 189 { 190 return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING)); 191 } 192 193 static inline bool irqd_affinity_was_set(struct irq_data *d) 194 { 195 return d->state_use_accessors & IRQD_AFFINITY_SET; 196 } 197 198 static inline void irqd_mark_affinity_was_set(struct irq_data *d) 199 { 200 d->state_use_accessors |= IRQD_AFFINITY_SET; 201 } 202 203 static inline u32 irqd_get_trigger_type(struct irq_data *d) 204 { 205 return d->state_use_accessors & IRQD_TRIGGER_MASK; 206 } 207 208 /* 209 * Must only be called inside irq_chip.irq_set_type() functions. 210 */ 211 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) 212 { 213 d->state_use_accessors &= ~IRQD_TRIGGER_MASK; 214 d->state_use_accessors |= type & IRQD_TRIGGER_MASK; 215 } 216 217 static inline bool irqd_is_level_type(struct irq_data *d) 218 { 219 return d->state_use_accessors & IRQD_LEVEL; 220 } 221 222 static inline bool irqd_is_wakeup_set(struct irq_data *d) 223 { 224 return d->state_use_accessors & IRQD_WAKEUP_STATE; 225 } 226 227 static inline bool irqd_can_move_in_process_context(struct irq_data *d) 228 { 229 return d->state_use_accessors & IRQD_MOVE_PCNTXT; 230 } 231 232 static inline bool irqd_irq_disabled(struct irq_data *d) 233 { 234 return d->state_use_accessors & IRQD_IRQ_DISABLED; 235 } 236 237 static inline bool irqd_irq_masked(struct irq_data *d) 238 { 239 return d->state_use_accessors & IRQD_IRQ_MASKED; 240 } 241 242 static inline bool irqd_irq_inprogress(struct irq_data *d) 243 { 244 return d->state_use_accessors & IRQD_IRQ_INPROGRESS; 245 } 246 247 /* 248 * Functions for chained handlers which can be enabled/disabled by the 249 * standard disable_irq/enable_irq calls. Must be called with 250 * irq_desc->lock held. 251 */ 252 static inline void irqd_set_chained_irq_inprogress(struct irq_data *d) 253 { 254 d->state_use_accessors |= IRQD_IRQ_INPROGRESS; 255 } 256 257 static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d) 258 { 259 d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS; 260 } 261 262 /** 263 * struct irq_chip - hardware interrupt chip descriptor 264 * 265 * @name: name for /proc/interrupts 266 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 267 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 268 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) 269 * @irq_disable: disable the interrupt 270 * @irq_ack: start of a new interrupt 271 * @irq_mask: mask an interrupt source 272 * @irq_mask_ack: ack and mask an interrupt source 273 * @irq_unmask: unmask an interrupt source 274 * @irq_eoi: end of interrupt 275 * @irq_set_affinity: set the CPU affinity on SMP machines 276 * @irq_retrigger: resend an IRQ to the CPU 277 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ 278 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 279 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 280 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 281 * @irq_cpu_online: configure an interrupt source for a secondary CPU 282 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU 283 * @irq_suspend: function called from core code on suspend once per chip 284 * @irq_resume: function called from core code on resume once per chip 285 * @irq_pm_shutdown: function called from core code on shutdown once per chip 286 * @irq_print_chip: optional to print special chip info in show_interrupts 287 * @flags: chip specific flags 288 * 289 * @release: release function solely used by UML 290 */ 291 struct irq_chip { 292 const char *name; 293 unsigned int (*irq_startup)(struct irq_data *data); 294 void (*irq_shutdown)(struct irq_data *data); 295 void (*irq_enable)(struct irq_data *data); 296 void (*irq_disable)(struct irq_data *data); 297 298 void (*irq_ack)(struct irq_data *data); 299 void (*irq_mask)(struct irq_data *data); 300 void (*irq_mask_ack)(struct irq_data *data); 301 void (*irq_unmask)(struct irq_data *data); 302 void (*irq_eoi)(struct irq_data *data); 303 304 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); 305 int (*irq_retrigger)(struct irq_data *data); 306 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); 307 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 308 309 void (*irq_bus_lock)(struct irq_data *data); 310 void (*irq_bus_sync_unlock)(struct irq_data *data); 311 312 void (*irq_cpu_online)(struct irq_data *data); 313 void (*irq_cpu_offline)(struct irq_data *data); 314 315 void (*irq_suspend)(struct irq_data *data); 316 void (*irq_resume)(struct irq_data *data); 317 void (*irq_pm_shutdown)(struct irq_data *data); 318 319 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 320 321 unsigned long flags; 322 323 /* Currently used only by UML, might disappear one day.*/ 324 #ifdef CONFIG_IRQ_RELEASE_METHOD 325 void (*release)(unsigned int irq, void *dev_id); 326 #endif 327 }; 328 329 /* 330 * irq_chip specific flags 331 * 332 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() 333 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled 334 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path 335 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks 336 * when irq enabled 337 */ 338 enum { 339 IRQCHIP_SET_TYPE_MASKED = (1 << 0), 340 IRQCHIP_EOI_IF_HANDLED = (1 << 1), 341 IRQCHIP_MASK_ON_SUSPEND = (1 << 2), 342 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), 343 }; 344 345 /* This include will go away once we isolated irq_desc usage to core code */ 346 #include <linux/irqdesc.h> 347 348 /* 349 * Pick up the arch-dependent methods: 350 */ 351 #include <asm/hw_irq.h> 352 353 #ifndef NR_IRQS_LEGACY 354 # define NR_IRQS_LEGACY 0 355 #endif 356 357 #ifndef ARCH_IRQ_INIT_FLAGS 358 # define ARCH_IRQ_INIT_FLAGS 0 359 #endif 360 361 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS 362 363 struct irqaction; 364 extern int setup_irq(unsigned int irq, struct irqaction *new); 365 extern void remove_irq(unsigned int irq, struct irqaction *act); 366 367 extern void irq_cpu_online(void); 368 extern void irq_cpu_offline(void); 369 extern int __irq_set_affinity_locked(struct irq_data *data, const struct cpumask *cpumask); 370 371 #ifdef CONFIG_GENERIC_HARDIRQS 372 373 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) 374 void irq_move_irq(struct irq_data *data); 375 void irq_move_masked_irq(struct irq_data *data); 376 #else 377 static inline void irq_move_irq(struct irq_data *data) { } 378 static inline void irq_move_masked_irq(struct irq_data *data) { } 379 #endif 380 381 extern int no_irq_affinity; 382 383 /* 384 * Built-in IRQ handlers for various IRQ types, 385 * callable via desc->handle_irq() 386 */ 387 extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); 388 extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); 389 extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); 390 extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc); 391 extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); 392 extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); 393 extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); 394 extern void handle_nested_irq(unsigned int irq); 395 396 /* Handling of unhandled and spurious interrupts: */ 397 extern void note_interrupt(unsigned int irq, struct irq_desc *desc, 398 irqreturn_t action_ret); 399 400 401 /* Enable/disable irq debugging output: */ 402 extern int noirqdebug_setup(char *str); 403 404 /* Checks whether the interrupt can be requested by request_irq(): */ 405 extern int can_request_irq(unsigned int irq, unsigned long irqflags); 406 407 /* Dummy irq-chip implementations: */ 408 extern struct irq_chip no_irq_chip; 409 extern struct irq_chip dummy_irq_chip; 410 411 extern void 412 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, 413 irq_flow_handler_t handle, const char *name); 414 415 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, 416 irq_flow_handler_t handle) 417 { 418 irq_set_chip_and_handler_name(irq, chip, handle, NULL); 419 } 420 421 extern void 422 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, 423 const char *name); 424 425 static inline void 426 irq_set_handler(unsigned int irq, irq_flow_handler_t handle) 427 { 428 __irq_set_handler(irq, handle, 0, NULL); 429 } 430 431 /* 432 * Set a highlevel chained flow handler for a given IRQ. 433 * (a chained handler is automatically enabled and set to 434 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 435 */ 436 static inline void 437 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) 438 { 439 __irq_set_handler(irq, handle, 1, NULL); 440 } 441 442 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); 443 444 static inline void irq_set_status_flags(unsigned int irq, unsigned long set) 445 { 446 irq_modify_status(irq, 0, set); 447 } 448 449 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) 450 { 451 irq_modify_status(irq, clr, 0); 452 } 453 454 static inline void irq_set_noprobe(unsigned int irq) 455 { 456 irq_modify_status(irq, 0, IRQ_NOPROBE); 457 } 458 459 static inline void irq_set_probe(unsigned int irq) 460 { 461 irq_modify_status(irq, IRQ_NOPROBE, 0); 462 } 463 464 static inline void irq_set_nothread(unsigned int irq) 465 { 466 irq_modify_status(irq, 0, IRQ_NOTHREAD); 467 } 468 469 static inline void irq_set_thread(unsigned int irq) 470 { 471 irq_modify_status(irq, IRQ_NOTHREAD, 0); 472 } 473 474 static inline void irq_set_nested_thread(unsigned int irq, bool nest) 475 { 476 if (nest) 477 irq_set_status_flags(irq, IRQ_NESTED_THREAD); 478 else 479 irq_clear_status_flags(irq, IRQ_NESTED_THREAD); 480 } 481 482 /* Handle dynamic irq creation and destruction */ 483 extern unsigned int create_irq_nr(unsigned int irq_want, int node); 484 extern int create_irq(void); 485 extern void destroy_irq(unsigned int irq); 486 487 /* 488 * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and 489 * irq_free_desc instead. 490 */ 491 extern void dynamic_irq_cleanup(unsigned int irq); 492 static inline void dynamic_irq_init(unsigned int irq) 493 { 494 dynamic_irq_cleanup(irq); 495 } 496 497 /* Set/get chip/data for an IRQ: */ 498 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); 499 extern int irq_set_handler_data(unsigned int irq, void *data); 500 extern int irq_set_chip_data(unsigned int irq, void *data); 501 extern int irq_set_irq_type(unsigned int irq, unsigned int type); 502 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 503 extern struct irq_data *irq_get_irq_data(unsigned int irq); 504 505 static inline struct irq_chip *irq_get_chip(unsigned int irq) 506 { 507 struct irq_data *d = irq_get_irq_data(irq); 508 return d ? d->chip : NULL; 509 } 510 511 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) 512 { 513 return d->chip; 514 } 515 516 static inline void *irq_get_chip_data(unsigned int irq) 517 { 518 struct irq_data *d = irq_get_irq_data(irq); 519 return d ? d->chip_data : NULL; 520 } 521 522 static inline void *irq_data_get_irq_chip_data(struct irq_data *d) 523 { 524 return d->chip_data; 525 } 526 527 static inline void *irq_get_handler_data(unsigned int irq) 528 { 529 struct irq_data *d = irq_get_irq_data(irq); 530 return d ? d->handler_data : NULL; 531 } 532 533 static inline void *irq_data_get_irq_handler_data(struct irq_data *d) 534 { 535 return d->handler_data; 536 } 537 538 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) 539 { 540 struct irq_data *d = irq_get_irq_data(irq); 541 return d ? d->msi_desc : NULL; 542 } 543 544 static inline struct msi_desc *irq_data_get_msi(struct irq_data *d) 545 { 546 return d->msi_desc; 547 } 548 549 int irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node); 550 void irq_free_descs(unsigned int irq, unsigned int cnt); 551 int irq_reserve_irqs(unsigned int from, unsigned int cnt); 552 553 static inline int irq_alloc_desc(int node) 554 { 555 return irq_alloc_descs(-1, 0, 1, node); 556 } 557 558 static inline int irq_alloc_desc_at(unsigned int at, int node) 559 { 560 return irq_alloc_descs(at, at, 1, node); 561 } 562 563 static inline int irq_alloc_desc_from(unsigned int from, int node) 564 { 565 return irq_alloc_descs(-1, from, 1, node); 566 } 567 568 static inline void irq_free_desc(unsigned int irq) 569 { 570 irq_free_descs(irq, 1); 571 } 572 573 static inline int irq_reserve_irq(unsigned int irq) 574 { 575 return irq_reserve_irqs(irq, 1); 576 } 577 578 #ifndef irq_reg_writel 579 # define irq_reg_writel(val, addr) writel(val, addr) 580 #endif 581 #ifndef irq_reg_readl 582 # define irq_reg_readl(addr) readl(addr) 583 #endif 584 585 /** 586 * struct irq_chip_regs - register offsets for struct irq_gci 587 * @enable: Enable register offset to reg_base 588 * @disable: Disable register offset to reg_base 589 * @mask: Mask register offset to reg_base 590 * @ack: Ack register offset to reg_base 591 * @eoi: Eoi register offset to reg_base 592 * @type: Type configuration register offset to reg_base 593 * @polarity: Polarity configuration register offset to reg_base 594 */ 595 struct irq_chip_regs { 596 unsigned long enable; 597 unsigned long disable; 598 unsigned long mask; 599 unsigned long ack; 600 unsigned long eoi; 601 unsigned long type; 602 unsigned long polarity; 603 }; 604 605 /** 606 * struct irq_chip_type - Generic interrupt chip instance for a flow type 607 * @chip: The real interrupt chip which provides the callbacks 608 * @regs: Register offsets for this chip 609 * @handler: Flow handler associated with this chip 610 * @type: Chip can handle these flow types 611 * 612 * A irq_generic_chip can have several instances of irq_chip_type when 613 * it requires different functions and register offsets for different 614 * flow types. 615 */ 616 struct irq_chip_type { 617 struct irq_chip chip; 618 struct irq_chip_regs regs; 619 irq_flow_handler_t handler; 620 u32 type; 621 }; 622 623 /** 624 * struct irq_chip_generic - Generic irq chip data structure 625 * @lock: Lock to protect register and cache data access 626 * @reg_base: Register base address (virtual) 627 * @irq_base: Interrupt base nr for this chip 628 * @irq_cnt: Number of interrupts handled by this chip 629 * @mask_cache: Cached mask register 630 * @type_cache: Cached type register 631 * @polarity_cache: Cached polarity register 632 * @wake_enabled: Interrupt can wakeup from suspend 633 * @wake_active: Interrupt is marked as an wakeup from suspend source 634 * @num_ct: Number of available irq_chip_type instances (usually 1) 635 * @private: Private data for non generic chip callbacks 636 * @list: List head for keeping track of instances 637 * @chip_types: Array of interrupt irq_chip_types 638 * 639 * Note, that irq_chip_generic can have multiple irq_chip_type 640 * implementations which can be associated to a particular irq line of 641 * an irq_chip_generic instance. That allows to share and protect 642 * state in an irq_chip_generic instance when we need to implement 643 * different flow mechanisms (level/edge) for it. 644 */ 645 struct irq_chip_generic { 646 raw_spinlock_t lock; 647 void __iomem *reg_base; 648 unsigned int irq_base; 649 unsigned int irq_cnt; 650 u32 mask_cache; 651 u32 type_cache; 652 u32 polarity_cache; 653 u32 wake_enabled; 654 u32 wake_active; 655 unsigned int num_ct; 656 void *private; 657 struct list_head list; 658 struct irq_chip_type chip_types[0]; 659 }; 660 661 /** 662 * enum irq_gc_flags - Initialization flags for generic irq chips 663 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg 664 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for 665 * irq chips which need to call irq_set_wake() on 666 * the parent irq. Usually GPIO implementations 667 */ 668 enum irq_gc_flags { 669 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 670 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 671 }; 672 673 /* Generic chip callback functions */ 674 void irq_gc_noop(struct irq_data *d); 675 void irq_gc_mask_disable_reg(struct irq_data *d); 676 void irq_gc_mask_set_bit(struct irq_data *d); 677 void irq_gc_mask_clr_bit(struct irq_data *d); 678 void irq_gc_unmask_enable_reg(struct irq_data *d); 679 void irq_gc_ack(struct irq_data *d); 680 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); 681 void irq_gc_eoi(struct irq_data *d); 682 int irq_gc_set_wake(struct irq_data *d, unsigned int on); 683 684 /* Setup functions for irq_chip_generic */ 685 struct irq_chip_generic * 686 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, 687 void __iomem *reg_base, irq_flow_handler_t handler); 688 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 689 enum irq_gc_flags flags, unsigned int clr, 690 unsigned int set); 691 int irq_setup_alt_chip(struct irq_data *d, unsigned int type); 692 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 693 unsigned int clr, unsigned int set); 694 695 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) 696 { 697 return container_of(d->chip, struct irq_chip_type, chip); 698 } 699 700 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) 701 702 #ifdef CONFIG_SMP 703 static inline void irq_gc_lock(struct irq_chip_generic *gc) 704 { 705 raw_spin_lock(&gc->lock); 706 } 707 708 static inline void irq_gc_unlock(struct irq_chip_generic *gc) 709 { 710 raw_spin_unlock(&gc->lock); 711 } 712 #else 713 static inline void irq_gc_lock(struct irq_chip_generic *gc) { } 714 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } 715 #endif 716 717 #endif /* CONFIG_GENERIC_HARDIRQS */ 718 719 #endif /* !CONFIG_S390 */ 720 721 #endif /* _LINUX_IRQ_H */ 722