1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_IRQ_H 3 #define _LINUX_IRQ_H 4 5 /* 6 * Please do not include this file in generic code. There is currently 7 * no requirement for any architecture to implement anything held 8 * within this file. 9 * 10 * Thanks. --rmk 11 */ 12 13 #include <linux/cache.h> 14 #include <linux/spinlock.h> 15 #include <linux/cpumask.h> 16 #include <linux/irqhandler.h> 17 #include <linux/irqreturn.h> 18 #include <linux/irqnr.h> 19 #include <linux/topology.h> 20 #include <linux/io.h> 21 #include <linux/slab.h> 22 23 #include <asm/irq.h> 24 #include <asm/ptrace.h> 25 #include <asm/irq_regs.h> 26 27 struct seq_file; 28 struct module; 29 struct msi_msg; 30 struct irq_affinity_desc; 31 enum irqchip_irq_state; 32 33 /* 34 * IRQ line status. 35 * 36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h 37 * 38 * IRQ_TYPE_NONE - default, unspecified type 39 * IRQ_TYPE_EDGE_RISING - rising edge triggered 40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered 41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 42 * IRQ_TYPE_LEVEL_HIGH - high level triggered 43 * IRQ_TYPE_LEVEL_LOW - low level triggered 44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 45 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits 46 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type 47 * to setup the HW to a sane default (used 48 * by irqdomain map() callbacks to synchronize 49 * the HW state and SW flags for a newly 50 * allocated descriptor). 51 * 52 * IRQ_TYPE_PROBE - Special flag for probing in progress 53 * 54 * Bits which can be modified via irq_set/clear/modify_status_flags() 55 * IRQ_LEVEL - Interrupt is level type. Will be also 56 * updated in the code when the above trigger 57 * bits are modified via irq_set_irq_type() 58 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect 59 * it from affinity setting 60 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing 61 * IRQ_NOREQUEST - Interrupt cannot be requested via 62 * request_irq() 63 * IRQ_NOTHREAD - Interrupt cannot be threaded 64 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in 65 * request/setup_irq() 66 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) 67 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context 68 * IRQ_NESTED_THREAD - Interrupt nests into another thread 69 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable 70 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude 71 * it from the spurious interrupt detection 72 * mechanism and from core side polling. 73 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable 74 */ 75 enum { 76 IRQ_TYPE_NONE = 0x00000000, 77 IRQ_TYPE_EDGE_RISING = 0x00000001, 78 IRQ_TYPE_EDGE_FALLING = 0x00000002, 79 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), 80 IRQ_TYPE_LEVEL_HIGH = 0x00000004, 81 IRQ_TYPE_LEVEL_LOW = 0x00000008, 82 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), 83 IRQ_TYPE_SENSE_MASK = 0x0000000f, 84 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, 85 86 IRQ_TYPE_PROBE = 0x00000010, 87 88 IRQ_LEVEL = (1 << 8), 89 IRQ_PER_CPU = (1 << 9), 90 IRQ_NOPROBE = (1 << 10), 91 IRQ_NOREQUEST = (1 << 11), 92 IRQ_NOAUTOEN = (1 << 12), 93 IRQ_NO_BALANCING = (1 << 13), 94 IRQ_MOVE_PCNTXT = (1 << 14), 95 IRQ_NESTED_THREAD = (1 << 15), 96 IRQ_NOTHREAD = (1 << 16), 97 IRQ_PER_CPU_DEVID = (1 << 17), 98 IRQ_IS_POLLED = (1 << 18), 99 IRQ_DISABLE_UNLAZY = (1 << 19), 100 }; 101 102 #define IRQF_MODIFY_MASK \ 103 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ 104 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ 105 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ 106 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY) 107 108 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 109 110 /* 111 * Return value for chip->irq_set_affinity() 112 * 113 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity 114 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity 115 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to 116 * support stacked irqchips, which indicates skipping 117 * all descendent irqchips. 118 */ 119 enum { 120 IRQ_SET_MASK_OK = 0, 121 IRQ_SET_MASK_OK_NOCOPY, 122 IRQ_SET_MASK_OK_DONE, 123 }; 124 125 struct msi_desc; 126 struct irq_domain; 127 128 /** 129 * struct irq_common_data - per irq data shared by all irqchips 130 * @state_use_accessors: status information for irq chip functions. 131 * Use accessor functions to deal with it 132 * @node: node index useful for balancing 133 * @handler_data: per-IRQ data for the irq_chip methods 134 * @affinity: IRQ affinity on SMP. If this is an IPI 135 * related irq, then this is the mask of the 136 * CPUs to which an IPI can be sent. 137 * @effective_affinity: The effective IRQ affinity on SMP as some irq 138 * chips do not allow multi CPU destinations. 139 * A subset of @affinity. 140 * @msi_desc: MSI descriptor 141 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional. 142 */ 143 struct irq_common_data { 144 unsigned int __private state_use_accessors; 145 #ifdef CONFIG_NUMA 146 unsigned int node; 147 #endif 148 void *handler_data; 149 struct msi_desc *msi_desc; 150 cpumask_var_t affinity; 151 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 152 cpumask_var_t effective_affinity; 153 #endif 154 #ifdef CONFIG_GENERIC_IRQ_IPI 155 unsigned int ipi_offset; 156 #endif 157 }; 158 159 /** 160 * struct irq_data - per irq chip data passed down to chip functions 161 * @mask: precomputed bitmask for accessing the chip registers 162 * @irq: interrupt number 163 * @hwirq: hardware interrupt number, local to the interrupt domain 164 * @common: point to data shared by all irqchips 165 * @chip: low level interrupt hardware access 166 * @domain: Interrupt translation domain; responsible for mapping 167 * between hwirq number and linux irq number. 168 * @parent_data: pointer to parent struct irq_data to support hierarchy 169 * irq_domain 170 * @chip_data: platform-specific per-chip private data for the chip 171 * methods, to allow shared chip implementations 172 */ 173 struct irq_data { 174 u32 mask; 175 unsigned int irq; 176 unsigned long hwirq; 177 struct irq_common_data *common; 178 struct irq_chip *chip; 179 struct irq_domain *domain; 180 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 181 struct irq_data *parent_data; 182 #endif 183 void *chip_data; 184 }; 185 186 /* 187 * Bit masks for irq_common_data.state_use_accessors 188 * 189 * IRQD_TRIGGER_MASK - Mask for the trigger type bits 190 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 191 * IRQD_ACTIVATED - Interrupt has already been activated 192 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 193 * IRQD_PER_CPU - Interrupt is per cpu 194 * IRQD_AFFINITY_SET - Interrupt affinity was set 195 * IRQD_LEVEL - Interrupt is level triggered 196 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup 197 * from suspend 198 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process 199 * context 200 * IRQD_IRQ_DISABLED - Disabled state of the interrupt 201 * IRQD_IRQ_MASKED - Masked state of the interrupt 202 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt 203 * IRQD_WAKEUP_ARMED - Wakeup mode armed 204 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU 205 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel 206 * IRQD_IRQ_STARTED - Startup state of the interrupt 207 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity 208 * mask. Applies only to affinity managed irqs. 209 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target 210 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set 211 * IRQD_CAN_RESERVE - Can use reservation mode 212 */ 213 enum { 214 IRQD_TRIGGER_MASK = 0xf, 215 IRQD_SETAFFINITY_PENDING = (1 << 8), 216 IRQD_ACTIVATED = (1 << 9), 217 IRQD_NO_BALANCING = (1 << 10), 218 IRQD_PER_CPU = (1 << 11), 219 IRQD_AFFINITY_SET = (1 << 12), 220 IRQD_LEVEL = (1 << 13), 221 IRQD_WAKEUP_STATE = (1 << 14), 222 IRQD_MOVE_PCNTXT = (1 << 15), 223 IRQD_IRQ_DISABLED = (1 << 16), 224 IRQD_IRQ_MASKED = (1 << 17), 225 IRQD_IRQ_INPROGRESS = (1 << 18), 226 IRQD_WAKEUP_ARMED = (1 << 19), 227 IRQD_FORWARDED_TO_VCPU = (1 << 20), 228 IRQD_AFFINITY_MANAGED = (1 << 21), 229 IRQD_IRQ_STARTED = (1 << 22), 230 IRQD_MANAGED_SHUTDOWN = (1 << 23), 231 IRQD_SINGLE_TARGET = (1 << 24), 232 IRQD_DEFAULT_TRIGGER_SET = (1 << 25), 233 IRQD_CAN_RESERVE = (1 << 26), 234 }; 235 236 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors) 237 238 static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 239 { 240 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING; 241 } 242 243 static inline bool irqd_is_per_cpu(struct irq_data *d) 244 { 245 return __irqd_to_state(d) & IRQD_PER_CPU; 246 } 247 248 static inline bool irqd_can_balance(struct irq_data *d) 249 { 250 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); 251 } 252 253 static inline bool irqd_affinity_was_set(struct irq_data *d) 254 { 255 return __irqd_to_state(d) & IRQD_AFFINITY_SET; 256 } 257 258 static inline void irqd_mark_affinity_was_set(struct irq_data *d) 259 { 260 __irqd_to_state(d) |= IRQD_AFFINITY_SET; 261 } 262 263 static inline bool irqd_trigger_type_was_set(struct irq_data *d) 264 { 265 return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET; 266 } 267 268 static inline u32 irqd_get_trigger_type(struct irq_data *d) 269 { 270 return __irqd_to_state(d) & IRQD_TRIGGER_MASK; 271 } 272 273 /* 274 * Must only be called inside irq_chip.irq_set_type() functions or 275 * from the DT/ACPI setup code. 276 */ 277 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) 278 { 279 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK; 280 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK; 281 __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET; 282 } 283 284 static inline bool irqd_is_level_type(struct irq_data *d) 285 { 286 return __irqd_to_state(d) & IRQD_LEVEL; 287 } 288 289 /* 290 * Must only be called of irqchip.irq_set_affinity() or low level 291 * hieararchy domain allocation functions. 292 */ 293 static inline void irqd_set_single_target(struct irq_data *d) 294 { 295 __irqd_to_state(d) |= IRQD_SINGLE_TARGET; 296 } 297 298 static inline bool irqd_is_single_target(struct irq_data *d) 299 { 300 return __irqd_to_state(d) & IRQD_SINGLE_TARGET; 301 } 302 303 static inline bool irqd_is_wakeup_set(struct irq_data *d) 304 { 305 return __irqd_to_state(d) & IRQD_WAKEUP_STATE; 306 } 307 308 static inline bool irqd_can_move_in_process_context(struct irq_data *d) 309 { 310 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT; 311 } 312 313 static inline bool irqd_irq_disabled(struct irq_data *d) 314 { 315 return __irqd_to_state(d) & IRQD_IRQ_DISABLED; 316 } 317 318 static inline bool irqd_irq_masked(struct irq_data *d) 319 { 320 return __irqd_to_state(d) & IRQD_IRQ_MASKED; 321 } 322 323 static inline bool irqd_irq_inprogress(struct irq_data *d) 324 { 325 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; 326 } 327 328 static inline bool irqd_is_wakeup_armed(struct irq_data *d) 329 { 330 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED; 331 } 332 333 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d) 334 { 335 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU; 336 } 337 338 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d) 339 { 340 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU; 341 } 342 343 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d) 344 { 345 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; 346 } 347 348 static inline bool irqd_affinity_is_managed(struct irq_data *d) 349 { 350 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED; 351 } 352 353 static inline bool irqd_is_activated(struct irq_data *d) 354 { 355 return __irqd_to_state(d) & IRQD_ACTIVATED; 356 } 357 358 static inline void irqd_set_activated(struct irq_data *d) 359 { 360 __irqd_to_state(d) |= IRQD_ACTIVATED; 361 } 362 363 static inline void irqd_clr_activated(struct irq_data *d) 364 { 365 __irqd_to_state(d) &= ~IRQD_ACTIVATED; 366 } 367 368 static inline bool irqd_is_started(struct irq_data *d) 369 { 370 return __irqd_to_state(d) & IRQD_IRQ_STARTED; 371 } 372 373 static inline bool irqd_is_managed_and_shutdown(struct irq_data *d) 374 { 375 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN; 376 } 377 378 static inline void irqd_set_can_reserve(struct irq_data *d) 379 { 380 __irqd_to_state(d) |= IRQD_CAN_RESERVE; 381 } 382 383 static inline void irqd_clr_can_reserve(struct irq_data *d) 384 { 385 __irqd_to_state(d) &= ~IRQD_CAN_RESERVE; 386 } 387 388 static inline bool irqd_can_reserve(struct irq_data *d) 389 { 390 return __irqd_to_state(d) & IRQD_CAN_RESERVE; 391 } 392 393 #undef __irqd_to_state 394 395 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) 396 { 397 return d->hwirq; 398 } 399 400 /** 401 * struct irq_chip - hardware interrupt chip descriptor 402 * 403 * @parent_device: pointer to parent device for irqchip 404 * @name: name for /proc/interrupts 405 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 406 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 407 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) 408 * @irq_disable: disable the interrupt 409 * @irq_ack: start of a new interrupt 410 * @irq_mask: mask an interrupt source 411 * @irq_mask_ack: ack and mask an interrupt source 412 * @irq_unmask: unmask an interrupt source 413 * @irq_eoi: end of interrupt 414 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force 415 * argument is true, it tells the driver to 416 * unconditionally apply the affinity setting. Sanity 417 * checks against the supplied affinity mask are not 418 * required. This is used for CPU hotplug where the 419 * target CPU is not yet set in the cpu_online_mask. 420 * @irq_retrigger: resend an IRQ to the CPU 421 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ 422 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 423 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 424 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 425 * @irq_cpu_online: configure an interrupt source for a secondary CPU 426 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU 427 * @irq_suspend: function called from core code on suspend once per 428 * chip, when one or more interrupts are installed 429 * @irq_resume: function called from core code on resume once per chip, 430 * when one ore more interrupts are installed 431 * @irq_pm_shutdown: function called from core code on shutdown once per chip 432 * @irq_calc_mask: Optional function to set irq_data.mask for special cases 433 * @irq_print_chip: optional to print special chip info in show_interrupts 434 * @irq_request_resources: optional to request resources before calling 435 * any other callback related to this irq 436 * @irq_release_resources: optional to release resources acquired with 437 * irq_request_resources 438 * @irq_compose_msi_msg: optional to compose message content for MSI 439 * @irq_write_msi_msg: optional to write message content for MSI 440 * @irq_get_irqchip_state: return the internal state of an interrupt 441 * @irq_set_irqchip_state: set the internal state of a interrupt 442 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine 443 * @ipi_send_single: send a single IPI to destination cpus 444 * @ipi_send_mask: send an IPI to destination cpus in cpumask 445 * @irq_nmi_setup: function called from core code before enabling an NMI 446 * @irq_nmi_teardown: function called from core code after disabling an NMI 447 * @flags: chip specific flags 448 */ 449 struct irq_chip { 450 struct device *parent_device; 451 const char *name; 452 unsigned int (*irq_startup)(struct irq_data *data); 453 void (*irq_shutdown)(struct irq_data *data); 454 void (*irq_enable)(struct irq_data *data); 455 void (*irq_disable)(struct irq_data *data); 456 457 void (*irq_ack)(struct irq_data *data); 458 void (*irq_mask)(struct irq_data *data); 459 void (*irq_mask_ack)(struct irq_data *data); 460 void (*irq_unmask)(struct irq_data *data); 461 void (*irq_eoi)(struct irq_data *data); 462 463 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); 464 int (*irq_retrigger)(struct irq_data *data); 465 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); 466 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 467 468 void (*irq_bus_lock)(struct irq_data *data); 469 void (*irq_bus_sync_unlock)(struct irq_data *data); 470 471 void (*irq_cpu_online)(struct irq_data *data); 472 void (*irq_cpu_offline)(struct irq_data *data); 473 474 void (*irq_suspend)(struct irq_data *data); 475 void (*irq_resume)(struct irq_data *data); 476 void (*irq_pm_shutdown)(struct irq_data *data); 477 478 void (*irq_calc_mask)(struct irq_data *data); 479 480 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 481 int (*irq_request_resources)(struct irq_data *data); 482 void (*irq_release_resources)(struct irq_data *data); 483 484 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); 485 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); 486 487 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); 488 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); 489 490 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); 491 492 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); 493 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); 494 495 int (*irq_nmi_setup)(struct irq_data *data); 496 void (*irq_nmi_teardown)(struct irq_data *data); 497 498 unsigned long flags; 499 }; 500 501 /* 502 * irq_chip specific flags 503 * 504 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() 505 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled 506 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path 507 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks 508 * when irq enabled 509 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip 510 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask 511 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode 512 * IRQCHIP_SUPPORTS_LEVEL_MSI Chip can provide two doorbells for Level MSIs 513 * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips 514 */ 515 enum { 516 IRQCHIP_SET_TYPE_MASKED = (1 << 0), 517 IRQCHIP_EOI_IF_HANDLED = (1 << 1), 518 IRQCHIP_MASK_ON_SUSPEND = (1 << 2), 519 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), 520 IRQCHIP_SKIP_SET_WAKE = (1 << 4), 521 IRQCHIP_ONESHOT_SAFE = (1 << 5), 522 IRQCHIP_EOI_THREADED = (1 << 6), 523 IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7), 524 IRQCHIP_SUPPORTS_NMI = (1 << 8), 525 }; 526 527 #include <linux/irqdesc.h> 528 529 /* 530 * Pick up the arch-dependent methods: 531 */ 532 #include <asm/hw_irq.h> 533 534 #ifndef NR_IRQS_LEGACY 535 # define NR_IRQS_LEGACY 0 536 #endif 537 538 #ifndef ARCH_IRQ_INIT_FLAGS 539 # define ARCH_IRQ_INIT_FLAGS 0 540 #endif 541 542 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS 543 544 struct irqaction; 545 extern int setup_irq(unsigned int irq, struct irqaction *new); 546 extern void remove_irq(unsigned int irq, struct irqaction *act); 547 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); 548 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); 549 550 extern void irq_cpu_online(void); 551 extern void irq_cpu_offline(void); 552 extern int irq_set_affinity_locked(struct irq_data *data, 553 const struct cpumask *cpumask, bool force); 554 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info); 555 556 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION) 557 extern void irq_migrate_all_off_this_cpu(void); 558 extern int irq_affinity_online_cpu(unsigned int cpu); 559 #else 560 # define irq_affinity_online_cpu NULL 561 #endif 562 563 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) 564 void __irq_move_irq(struct irq_data *data); 565 static inline void irq_move_irq(struct irq_data *data) 566 { 567 if (unlikely(irqd_is_setaffinity_pending(data))) 568 __irq_move_irq(data); 569 } 570 void irq_move_masked_irq(struct irq_data *data); 571 void irq_force_complete_move(struct irq_desc *desc); 572 #else 573 static inline void irq_move_irq(struct irq_data *data) { } 574 static inline void irq_move_masked_irq(struct irq_data *data) { } 575 static inline void irq_force_complete_move(struct irq_desc *desc) { } 576 #endif 577 578 extern int no_irq_affinity; 579 580 #ifdef CONFIG_HARDIRQS_SW_RESEND 581 int irq_set_parent(int irq, int parent_irq); 582 #else 583 static inline int irq_set_parent(int irq, int parent_irq) 584 { 585 return 0; 586 } 587 #endif 588 589 /* 590 * Built-in IRQ handlers for various IRQ types, 591 * callable via desc->handle_irq() 592 */ 593 extern void handle_level_irq(struct irq_desc *desc); 594 extern void handle_fasteoi_irq(struct irq_desc *desc); 595 extern void handle_edge_irq(struct irq_desc *desc); 596 extern void handle_edge_eoi_irq(struct irq_desc *desc); 597 extern void handle_simple_irq(struct irq_desc *desc); 598 extern void handle_untracked_irq(struct irq_desc *desc); 599 extern void handle_percpu_irq(struct irq_desc *desc); 600 extern void handle_percpu_devid_irq(struct irq_desc *desc); 601 extern void handle_bad_irq(struct irq_desc *desc); 602 extern void handle_nested_irq(unsigned int irq); 603 604 extern void handle_fasteoi_nmi(struct irq_desc *desc); 605 extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc); 606 607 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); 608 extern int irq_chip_pm_get(struct irq_data *data); 609 extern int irq_chip_pm_put(struct irq_data *data); 610 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 611 extern void handle_fasteoi_ack_irq(struct irq_desc *desc); 612 extern void handle_fasteoi_mask_irq(struct irq_desc *desc); 613 extern void irq_chip_enable_parent(struct irq_data *data); 614 extern void irq_chip_disable_parent(struct irq_data *data); 615 extern void irq_chip_ack_parent(struct irq_data *data); 616 extern int irq_chip_retrigger_hierarchy(struct irq_data *data); 617 extern void irq_chip_mask_parent(struct irq_data *data); 618 extern void irq_chip_mask_ack_parent(struct irq_data *data); 619 extern void irq_chip_unmask_parent(struct irq_data *data); 620 extern void irq_chip_eoi_parent(struct irq_data *data); 621 extern int irq_chip_set_affinity_parent(struct irq_data *data, 622 const struct cpumask *dest, 623 bool force); 624 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); 625 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, 626 void *vcpu_info); 627 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); 628 #endif 629 630 /* Handling of unhandled and spurious interrupts: */ 631 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret); 632 633 634 /* Enable/disable irq debugging output: */ 635 extern int noirqdebug_setup(char *str); 636 637 /* Checks whether the interrupt can be requested by request_irq(): */ 638 extern int can_request_irq(unsigned int irq, unsigned long irqflags); 639 640 /* Dummy irq-chip implementations: */ 641 extern struct irq_chip no_irq_chip; 642 extern struct irq_chip dummy_irq_chip; 643 644 extern void 645 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, 646 irq_flow_handler_t handle, const char *name); 647 648 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, 649 irq_flow_handler_t handle) 650 { 651 irq_set_chip_and_handler_name(irq, chip, handle, NULL); 652 } 653 654 extern int irq_set_percpu_devid(unsigned int irq); 655 extern int irq_set_percpu_devid_partition(unsigned int irq, 656 const struct cpumask *affinity); 657 extern int irq_get_percpu_devid_partition(unsigned int irq, 658 struct cpumask *affinity); 659 660 extern void 661 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, 662 const char *name); 663 664 static inline void 665 irq_set_handler(unsigned int irq, irq_flow_handler_t handle) 666 { 667 __irq_set_handler(irq, handle, 0, NULL); 668 } 669 670 /* 671 * Set a highlevel chained flow handler for a given IRQ. 672 * (a chained handler is automatically enabled and set to 673 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 674 */ 675 static inline void 676 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) 677 { 678 __irq_set_handler(irq, handle, 1, NULL); 679 } 680 681 /* 682 * Set a highlevel chained flow handler and its data for a given IRQ. 683 * (a chained handler is automatically enabled and set to 684 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 685 */ 686 void 687 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, 688 void *data); 689 690 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); 691 692 static inline void irq_set_status_flags(unsigned int irq, unsigned long set) 693 { 694 irq_modify_status(irq, 0, set); 695 } 696 697 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) 698 { 699 irq_modify_status(irq, clr, 0); 700 } 701 702 static inline void irq_set_noprobe(unsigned int irq) 703 { 704 irq_modify_status(irq, 0, IRQ_NOPROBE); 705 } 706 707 static inline void irq_set_probe(unsigned int irq) 708 { 709 irq_modify_status(irq, IRQ_NOPROBE, 0); 710 } 711 712 static inline void irq_set_nothread(unsigned int irq) 713 { 714 irq_modify_status(irq, 0, IRQ_NOTHREAD); 715 } 716 717 static inline void irq_set_thread(unsigned int irq) 718 { 719 irq_modify_status(irq, IRQ_NOTHREAD, 0); 720 } 721 722 static inline void irq_set_nested_thread(unsigned int irq, bool nest) 723 { 724 if (nest) 725 irq_set_status_flags(irq, IRQ_NESTED_THREAD); 726 else 727 irq_clear_status_flags(irq, IRQ_NESTED_THREAD); 728 } 729 730 static inline void irq_set_percpu_devid_flags(unsigned int irq) 731 { 732 irq_set_status_flags(irq, 733 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | 734 IRQ_NOPROBE | IRQ_PER_CPU_DEVID); 735 } 736 737 /* Set/get chip/data for an IRQ: */ 738 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); 739 extern int irq_set_handler_data(unsigned int irq, void *data); 740 extern int irq_set_chip_data(unsigned int irq, void *data); 741 extern int irq_set_irq_type(unsigned int irq, unsigned int type); 742 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 743 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, 744 struct msi_desc *entry); 745 extern struct irq_data *irq_get_irq_data(unsigned int irq); 746 747 static inline struct irq_chip *irq_get_chip(unsigned int irq) 748 { 749 struct irq_data *d = irq_get_irq_data(irq); 750 return d ? d->chip : NULL; 751 } 752 753 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) 754 { 755 return d->chip; 756 } 757 758 static inline void *irq_get_chip_data(unsigned int irq) 759 { 760 struct irq_data *d = irq_get_irq_data(irq); 761 return d ? d->chip_data : NULL; 762 } 763 764 static inline void *irq_data_get_irq_chip_data(struct irq_data *d) 765 { 766 return d->chip_data; 767 } 768 769 static inline void *irq_get_handler_data(unsigned int irq) 770 { 771 struct irq_data *d = irq_get_irq_data(irq); 772 return d ? d->common->handler_data : NULL; 773 } 774 775 static inline void *irq_data_get_irq_handler_data(struct irq_data *d) 776 { 777 return d->common->handler_data; 778 } 779 780 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) 781 { 782 struct irq_data *d = irq_get_irq_data(irq); 783 return d ? d->common->msi_desc : NULL; 784 } 785 786 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d) 787 { 788 return d->common->msi_desc; 789 } 790 791 static inline u32 irq_get_trigger_type(unsigned int irq) 792 { 793 struct irq_data *d = irq_get_irq_data(irq); 794 return d ? irqd_get_trigger_type(d) : 0; 795 } 796 797 static inline int irq_common_data_get_node(struct irq_common_data *d) 798 { 799 #ifdef CONFIG_NUMA 800 return d->node; 801 #else 802 return 0; 803 #endif 804 } 805 806 static inline int irq_data_get_node(struct irq_data *d) 807 { 808 return irq_common_data_get_node(d->common); 809 } 810 811 static inline struct cpumask *irq_get_affinity_mask(int irq) 812 { 813 struct irq_data *d = irq_get_irq_data(irq); 814 815 return d ? d->common->affinity : NULL; 816 } 817 818 static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d) 819 { 820 return d->common->affinity; 821 } 822 823 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 824 static inline 825 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 826 { 827 return d->common->effective_affinity; 828 } 829 static inline void irq_data_update_effective_affinity(struct irq_data *d, 830 const struct cpumask *m) 831 { 832 cpumask_copy(d->common->effective_affinity, m); 833 } 834 #else 835 static inline void irq_data_update_effective_affinity(struct irq_data *d, 836 const struct cpumask *m) 837 { 838 } 839 static inline 840 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 841 { 842 return d->common->affinity; 843 } 844 #endif 845 846 unsigned int arch_dynirq_lower_bound(unsigned int from); 847 848 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, 849 struct module *owner, 850 const struct irq_affinity_desc *affinity); 851 852 int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from, 853 unsigned int cnt, int node, struct module *owner, 854 const struct irq_affinity_desc *affinity); 855 856 /* use macros to avoid needing export.h for THIS_MODULE */ 857 #define irq_alloc_descs(irq, from, cnt, node) \ 858 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL) 859 860 #define irq_alloc_desc(node) \ 861 irq_alloc_descs(-1, 0, 1, node) 862 863 #define irq_alloc_desc_at(at, node) \ 864 irq_alloc_descs(at, at, 1, node) 865 866 #define irq_alloc_desc_from(from, node) \ 867 irq_alloc_descs(-1, from, 1, node) 868 869 #define irq_alloc_descs_from(from, cnt, node) \ 870 irq_alloc_descs(-1, from, cnt, node) 871 872 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \ 873 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL) 874 875 #define devm_irq_alloc_desc(dev, node) \ 876 devm_irq_alloc_descs(dev, -1, 0, 1, node) 877 878 #define devm_irq_alloc_desc_at(dev, at, node) \ 879 devm_irq_alloc_descs(dev, at, at, 1, node) 880 881 #define devm_irq_alloc_desc_from(dev, from, node) \ 882 devm_irq_alloc_descs(dev, -1, from, 1, node) 883 884 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \ 885 devm_irq_alloc_descs(dev, -1, from, cnt, node) 886 887 void irq_free_descs(unsigned int irq, unsigned int cnt); 888 static inline void irq_free_desc(unsigned int irq) 889 { 890 irq_free_descs(irq, 1); 891 } 892 893 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ 894 unsigned int irq_alloc_hwirqs(int cnt, int node); 895 static inline unsigned int irq_alloc_hwirq(int node) 896 { 897 return irq_alloc_hwirqs(1, node); 898 } 899 void irq_free_hwirqs(unsigned int from, int cnt); 900 static inline void irq_free_hwirq(unsigned int irq) 901 { 902 return irq_free_hwirqs(irq, 1); 903 } 904 int arch_setup_hwirq(unsigned int irq, int node); 905 void arch_teardown_hwirq(unsigned int irq); 906 #endif 907 908 #ifdef CONFIG_GENERIC_IRQ_LEGACY 909 void irq_init_desc(unsigned int irq); 910 #endif 911 912 /** 913 * struct irq_chip_regs - register offsets for struct irq_gci 914 * @enable: Enable register offset to reg_base 915 * @disable: Disable register offset to reg_base 916 * @mask: Mask register offset to reg_base 917 * @ack: Ack register offset to reg_base 918 * @eoi: Eoi register offset to reg_base 919 * @type: Type configuration register offset to reg_base 920 * @polarity: Polarity configuration register offset to reg_base 921 */ 922 struct irq_chip_regs { 923 unsigned long enable; 924 unsigned long disable; 925 unsigned long mask; 926 unsigned long ack; 927 unsigned long eoi; 928 unsigned long type; 929 unsigned long polarity; 930 }; 931 932 /** 933 * struct irq_chip_type - Generic interrupt chip instance for a flow type 934 * @chip: The real interrupt chip which provides the callbacks 935 * @regs: Register offsets for this chip 936 * @handler: Flow handler associated with this chip 937 * @type: Chip can handle these flow types 938 * @mask_cache_priv: Cached mask register private to the chip type 939 * @mask_cache: Pointer to cached mask register 940 * 941 * A irq_generic_chip can have several instances of irq_chip_type when 942 * it requires different functions and register offsets for different 943 * flow types. 944 */ 945 struct irq_chip_type { 946 struct irq_chip chip; 947 struct irq_chip_regs regs; 948 irq_flow_handler_t handler; 949 u32 type; 950 u32 mask_cache_priv; 951 u32 *mask_cache; 952 }; 953 954 /** 955 * struct irq_chip_generic - Generic irq chip data structure 956 * @lock: Lock to protect register and cache data access 957 * @reg_base: Register base address (virtual) 958 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL) 959 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL) 960 * @suspend: Function called from core code on suspend once per 961 * chip; can be useful instead of irq_chip::suspend to 962 * handle chip details even when no interrupts are in use 963 * @resume: Function called from core code on resume once per chip; 964 * can be useful instead of irq_chip::suspend to handle 965 * chip details even when no interrupts are in use 966 * @irq_base: Interrupt base nr for this chip 967 * @irq_cnt: Number of interrupts handled by this chip 968 * @mask_cache: Cached mask register shared between all chip types 969 * @type_cache: Cached type register 970 * @polarity_cache: Cached polarity register 971 * @wake_enabled: Interrupt can wakeup from suspend 972 * @wake_active: Interrupt is marked as an wakeup from suspend source 973 * @num_ct: Number of available irq_chip_type instances (usually 1) 974 * @private: Private data for non generic chip callbacks 975 * @installed: bitfield to denote installed interrupts 976 * @unused: bitfield to denote unused interrupts 977 * @domain: irq domain pointer 978 * @list: List head for keeping track of instances 979 * @chip_types: Array of interrupt irq_chip_types 980 * 981 * Note, that irq_chip_generic can have multiple irq_chip_type 982 * implementations which can be associated to a particular irq line of 983 * an irq_chip_generic instance. That allows to share and protect 984 * state in an irq_chip_generic instance when we need to implement 985 * different flow mechanisms (level/edge) for it. 986 */ 987 struct irq_chip_generic { 988 raw_spinlock_t lock; 989 void __iomem *reg_base; 990 u32 (*reg_readl)(void __iomem *addr); 991 void (*reg_writel)(u32 val, void __iomem *addr); 992 void (*suspend)(struct irq_chip_generic *gc); 993 void (*resume)(struct irq_chip_generic *gc); 994 unsigned int irq_base; 995 unsigned int irq_cnt; 996 u32 mask_cache; 997 u32 type_cache; 998 u32 polarity_cache; 999 u32 wake_enabled; 1000 u32 wake_active; 1001 unsigned int num_ct; 1002 void *private; 1003 unsigned long installed; 1004 unsigned long unused; 1005 struct irq_domain *domain; 1006 struct list_head list; 1007 struct irq_chip_type chip_types[0]; 1008 }; 1009 1010 /** 1011 * enum irq_gc_flags - Initialization flags for generic irq chips 1012 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg 1013 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for 1014 * irq chips which need to call irq_set_wake() on 1015 * the parent irq. Usually GPIO implementations 1016 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private 1017 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask 1018 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE) 1019 */ 1020 enum irq_gc_flags { 1021 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 1022 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 1023 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, 1024 IRQ_GC_NO_MASK = 1 << 3, 1025 IRQ_GC_BE_IO = 1 << 4, 1026 }; 1027 1028 /* 1029 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains 1030 * @irqs_per_chip: Number of interrupts per chip 1031 * @num_chips: Number of chips 1032 * @irq_flags_to_set: IRQ* flags to set on irq setup 1033 * @irq_flags_to_clear: IRQ* flags to clear on irq setup 1034 * @gc_flags: Generic chip specific setup flags 1035 * @gc: Array of pointers to generic interrupt chips 1036 */ 1037 struct irq_domain_chip_generic { 1038 unsigned int irqs_per_chip; 1039 unsigned int num_chips; 1040 unsigned int irq_flags_to_clear; 1041 unsigned int irq_flags_to_set; 1042 enum irq_gc_flags gc_flags; 1043 struct irq_chip_generic *gc[0]; 1044 }; 1045 1046 /* Generic chip callback functions */ 1047 void irq_gc_noop(struct irq_data *d); 1048 void irq_gc_mask_disable_reg(struct irq_data *d); 1049 void irq_gc_mask_set_bit(struct irq_data *d); 1050 void irq_gc_mask_clr_bit(struct irq_data *d); 1051 void irq_gc_unmask_enable_reg(struct irq_data *d); 1052 void irq_gc_ack_set_bit(struct irq_data *d); 1053 void irq_gc_ack_clr_bit(struct irq_data *d); 1054 void irq_gc_mask_disable_and_ack_set(struct irq_data *d); 1055 void irq_gc_eoi(struct irq_data *d); 1056 int irq_gc_set_wake(struct irq_data *d, unsigned int on); 1057 1058 /* Setup functions for irq_chip_generic */ 1059 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, 1060 irq_hw_number_t hw_irq); 1061 struct irq_chip_generic * 1062 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, 1063 void __iomem *reg_base, irq_flow_handler_t handler); 1064 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 1065 enum irq_gc_flags flags, unsigned int clr, 1066 unsigned int set); 1067 int irq_setup_alt_chip(struct irq_data *d, unsigned int type); 1068 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 1069 unsigned int clr, unsigned int set); 1070 1071 struct irq_chip_generic * 1072 devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct, 1073 unsigned int irq_base, void __iomem *reg_base, 1074 irq_flow_handler_t handler); 1075 int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc, 1076 u32 msk, enum irq_gc_flags flags, 1077 unsigned int clr, unsigned int set); 1078 1079 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); 1080 1081 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, 1082 int num_ct, const char *name, 1083 irq_flow_handler_t handler, 1084 unsigned int clr, unsigned int set, 1085 enum irq_gc_flags flags); 1086 1087 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \ 1088 handler, clr, set, flags) \ 1089 ({ \ 1090 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \ 1091 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\ 1092 handler, clr, set, flags); \ 1093 }) 1094 1095 static inline void irq_free_generic_chip(struct irq_chip_generic *gc) 1096 { 1097 kfree(gc); 1098 } 1099 1100 static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc, 1101 u32 msk, unsigned int clr, 1102 unsigned int set) 1103 { 1104 irq_remove_generic_chip(gc, msk, clr, set); 1105 irq_free_generic_chip(gc); 1106 } 1107 1108 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) 1109 { 1110 return container_of(d->chip, struct irq_chip_type, chip); 1111 } 1112 1113 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) 1114 1115 #ifdef CONFIG_SMP 1116 static inline void irq_gc_lock(struct irq_chip_generic *gc) 1117 { 1118 raw_spin_lock(&gc->lock); 1119 } 1120 1121 static inline void irq_gc_unlock(struct irq_chip_generic *gc) 1122 { 1123 raw_spin_unlock(&gc->lock); 1124 } 1125 #else 1126 static inline void irq_gc_lock(struct irq_chip_generic *gc) { } 1127 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } 1128 #endif 1129 1130 /* 1131 * The irqsave variants are for usage in non interrupt code. Do not use 1132 * them in irq_chip callbacks. Use irq_gc_lock() instead. 1133 */ 1134 #define irq_gc_lock_irqsave(gc, flags) \ 1135 raw_spin_lock_irqsave(&(gc)->lock, flags) 1136 1137 #define irq_gc_unlock_irqrestore(gc, flags) \ 1138 raw_spin_unlock_irqrestore(&(gc)->lock, flags) 1139 1140 static inline void irq_reg_writel(struct irq_chip_generic *gc, 1141 u32 val, int reg_offset) 1142 { 1143 if (gc->reg_writel) 1144 gc->reg_writel(val, gc->reg_base + reg_offset); 1145 else 1146 writel(val, gc->reg_base + reg_offset); 1147 } 1148 1149 static inline u32 irq_reg_readl(struct irq_chip_generic *gc, 1150 int reg_offset) 1151 { 1152 if (gc->reg_readl) 1153 return gc->reg_readl(gc->reg_base + reg_offset); 1154 else 1155 return readl(gc->reg_base + reg_offset); 1156 } 1157 1158 struct irq_matrix; 1159 struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits, 1160 unsigned int alloc_start, 1161 unsigned int alloc_end); 1162 void irq_matrix_online(struct irq_matrix *m); 1163 void irq_matrix_offline(struct irq_matrix *m); 1164 void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace); 1165 int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk); 1166 void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk); 1167 int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk, 1168 unsigned int *mapped_cpu); 1169 void irq_matrix_reserve(struct irq_matrix *m); 1170 void irq_matrix_remove_reserved(struct irq_matrix *m); 1171 int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk, 1172 bool reserved, unsigned int *mapped_cpu); 1173 void irq_matrix_free(struct irq_matrix *m, unsigned int cpu, 1174 unsigned int bit, bool managed); 1175 void irq_matrix_assign(struct irq_matrix *m, unsigned int bit); 1176 unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown); 1177 unsigned int irq_matrix_allocated(struct irq_matrix *m); 1178 unsigned int irq_matrix_reserved(struct irq_matrix *m); 1179 void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind); 1180 1181 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */ 1182 #define INVALID_HWIRQ (~0UL) 1183 irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu); 1184 int __ipi_send_single(struct irq_desc *desc, unsigned int cpu); 1185 int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest); 1186 int ipi_send_single(unsigned int virq, unsigned int cpu); 1187 int ipi_send_mask(unsigned int virq, const struct cpumask *dest); 1188 1189 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER 1190 /* 1191 * Registers a generic IRQ handling function as the top-level IRQ handler in 1192 * the system, which is generally the first C code called from an assembly 1193 * architecture-specific interrupt handler. 1194 * 1195 * Returns 0 on success, or -EBUSY if an IRQ handler has already been 1196 * registered. 1197 */ 1198 int __init set_handle_irq(void (*handle_irq)(struct pt_regs *)); 1199 1200 /* 1201 * Allows interrupt handlers to find the irqchip that's been registered as the 1202 * top-level IRQ handler. 1203 */ 1204 extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init; 1205 #endif 1206 1207 #endif /* _LINUX_IRQ_H */ 1208