1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_IRQ_H 3 #define _LINUX_IRQ_H 4 5 /* 6 * Please do not include this file in generic code. There is currently 7 * no requirement for any architecture to implement anything held 8 * within this file. 9 * 10 * Thanks. --rmk 11 */ 12 13 #include <linux/cache.h> 14 #include <linux/spinlock.h> 15 #include <linux/cpumask.h> 16 #include <linux/irqhandler.h> 17 #include <linux/irqreturn.h> 18 #include <linux/irqnr.h> 19 #include <linux/topology.h> 20 #include <linux/io.h> 21 #include <linux/slab.h> 22 23 #include <asm/irq.h> 24 #include <asm/ptrace.h> 25 #include <asm/irq_regs.h> 26 27 struct seq_file; 28 struct module; 29 struct msi_msg; 30 enum irqchip_irq_state; 31 32 /* 33 * IRQ line status. 34 * 35 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h 36 * 37 * IRQ_TYPE_NONE - default, unspecified type 38 * IRQ_TYPE_EDGE_RISING - rising edge triggered 39 * IRQ_TYPE_EDGE_FALLING - falling edge triggered 40 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 41 * IRQ_TYPE_LEVEL_HIGH - high level triggered 42 * IRQ_TYPE_LEVEL_LOW - low level triggered 43 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 44 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits 45 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type 46 * to setup the HW to a sane default (used 47 * by irqdomain map() callbacks to synchronize 48 * the HW state and SW flags for a newly 49 * allocated descriptor). 50 * 51 * IRQ_TYPE_PROBE - Special flag for probing in progress 52 * 53 * Bits which can be modified via irq_set/clear/modify_status_flags() 54 * IRQ_LEVEL - Interrupt is level type. Will be also 55 * updated in the code when the above trigger 56 * bits are modified via irq_set_irq_type() 57 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect 58 * it from affinity setting 59 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing 60 * IRQ_NOREQUEST - Interrupt cannot be requested via 61 * request_irq() 62 * IRQ_NOTHREAD - Interrupt cannot be threaded 63 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in 64 * request/setup_irq() 65 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) 66 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context 67 * IRQ_NESTED_THREAD - Interrupt nests into another thread 68 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable 69 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude 70 * it from the spurious interrupt detection 71 * mechanism and from core side polling. 72 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable 73 */ 74 enum { 75 IRQ_TYPE_NONE = 0x00000000, 76 IRQ_TYPE_EDGE_RISING = 0x00000001, 77 IRQ_TYPE_EDGE_FALLING = 0x00000002, 78 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), 79 IRQ_TYPE_LEVEL_HIGH = 0x00000004, 80 IRQ_TYPE_LEVEL_LOW = 0x00000008, 81 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), 82 IRQ_TYPE_SENSE_MASK = 0x0000000f, 83 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, 84 85 IRQ_TYPE_PROBE = 0x00000010, 86 87 IRQ_LEVEL = (1 << 8), 88 IRQ_PER_CPU = (1 << 9), 89 IRQ_NOPROBE = (1 << 10), 90 IRQ_NOREQUEST = (1 << 11), 91 IRQ_NOAUTOEN = (1 << 12), 92 IRQ_NO_BALANCING = (1 << 13), 93 IRQ_MOVE_PCNTXT = (1 << 14), 94 IRQ_NESTED_THREAD = (1 << 15), 95 IRQ_NOTHREAD = (1 << 16), 96 IRQ_PER_CPU_DEVID = (1 << 17), 97 IRQ_IS_POLLED = (1 << 18), 98 IRQ_DISABLE_UNLAZY = (1 << 19), 99 }; 100 101 #define IRQF_MODIFY_MASK \ 102 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ 103 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ 104 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ 105 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY) 106 107 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 108 109 /* 110 * Return value for chip->irq_set_affinity() 111 * 112 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity 113 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity 114 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to 115 * support stacked irqchips, which indicates skipping 116 * all descendent irqchips. 117 */ 118 enum { 119 IRQ_SET_MASK_OK = 0, 120 IRQ_SET_MASK_OK_NOCOPY, 121 IRQ_SET_MASK_OK_DONE, 122 }; 123 124 struct msi_desc; 125 struct irq_domain; 126 127 /** 128 * struct irq_common_data - per irq data shared by all irqchips 129 * @state_use_accessors: status information for irq chip functions. 130 * Use accessor functions to deal with it 131 * @node: node index useful for balancing 132 * @handler_data: per-IRQ data for the irq_chip methods 133 * @affinity: IRQ affinity on SMP. If this is an IPI 134 * related irq, then this is the mask of the 135 * CPUs to which an IPI can be sent. 136 * @effective_affinity: The effective IRQ affinity on SMP as some irq 137 * chips do not allow multi CPU destinations. 138 * A subset of @affinity. 139 * @msi_desc: MSI descriptor 140 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional. 141 */ 142 struct irq_common_data { 143 unsigned int __private state_use_accessors; 144 #ifdef CONFIG_NUMA 145 unsigned int node; 146 #endif 147 void *handler_data; 148 struct msi_desc *msi_desc; 149 cpumask_var_t affinity; 150 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 151 cpumask_var_t effective_affinity; 152 #endif 153 #ifdef CONFIG_GENERIC_IRQ_IPI 154 unsigned int ipi_offset; 155 #endif 156 }; 157 158 /** 159 * struct irq_data - per irq chip data passed down to chip functions 160 * @mask: precomputed bitmask for accessing the chip registers 161 * @irq: interrupt number 162 * @hwirq: hardware interrupt number, local to the interrupt domain 163 * @common: point to data shared by all irqchips 164 * @chip: low level interrupt hardware access 165 * @domain: Interrupt translation domain; responsible for mapping 166 * between hwirq number and linux irq number. 167 * @parent_data: pointer to parent struct irq_data to support hierarchy 168 * irq_domain 169 * @chip_data: platform-specific per-chip private data for the chip 170 * methods, to allow shared chip implementations 171 */ 172 struct irq_data { 173 u32 mask; 174 unsigned int irq; 175 unsigned long hwirq; 176 struct irq_common_data *common; 177 struct irq_chip *chip; 178 struct irq_domain *domain; 179 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 180 struct irq_data *parent_data; 181 #endif 182 void *chip_data; 183 }; 184 185 /* 186 * Bit masks for irq_common_data.state_use_accessors 187 * 188 * IRQD_TRIGGER_MASK - Mask for the trigger type bits 189 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 190 * IRQD_ACTIVATED - Interrupt has already been activated 191 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 192 * IRQD_PER_CPU - Interrupt is per cpu 193 * IRQD_AFFINITY_SET - Interrupt affinity was set 194 * IRQD_LEVEL - Interrupt is level triggered 195 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup 196 * from suspend 197 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process 198 * context 199 * IRQD_IRQ_DISABLED - Disabled state of the interrupt 200 * IRQD_IRQ_MASKED - Masked state of the interrupt 201 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt 202 * IRQD_WAKEUP_ARMED - Wakeup mode armed 203 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU 204 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel 205 * IRQD_IRQ_STARTED - Startup state of the interrupt 206 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity 207 * mask. Applies only to affinity managed irqs. 208 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target 209 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set 210 * IRQD_CAN_RESERVE - Can use reservation mode 211 */ 212 enum { 213 IRQD_TRIGGER_MASK = 0xf, 214 IRQD_SETAFFINITY_PENDING = (1 << 8), 215 IRQD_ACTIVATED = (1 << 9), 216 IRQD_NO_BALANCING = (1 << 10), 217 IRQD_PER_CPU = (1 << 11), 218 IRQD_AFFINITY_SET = (1 << 12), 219 IRQD_LEVEL = (1 << 13), 220 IRQD_WAKEUP_STATE = (1 << 14), 221 IRQD_MOVE_PCNTXT = (1 << 15), 222 IRQD_IRQ_DISABLED = (1 << 16), 223 IRQD_IRQ_MASKED = (1 << 17), 224 IRQD_IRQ_INPROGRESS = (1 << 18), 225 IRQD_WAKEUP_ARMED = (1 << 19), 226 IRQD_FORWARDED_TO_VCPU = (1 << 20), 227 IRQD_AFFINITY_MANAGED = (1 << 21), 228 IRQD_IRQ_STARTED = (1 << 22), 229 IRQD_MANAGED_SHUTDOWN = (1 << 23), 230 IRQD_SINGLE_TARGET = (1 << 24), 231 IRQD_DEFAULT_TRIGGER_SET = (1 << 25), 232 IRQD_CAN_RESERVE = (1 << 26), 233 }; 234 235 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors) 236 237 static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 238 { 239 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING; 240 } 241 242 static inline bool irqd_is_per_cpu(struct irq_data *d) 243 { 244 return __irqd_to_state(d) & IRQD_PER_CPU; 245 } 246 247 static inline bool irqd_can_balance(struct irq_data *d) 248 { 249 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); 250 } 251 252 static inline bool irqd_affinity_was_set(struct irq_data *d) 253 { 254 return __irqd_to_state(d) & IRQD_AFFINITY_SET; 255 } 256 257 static inline void irqd_mark_affinity_was_set(struct irq_data *d) 258 { 259 __irqd_to_state(d) |= IRQD_AFFINITY_SET; 260 } 261 262 static inline bool irqd_trigger_type_was_set(struct irq_data *d) 263 { 264 return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET; 265 } 266 267 static inline u32 irqd_get_trigger_type(struct irq_data *d) 268 { 269 return __irqd_to_state(d) & IRQD_TRIGGER_MASK; 270 } 271 272 /* 273 * Must only be called inside irq_chip.irq_set_type() functions or 274 * from the DT/ACPI setup code. 275 */ 276 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) 277 { 278 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK; 279 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK; 280 __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET; 281 } 282 283 static inline bool irqd_is_level_type(struct irq_data *d) 284 { 285 return __irqd_to_state(d) & IRQD_LEVEL; 286 } 287 288 /* 289 * Must only be called of irqchip.irq_set_affinity() or low level 290 * hieararchy domain allocation functions. 291 */ 292 static inline void irqd_set_single_target(struct irq_data *d) 293 { 294 __irqd_to_state(d) |= IRQD_SINGLE_TARGET; 295 } 296 297 static inline bool irqd_is_single_target(struct irq_data *d) 298 { 299 return __irqd_to_state(d) & IRQD_SINGLE_TARGET; 300 } 301 302 static inline bool irqd_is_wakeup_set(struct irq_data *d) 303 { 304 return __irqd_to_state(d) & IRQD_WAKEUP_STATE; 305 } 306 307 static inline bool irqd_can_move_in_process_context(struct irq_data *d) 308 { 309 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT; 310 } 311 312 static inline bool irqd_irq_disabled(struct irq_data *d) 313 { 314 return __irqd_to_state(d) & IRQD_IRQ_DISABLED; 315 } 316 317 static inline bool irqd_irq_masked(struct irq_data *d) 318 { 319 return __irqd_to_state(d) & IRQD_IRQ_MASKED; 320 } 321 322 static inline bool irqd_irq_inprogress(struct irq_data *d) 323 { 324 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; 325 } 326 327 static inline bool irqd_is_wakeup_armed(struct irq_data *d) 328 { 329 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED; 330 } 331 332 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d) 333 { 334 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU; 335 } 336 337 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d) 338 { 339 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU; 340 } 341 342 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d) 343 { 344 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; 345 } 346 347 static inline bool irqd_affinity_is_managed(struct irq_data *d) 348 { 349 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED; 350 } 351 352 static inline bool irqd_is_activated(struct irq_data *d) 353 { 354 return __irqd_to_state(d) & IRQD_ACTIVATED; 355 } 356 357 static inline void irqd_set_activated(struct irq_data *d) 358 { 359 __irqd_to_state(d) |= IRQD_ACTIVATED; 360 } 361 362 static inline void irqd_clr_activated(struct irq_data *d) 363 { 364 __irqd_to_state(d) &= ~IRQD_ACTIVATED; 365 } 366 367 static inline bool irqd_is_started(struct irq_data *d) 368 { 369 return __irqd_to_state(d) & IRQD_IRQ_STARTED; 370 } 371 372 static inline bool irqd_is_managed_and_shutdown(struct irq_data *d) 373 { 374 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN; 375 } 376 377 static inline void irqd_set_can_reserve(struct irq_data *d) 378 { 379 __irqd_to_state(d) |= IRQD_CAN_RESERVE; 380 } 381 382 static inline void irqd_clr_can_reserve(struct irq_data *d) 383 { 384 __irqd_to_state(d) &= ~IRQD_CAN_RESERVE; 385 } 386 387 static inline bool irqd_can_reserve(struct irq_data *d) 388 { 389 return __irqd_to_state(d) & IRQD_CAN_RESERVE; 390 } 391 392 #undef __irqd_to_state 393 394 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) 395 { 396 return d->hwirq; 397 } 398 399 /** 400 * struct irq_chip - hardware interrupt chip descriptor 401 * 402 * @parent_device: pointer to parent device for irqchip 403 * @name: name for /proc/interrupts 404 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 405 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 406 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) 407 * @irq_disable: disable the interrupt 408 * @irq_ack: start of a new interrupt 409 * @irq_mask: mask an interrupt source 410 * @irq_mask_ack: ack and mask an interrupt source 411 * @irq_unmask: unmask an interrupt source 412 * @irq_eoi: end of interrupt 413 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force 414 * argument is true, it tells the driver to 415 * unconditionally apply the affinity setting. Sanity 416 * checks against the supplied affinity mask are not 417 * required. This is used for CPU hotplug where the 418 * target CPU is not yet set in the cpu_online_mask. 419 * @irq_retrigger: resend an IRQ to the CPU 420 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ 421 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 422 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 423 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 424 * @irq_cpu_online: configure an interrupt source for a secondary CPU 425 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU 426 * @irq_suspend: function called from core code on suspend once per 427 * chip, when one or more interrupts are installed 428 * @irq_resume: function called from core code on resume once per chip, 429 * when one ore more interrupts are installed 430 * @irq_pm_shutdown: function called from core code on shutdown once per chip 431 * @irq_calc_mask: Optional function to set irq_data.mask for special cases 432 * @irq_print_chip: optional to print special chip info in show_interrupts 433 * @irq_request_resources: optional to request resources before calling 434 * any other callback related to this irq 435 * @irq_release_resources: optional to release resources acquired with 436 * irq_request_resources 437 * @irq_compose_msi_msg: optional to compose message content for MSI 438 * @irq_write_msi_msg: optional to write message content for MSI 439 * @irq_get_irqchip_state: return the internal state of an interrupt 440 * @irq_set_irqchip_state: set the internal state of a interrupt 441 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine 442 * @ipi_send_single: send a single IPI to destination cpus 443 * @ipi_send_mask: send an IPI to destination cpus in cpumask 444 * @flags: chip specific flags 445 */ 446 struct irq_chip { 447 struct device *parent_device; 448 const char *name; 449 unsigned int (*irq_startup)(struct irq_data *data); 450 void (*irq_shutdown)(struct irq_data *data); 451 void (*irq_enable)(struct irq_data *data); 452 void (*irq_disable)(struct irq_data *data); 453 454 void (*irq_ack)(struct irq_data *data); 455 void (*irq_mask)(struct irq_data *data); 456 void (*irq_mask_ack)(struct irq_data *data); 457 void (*irq_unmask)(struct irq_data *data); 458 void (*irq_eoi)(struct irq_data *data); 459 460 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); 461 int (*irq_retrigger)(struct irq_data *data); 462 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); 463 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 464 465 void (*irq_bus_lock)(struct irq_data *data); 466 void (*irq_bus_sync_unlock)(struct irq_data *data); 467 468 void (*irq_cpu_online)(struct irq_data *data); 469 void (*irq_cpu_offline)(struct irq_data *data); 470 471 void (*irq_suspend)(struct irq_data *data); 472 void (*irq_resume)(struct irq_data *data); 473 void (*irq_pm_shutdown)(struct irq_data *data); 474 475 void (*irq_calc_mask)(struct irq_data *data); 476 477 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 478 int (*irq_request_resources)(struct irq_data *data); 479 void (*irq_release_resources)(struct irq_data *data); 480 481 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); 482 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); 483 484 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); 485 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); 486 487 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); 488 489 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); 490 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); 491 492 unsigned long flags; 493 }; 494 495 /* 496 * irq_chip specific flags 497 * 498 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() 499 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled 500 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path 501 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks 502 * when irq enabled 503 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip 504 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask 505 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode 506 */ 507 enum { 508 IRQCHIP_SET_TYPE_MASKED = (1 << 0), 509 IRQCHIP_EOI_IF_HANDLED = (1 << 1), 510 IRQCHIP_MASK_ON_SUSPEND = (1 << 2), 511 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), 512 IRQCHIP_SKIP_SET_WAKE = (1 << 4), 513 IRQCHIP_ONESHOT_SAFE = (1 << 5), 514 IRQCHIP_EOI_THREADED = (1 << 6), 515 }; 516 517 #include <linux/irqdesc.h> 518 519 /* 520 * Pick up the arch-dependent methods: 521 */ 522 #include <asm/hw_irq.h> 523 524 #ifndef NR_IRQS_LEGACY 525 # define NR_IRQS_LEGACY 0 526 #endif 527 528 #ifndef ARCH_IRQ_INIT_FLAGS 529 # define ARCH_IRQ_INIT_FLAGS 0 530 #endif 531 532 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS 533 534 struct irqaction; 535 extern int setup_irq(unsigned int irq, struct irqaction *new); 536 extern void remove_irq(unsigned int irq, struct irqaction *act); 537 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); 538 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); 539 540 extern void irq_cpu_online(void); 541 extern void irq_cpu_offline(void); 542 extern int irq_set_affinity_locked(struct irq_data *data, 543 const struct cpumask *cpumask, bool force); 544 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info); 545 546 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION) 547 extern void irq_migrate_all_off_this_cpu(void); 548 extern int irq_affinity_online_cpu(unsigned int cpu); 549 #else 550 # define irq_affinity_online_cpu NULL 551 #endif 552 553 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) 554 void irq_move_irq(struct irq_data *data); 555 void irq_move_masked_irq(struct irq_data *data); 556 void irq_force_complete_move(struct irq_desc *desc); 557 #else 558 static inline void irq_move_irq(struct irq_data *data) { } 559 static inline void irq_move_masked_irq(struct irq_data *data) { } 560 static inline void irq_force_complete_move(struct irq_desc *desc) { } 561 #endif 562 563 extern int no_irq_affinity; 564 565 #ifdef CONFIG_HARDIRQS_SW_RESEND 566 int irq_set_parent(int irq, int parent_irq); 567 #else 568 static inline int irq_set_parent(int irq, int parent_irq) 569 { 570 return 0; 571 } 572 #endif 573 574 /* 575 * Built-in IRQ handlers for various IRQ types, 576 * callable via desc->handle_irq() 577 */ 578 extern void handle_level_irq(struct irq_desc *desc); 579 extern void handle_fasteoi_irq(struct irq_desc *desc); 580 extern void handle_edge_irq(struct irq_desc *desc); 581 extern void handle_edge_eoi_irq(struct irq_desc *desc); 582 extern void handle_simple_irq(struct irq_desc *desc); 583 extern void handle_untracked_irq(struct irq_desc *desc); 584 extern void handle_percpu_irq(struct irq_desc *desc); 585 extern void handle_percpu_devid_irq(struct irq_desc *desc); 586 extern void handle_bad_irq(struct irq_desc *desc); 587 extern void handle_nested_irq(unsigned int irq); 588 589 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); 590 extern int irq_chip_pm_get(struct irq_data *data); 591 extern int irq_chip_pm_put(struct irq_data *data); 592 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 593 extern void handle_fasteoi_ack_irq(struct irq_desc *desc); 594 extern void handle_fasteoi_mask_irq(struct irq_desc *desc); 595 extern void irq_chip_enable_parent(struct irq_data *data); 596 extern void irq_chip_disable_parent(struct irq_data *data); 597 extern void irq_chip_ack_parent(struct irq_data *data); 598 extern int irq_chip_retrigger_hierarchy(struct irq_data *data); 599 extern void irq_chip_mask_parent(struct irq_data *data); 600 extern void irq_chip_unmask_parent(struct irq_data *data); 601 extern void irq_chip_eoi_parent(struct irq_data *data); 602 extern int irq_chip_set_affinity_parent(struct irq_data *data, 603 const struct cpumask *dest, 604 bool force); 605 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); 606 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, 607 void *vcpu_info); 608 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); 609 #endif 610 611 /* Handling of unhandled and spurious interrupts: */ 612 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret); 613 614 615 /* Enable/disable irq debugging output: */ 616 extern int noirqdebug_setup(char *str); 617 618 /* Checks whether the interrupt can be requested by request_irq(): */ 619 extern int can_request_irq(unsigned int irq, unsigned long irqflags); 620 621 /* Dummy irq-chip implementations: */ 622 extern struct irq_chip no_irq_chip; 623 extern struct irq_chip dummy_irq_chip; 624 625 extern void 626 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, 627 irq_flow_handler_t handle, const char *name); 628 629 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, 630 irq_flow_handler_t handle) 631 { 632 irq_set_chip_and_handler_name(irq, chip, handle, NULL); 633 } 634 635 extern int irq_set_percpu_devid(unsigned int irq); 636 extern int irq_set_percpu_devid_partition(unsigned int irq, 637 const struct cpumask *affinity); 638 extern int irq_get_percpu_devid_partition(unsigned int irq, 639 struct cpumask *affinity); 640 641 extern void 642 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, 643 const char *name); 644 645 static inline void 646 irq_set_handler(unsigned int irq, irq_flow_handler_t handle) 647 { 648 __irq_set_handler(irq, handle, 0, NULL); 649 } 650 651 /* 652 * Set a highlevel chained flow handler for a given IRQ. 653 * (a chained handler is automatically enabled and set to 654 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 655 */ 656 static inline void 657 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) 658 { 659 __irq_set_handler(irq, handle, 1, NULL); 660 } 661 662 /* 663 * Set a highlevel chained flow handler and its data for a given IRQ. 664 * (a chained handler is automatically enabled and set to 665 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 666 */ 667 void 668 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, 669 void *data); 670 671 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); 672 673 static inline void irq_set_status_flags(unsigned int irq, unsigned long set) 674 { 675 irq_modify_status(irq, 0, set); 676 } 677 678 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) 679 { 680 irq_modify_status(irq, clr, 0); 681 } 682 683 static inline void irq_set_noprobe(unsigned int irq) 684 { 685 irq_modify_status(irq, 0, IRQ_NOPROBE); 686 } 687 688 static inline void irq_set_probe(unsigned int irq) 689 { 690 irq_modify_status(irq, IRQ_NOPROBE, 0); 691 } 692 693 static inline void irq_set_nothread(unsigned int irq) 694 { 695 irq_modify_status(irq, 0, IRQ_NOTHREAD); 696 } 697 698 static inline void irq_set_thread(unsigned int irq) 699 { 700 irq_modify_status(irq, IRQ_NOTHREAD, 0); 701 } 702 703 static inline void irq_set_nested_thread(unsigned int irq, bool nest) 704 { 705 if (nest) 706 irq_set_status_flags(irq, IRQ_NESTED_THREAD); 707 else 708 irq_clear_status_flags(irq, IRQ_NESTED_THREAD); 709 } 710 711 static inline void irq_set_percpu_devid_flags(unsigned int irq) 712 { 713 irq_set_status_flags(irq, 714 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | 715 IRQ_NOPROBE | IRQ_PER_CPU_DEVID); 716 } 717 718 /* Set/get chip/data for an IRQ: */ 719 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); 720 extern int irq_set_handler_data(unsigned int irq, void *data); 721 extern int irq_set_chip_data(unsigned int irq, void *data); 722 extern int irq_set_irq_type(unsigned int irq, unsigned int type); 723 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 724 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, 725 struct msi_desc *entry); 726 extern struct irq_data *irq_get_irq_data(unsigned int irq); 727 728 static inline struct irq_chip *irq_get_chip(unsigned int irq) 729 { 730 struct irq_data *d = irq_get_irq_data(irq); 731 return d ? d->chip : NULL; 732 } 733 734 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) 735 { 736 return d->chip; 737 } 738 739 static inline void *irq_get_chip_data(unsigned int irq) 740 { 741 struct irq_data *d = irq_get_irq_data(irq); 742 return d ? d->chip_data : NULL; 743 } 744 745 static inline void *irq_data_get_irq_chip_data(struct irq_data *d) 746 { 747 return d->chip_data; 748 } 749 750 static inline void *irq_get_handler_data(unsigned int irq) 751 { 752 struct irq_data *d = irq_get_irq_data(irq); 753 return d ? d->common->handler_data : NULL; 754 } 755 756 static inline void *irq_data_get_irq_handler_data(struct irq_data *d) 757 { 758 return d->common->handler_data; 759 } 760 761 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) 762 { 763 struct irq_data *d = irq_get_irq_data(irq); 764 return d ? d->common->msi_desc : NULL; 765 } 766 767 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d) 768 { 769 return d->common->msi_desc; 770 } 771 772 static inline u32 irq_get_trigger_type(unsigned int irq) 773 { 774 struct irq_data *d = irq_get_irq_data(irq); 775 return d ? irqd_get_trigger_type(d) : 0; 776 } 777 778 static inline int irq_common_data_get_node(struct irq_common_data *d) 779 { 780 #ifdef CONFIG_NUMA 781 return d->node; 782 #else 783 return 0; 784 #endif 785 } 786 787 static inline int irq_data_get_node(struct irq_data *d) 788 { 789 return irq_common_data_get_node(d->common); 790 } 791 792 static inline struct cpumask *irq_get_affinity_mask(int irq) 793 { 794 struct irq_data *d = irq_get_irq_data(irq); 795 796 return d ? d->common->affinity : NULL; 797 } 798 799 static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d) 800 { 801 return d->common->affinity; 802 } 803 804 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 805 static inline 806 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 807 { 808 return d->common->effective_affinity; 809 } 810 static inline void irq_data_update_effective_affinity(struct irq_data *d, 811 const struct cpumask *m) 812 { 813 cpumask_copy(d->common->effective_affinity, m); 814 } 815 #else 816 static inline void irq_data_update_effective_affinity(struct irq_data *d, 817 const struct cpumask *m) 818 { 819 } 820 static inline 821 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 822 { 823 return d->common->affinity; 824 } 825 #endif 826 827 unsigned int arch_dynirq_lower_bound(unsigned int from); 828 829 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, 830 struct module *owner, const struct cpumask *affinity); 831 832 int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from, 833 unsigned int cnt, int node, struct module *owner, 834 const struct cpumask *affinity); 835 836 /* use macros to avoid needing export.h for THIS_MODULE */ 837 #define irq_alloc_descs(irq, from, cnt, node) \ 838 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL) 839 840 #define irq_alloc_desc(node) \ 841 irq_alloc_descs(-1, 0, 1, node) 842 843 #define irq_alloc_desc_at(at, node) \ 844 irq_alloc_descs(at, at, 1, node) 845 846 #define irq_alloc_desc_from(from, node) \ 847 irq_alloc_descs(-1, from, 1, node) 848 849 #define irq_alloc_descs_from(from, cnt, node) \ 850 irq_alloc_descs(-1, from, cnt, node) 851 852 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \ 853 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL) 854 855 #define devm_irq_alloc_desc(dev, node) \ 856 devm_irq_alloc_descs(dev, -1, 0, 1, node) 857 858 #define devm_irq_alloc_desc_at(dev, at, node) \ 859 devm_irq_alloc_descs(dev, at, at, 1, node) 860 861 #define devm_irq_alloc_desc_from(dev, from, node) \ 862 devm_irq_alloc_descs(dev, -1, from, 1, node) 863 864 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \ 865 devm_irq_alloc_descs(dev, -1, from, cnt, node) 866 867 void irq_free_descs(unsigned int irq, unsigned int cnt); 868 static inline void irq_free_desc(unsigned int irq) 869 { 870 irq_free_descs(irq, 1); 871 } 872 873 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ 874 unsigned int irq_alloc_hwirqs(int cnt, int node); 875 static inline unsigned int irq_alloc_hwirq(int node) 876 { 877 return irq_alloc_hwirqs(1, node); 878 } 879 void irq_free_hwirqs(unsigned int from, int cnt); 880 static inline void irq_free_hwirq(unsigned int irq) 881 { 882 return irq_free_hwirqs(irq, 1); 883 } 884 int arch_setup_hwirq(unsigned int irq, int node); 885 void arch_teardown_hwirq(unsigned int irq); 886 #endif 887 888 #ifdef CONFIG_GENERIC_IRQ_LEGACY 889 void irq_init_desc(unsigned int irq); 890 #endif 891 892 /** 893 * struct irq_chip_regs - register offsets for struct irq_gci 894 * @enable: Enable register offset to reg_base 895 * @disable: Disable register offset to reg_base 896 * @mask: Mask register offset to reg_base 897 * @ack: Ack register offset to reg_base 898 * @eoi: Eoi register offset to reg_base 899 * @type: Type configuration register offset to reg_base 900 * @polarity: Polarity configuration register offset to reg_base 901 */ 902 struct irq_chip_regs { 903 unsigned long enable; 904 unsigned long disable; 905 unsigned long mask; 906 unsigned long ack; 907 unsigned long eoi; 908 unsigned long type; 909 unsigned long polarity; 910 }; 911 912 /** 913 * struct irq_chip_type - Generic interrupt chip instance for a flow type 914 * @chip: The real interrupt chip which provides the callbacks 915 * @regs: Register offsets for this chip 916 * @handler: Flow handler associated with this chip 917 * @type: Chip can handle these flow types 918 * @mask_cache_priv: Cached mask register private to the chip type 919 * @mask_cache: Pointer to cached mask register 920 * 921 * A irq_generic_chip can have several instances of irq_chip_type when 922 * it requires different functions and register offsets for different 923 * flow types. 924 */ 925 struct irq_chip_type { 926 struct irq_chip chip; 927 struct irq_chip_regs regs; 928 irq_flow_handler_t handler; 929 u32 type; 930 u32 mask_cache_priv; 931 u32 *mask_cache; 932 }; 933 934 /** 935 * struct irq_chip_generic - Generic irq chip data structure 936 * @lock: Lock to protect register and cache data access 937 * @reg_base: Register base address (virtual) 938 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL) 939 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL) 940 * @suspend: Function called from core code on suspend once per 941 * chip; can be useful instead of irq_chip::suspend to 942 * handle chip details even when no interrupts are in use 943 * @resume: Function called from core code on resume once per chip; 944 * can be useful instead of irq_chip::suspend to handle 945 * chip details even when no interrupts are in use 946 * @irq_base: Interrupt base nr for this chip 947 * @irq_cnt: Number of interrupts handled by this chip 948 * @mask_cache: Cached mask register shared between all chip types 949 * @type_cache: Cached type register 950 * @polarity_cache: Cached polarity register 951 * @wake_enabled: Interrupt can wakeup from suspend 952 * @wake_active: Interrupt is marked as an wakeup from suspend source 953 * @num_ct: Number of available irq_chip_type instances (usually 1) 954 * @private: Private data for non generic chip callbacks 955 * @installed: bitfield to denote installed interrupts 956 * @unused: bitfield to denote unused interrupts 957 * @domain: irq domain pointer 958 * @list: List head for keeping track of instances 959 * @chip_types: Array of interrupt irq_chip_types 960 * 961 * Note, that irq_chip_generic can have multiple irq_chip_type 962 * implementations which can be associated to a particular irq line of 963 * an irq_chip_generic instance. That allows to share and protect 964 * state in an irq_chip_generic instance when we need to implement 965 * different flow mechanisms (level/edge) for it. 966 */ 967 struct irq_chip_generic { 968 raw_spinlock_t lock; 969 void __iomem *reg_base; 970 u32 (*reg_readl)(void __iomem *addr); 971 void (*reg_writel)(u32 val, void __iomem *addr); 972 void (*suspend)(struct irq_chip_generic *gc); 973 void (*resume)(struct irq_chip_generic *gc); 974 unsigned int irq_base; 975 unsigned int irq_cnt; 976 u32 mask_cache; 977 u32 type_cache; 978 u32 polarity_cache; 979 u32 wake_enabled; 980 u32 wake_active; 981 unsigned int num_ct; 982 void *private; 983 unsigned long installed; 984 unsigned long unused; 985 struct irq_domain *domain; 986 struct list_head list; 987 struct irq_chip_type chip_types[0]; 988 }; 989 990 /** 991 * enum irq_gc_flags - Initialization flags for generic irq chips 992 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg 993 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for 994 * irq chips which need to call irq_set_wake() on 995 * the parent irq. Usually GPIO implementations 996 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private 997 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask 998 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE) 999 */ 1000 enum irq_gc_flags { 1001 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 1002 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 1003 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, 1004 IRQ_GC_NO_MASK = 1 << 3, 1005 IRQ_GC_BE_IO = 1 << 4, 1006 }; 1007 1008 /* 1009 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains 1010 * @irqs_per_chip: Number of interrupts per chip 1011 * @num_chips: Number of chips 1012 * @irq_flags_to_set: IRQ* flags to set on irq setup 1013 * @irq_flags_to_clear: IRQ* flags to clear on irq setup 1014 * @gc_flags: Generic chip specific setup flags 1015 * @gc: Array of pointers to generic interrupt chips 1016 */ 1017 struct irq_domain_chip_generic { 1018 unsigned int irqs_per_chip; 1019 unsigned int num_chips; 1020 unsigned int irq_flags_to_clear; 1021 unsigned int irq_flags_to_set; 1022 enum irq_gc_flags gc_flags; 1023 struct irq_chip_generic *gc[0]; 1024 }; 1025 1026 /* Generic chip callback functions */ 1027 void irq_gc_noop(struct irq_data *d); 1028 void irq_gc_mask_disable_reg(struct irq_data *d); 1029 void irq_gc_mask_set_bit(struct irq_data *d); 1030 void irq_gc_mask_clr_bit(struct irq_data *d); 1031 void irq_gc_unmask_enable_reg(struct irq_data *d); 1032 void irq_gc_ack_set_bit(struct irq_data *d); 1033 void irq_gc_ack_clr_bit(struct irq_data *d); 1034 void irq_gc_mask_disable_and_ack_set(struct irq_data *d); 1035 void irq_gc_eoi(struct irq_data *d); 1036 int irq_gc_set_wake(struct irq_data *d, unsigned int on); 1037 1038 /* Setup functions for irq_chip_generic */ 1039 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, 1040 irq_hw_number_t hw_irq); 1041 struct irq_chip_generic * 1042 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, 1043 void __iomem *reg_base, irq_flow_handler_t handler); 1044 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 1045 enum irq_gc_flags flags, unsigned int clr, 1046 unsigned int set); 1047 int irq_setup_alt_chip(struct irq_data *d, unsigned int type); 1048 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 1049 unsigned int clr, unsigned int set); 1050 1051 struct irq_chip_generic * 1052 devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct, 1053 unsigned int irq_base, void __iomem *reg_base, 1054 irq_flow_handler_t handler); 1055 int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc, 1056 u32 msk, enum irq_gc_flags flags, 1057 unsigned int clr, unsigned int set); 1058 1059 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); 1060 1061 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, 1062 int num_ct, const char *name, 1063 irq_flow_handler_t handler, 1064 unsigned int clr, unsigned int set, 1065 enum irq_gc_flags flags); 1066 1067 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \ 1068 handler, clr, set, flags) \ 1069 ({ \ 1070 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \ 1071 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\ 1072 handler, clr, set, flags); \ 1073 }) 1074 1075 static inline void irq_free_generic_chip(struct irq_chip_generic *gc) 1076 { 1077 kfree(gc); 1078 } 1079 1080 static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc, 1081 u32 msk, unsigned int clr, 1082 unsigned int set) 1083 { 1084 irq_remove_generic_chip(gc, msk, clr, set); 1085 irq_free_generic_chip(gc); 1086 } 1087 1088 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) 1089 { 1090 return container_of(d->chip, struct irq_chip_type, chip); 1091 } 1092 1093 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) 1094 1095 #ifdef CONFIG_SMP 1096 static inline void irq_gc_lock(struct irq_chip_generic *gc) 1097 { 1098 raw_spin_lock(&gc->lock); 1099 } 1100 1101 static inline void irq_gc_unlock(struct irq_chip_generic *gc) 1102 { 1103 raw_spin_unlock(&gc->lock); 1104 } 1105 #else 1106 static inline void irq_gc_lock(struct irq_chip_generic *gc) { } 1107 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } 1108 #endif 1109 1110 /* 1111 * The irqsave variants are for usage in non interrupt code. Do not use 1112 * them in irq_chip callbacks. Use irq_gc_lock() instead. 1113 */ 1114 #define irq_gc_lock_irqsave(gc, flags) \ 1115 raw_spin_lock_irqsave(&(gc)->lock, flags) 1116 1117 #define irq_gc_unlock_irqrestore(gc, flags) \ 1118 raw_spin_unlock_irqrestore(&(gc)->lock, flags) 1119 1120 static inline void irq_reg_writel(struct irq_chip_generic *gc, 1121 u32 val, int reg_offset) 1122 { 1123 if (gc->reg_writel) 1124 gc->reg_writel(val, gc->reg_base + reg_offset); 1125 else 1126 writel(val, gc->reg_base + reg_offset); 1127 } 1128 1129 static inline u32 irq_reg_readl(struct irq_chip_generic *gc, 1130 int reg_offset) 1131 { 1132 if (gc->reg_readl) 1133 return gc->reg_readl(gc->reg_base + reg_offset); 1134 else 1135 return readl(gc->reg_base + reg_offset); 1136 } 1137 1138 struct irq_matrix; 1139 struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits, 1140 unsigned int alloc_start, 1141 unsigned int alloc_end); 1142 void irq_matrix_online(struct irq_matrix *m); 1143 void irq_matrix_offline(struct irq_matrix *m); 1144 void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace); 1145 int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk); 1146 void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk); 1147 int irq_matrix_alloc_managed(struct irq_matrix *m, unsigned int cpu); 1148 void irq_matrix_reserve(struct irq_matrix *m); 1149 void irq_matrix_remove_reserved(struct irq_matrix *m); 1150 int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk, 1151 bool reserved, unsigned int *mapped_cpu); 1152 void irq_matrix_free(struct irq_matrix *m, unsigned int cpu, 1153 unsigned int bit, bool managed); 1154 void irq_matrix_assign(struct irq_matrix *m, unsigned int bit); 1155 unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown); 1156 unsigned int irq_matrix_allocated(struct irq_matrix *m); 1157 unsigned int irq_matrix_reserved(struct irq_matrix *m); 1158 void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind); 1159 1160 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */ 1161 #define INVALID_HWIRQ (~0UL) 1162 irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu); 1163 int __ipi_send_single(struct irq_desc *desc, unsigned int cpu); 1164 int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest); 1165 int ipi_send_single(unsigned int virq, unsigned int cpu); 1166 int ipi_send_mask(unsigned int virq, const struct cpumask *dest); 1167 1168 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER 1169 /* 1170 * Registers a generic IRQ handling function as the top-level IRQ handler in 1171 * the system, which is generally the first C code called from an assembly 1172 * architecture-specific interrupt handler. 1173 * 1174 * Returns 0 on success, or -EBUSY if an IRQ handler has already been 1175 * registered. 1176 */ 1177 int __init set_handle_irq(void (*handle_irq)(struct pt_regs *)); 1178 1179 /* 1180 * Allows interrupt handlers to find the irqchip that's been registered as the 1181 * top-level IRQ handler. 1182 */ 1183 extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init; 1184 #endif 1185 1186 #endif /* _LINUX_IRQ_H */ 1187