1 /*
2  * Copyright (C) STMicroelectronics 2016
3  *
4  * Author: Benjamin Gaignard <[email protected]>
5  *
6  * License terms:  GNU General Public License (GPL), version 2
7  */
8 
9 #ifndef _STM32_TIMER_TRIGGER_H_
10 #define _STM32_TIMER_TRIGGER_H_
11 
12 #define TIM1_TRGO	"tim1_trgo"
13 #define TIM1_CH1	"tim1_ch1"
14 #define TIM1_CH2	"tim1_ch2"
15 #define TIM1_CH3	"tim1_ch3"
16 #define TIM1_CH4	"tim1_ch4"
17 
18 #define TIM2_TRGO	"tim2_trgo"
19 #define TIM2_CH1	"tim2_ch1"
20 #define TIM2_CH2	"tim2_ch2"
21 #define TIM2_CH3	"tim2_ch3"
22 #define TIM2_CH4	"tim2_ch4"
23 
24 #define TIM3_TRGO	"tim3_trgo"
25 #define TIM3_CH1	"tim3_ch1"
26 #define TIM3_CH2	"tim3_ch2"
27 #define TIM3_CH3	"tim3_ch3"
28 #define TIM3_CH4	"tim3_ch4"
29 
30 #define TIM4_TRGO	"tim4_trgo"
31 #define TIM4_CH1	"tim4_ch1"
32 #define TIM4_CH2	"tim4_ch2"
33 #define TIM4_CH3	"tim4_ch3"
34 #define TIM4_CH4	"tim4_ch4"
35 
36 #define TIM5_TRGO	"tim5_trgo"
37 #define TIM5_CH1	"tim5_ch1"
38 #define TIM5_CH2	"tim5_ch2"
39 #define TIM5_CH3	"tim5_ch3"
40 #define TIM5_CH4	"tim5_ch4"
41 
42 #define TIM6_TRGO	"tim6_trgo"
43 
44 #define TIM7_TRGO	"tim7_trgo"
45 
46 #define TIM8_TRGO	"tim8_trgo"
47 #define TIM8_CH1	"tim8_ch1"
48 #define TIM8_CH2	"tim8_ch2"
49 #define TIM8_CH3	"tim8_ch3"
50 #define TIM8_CH4	"tim8_ch4"
51 
52 #define TIM9_TRGO	"tim9_trgo"
53 #define TIM9_CH1	"tim9_ch1"
54 #define TIM9_CH2	"tim9_ch2"
55 
56 #define TIM12_TRGO	"tim12_trgo"
57 #define TIM12_CH1	"tim12_ch1"
58 #define TIM12_CH2	"tim12_ch2"
59 
60 bool is_stm32_timer_trigger(struct iio_trigger *trig);
61 
62 #endif
63