1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 #ifndef HISI_ACC_QM_H 4 #define HISI_ACC_QM_H 5 6 #include <linux/bitfield.h> 7 #include <linux/debugfs.h> 8 #include <linux/iopoll.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 12 #define QM_QNUM_V1 4096 13 #define QM_QNUM_V2 1024 14 #define QM_MAX_VFS_NUM_V2 63 15 16 /* qm user domain */ 17 #define QM_ARUSER_M_CFG_1 0x100088 18 #define AXUSER_SNOOP_ENABLE BIT(30) 19 #define AXUSER_CMD_TYPE GENMASK(14, 12) 20 #define AXUSER_CMD_SMMU_NORMAL 1 21 #define AXUSER_NS BIT(6) 22 #define AXUSER_NO BIT(5) 23 #define AXUSER_FP BIT(4) 24 #define AXUSER_SSV BIT(0) 25 #define AXUSER_BASE (AXUSER_SNOOP_ENABLE | \ 26 FIELD_PREP(AXUSER_CMD_TYPE, \ 27 AXUSER_CMD_SMMU_NORMAL) | \ 28 AXUSER_NS | AXUSER_NO | AXUSER_FP) 29 #define QM_ARUSER_M_CFG_ENABLE 0x100090 30 #define ARUSER_M_CFG_ENABLE 0xfffffffe 31 #define QM_AWUSER_M_CFG_1 0x100098 32 #define QM_AWUSER_M_CFG_ENABLE 0x1000a0 33 #define AWUSER_M_CFG_ENABLE 0xfffffffe 34 #define QM_WUSER_M_CFG_ENABLE 0x1000a8 35 #define WUSER_M_CFG_ENABLE 0xffffffff 36 37 /* mailbox */ 38 #define QM_MB_CMD_SQC 0x0 39 #define QM_MB_CMD_CQC 0x1 40 #define QM_MB_CMD_EQC 0x2 41 #define QM_MB_CMD_AEQC 0x3 42 #define QM_MB_CMD_SQC_BT 0x4 43 #define QM_MB_CMD_CQC_BT 0x5 44 #define QM_MB_CMD_SQC_VFT_V2 0x6 45 #define QM_MB_CMD_STOP_QP 0x8 46 #define QM_MB_CMD_FLUSH_QM 0x9 47 #define QM_MB_CMD_SRC 0xc 48 #define QM_MB_CMD_DST 0xd 49 50 #define QM_MB_CMD_SEND_BASE 0x300 51 #define QM_MB_EVENT_SHIFT 8 52 #define QM_MB_BUSY_SHIFT 13 53 #define QM_MB_OP_SHIFT 14 54 #define QM_MB_CMD_DATA_ADDR_L 0x304 55 #define QM_MB_CMD_DATA_ADDR_H 0x308 56 #define QM_MB_MAX_WAIT_CNT 6000 57 58 /* doorbell */ 59 #define QM_DOORBELL_CMD_SQ 0 60 #define QM_DOORBELL_CMD_CQ 1 61 #define QM_DOORBELL_CMD_EQ 2 62 #define QM_DOORBELL_CMD_AEQ 3 63 64 #define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000 65 #define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000 66 #define QM_QP_MAX_NUM_SHIFT 11 67 #define QM_DB_CMD_SHIFT_V2 12 68 #define QM_DB_RAND_SHIFT_V2 16 69 #define QM_DB_INDEX_SHIFT_V2 32 70 #define QM_DB_PRIORITY_SHIFT_V2 48 71 #define QM_VF_STATE 0x60 72 73 /* qm cache */ 74 #define QM_CACHE_CTL 0x100050 75 #define SQC_CACHE_ENABLE BIT(0) 76 #define CQC_CACHE_ENABLE BIT(1) 77 #define SQC_CACHE_WB_ENABLE BIT(4) 78 #define SQC_CACHE_WB_THRD GENMASK(10, 5) 79 #define CQC_CACHE_WB_ENABLE BIT(11) 80 #define CQC_CACHE_WB_THRD GENMASK(17, 12) 81 #define QM_AXI_M_CFG 0x1000ac 82 #define AXI_M_CFG 0xffff 83 #define QM_AXI_M_CFG_ENABLE 0x1000b0 84 #define AM_CFG_SINGLE_PORT_MAX_TRANS 0x300014 85 #define AXI_M_CFG_ENABLE 0xffffffff 86 #define QM_PEH_AXUSER_CFG 0x1000cc 87 #define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0 88 #define PEH_AXUSER_CFG 0x401001 89 #define PEH_AXUSER_CFG_ENABLE 0xffffffff 90 91 #define QM_MIN_QNUM 2 92 #define HISI_ACC_SGL_SGE_NR_MAX 255 93 #define QM_SHAPER_CFG 0x100164 94 #define QM_SHAPER_ENABLE BIT(30) 95 #define QM_SHAPER_TYPE1_OFFSET 10 96 97 /* page number for queue file region */ 98 #define QM_DOORBELL_PAGE_NR 1 99 100 /* uacce mode of the driver */ 101 #define UACCE_MODE_NOUACCE 0 /* don't use uacce */ 102 #define UACCE_MODE_SVA 1 /* use uacce sva mode */ 103 #define UACCE_MODE_DESC "0(default) means only register to crypto, 1 means both register to crypto and uacce" 104 105 enum qm_stop_reason { 106 QM_NORMAL, 107 QM_SOFT_RESET, 108 QM_DOWN, 109 }; 110 111 enum qm_state { 112 QM_WORK = 0, 113 QM_STOP, 114 }; 115 116 enum qp_state { 117 QP_START = 1, 118 QP_STOP, 119 }; 120 121 enum qm_hw_ver { 122 QM_HW_V1 = 0x20, 123 QM_HW_V2 = 0x21, 124 QM_HW_V3 = 0x30, 125 }; 126 127 enum qm_fun_type { 128 QM_HW_PF, 129 QM_HW_VF, 130 }; 131 132 enum qm_debug_file { 133 CURRENT_QM, 134 CURRENT_Q, 135 CLEAR_ENABLE, 136 DEBUG_FILE_NUM, 137 }; 138 139 enum qm_vf_state { 140 QM_READY = 0, 141 QM_NOT_READY, 142 }; 143 144 enum qm_misc_ctl_bits { 145 QM_DRIVER_REMOVING = 0x0, 146 QM_RST_SCHED, 147 QM_RESETTING, 148 QM_MODULE_PARAM, 149 }; 150 151 enum qm_cap_bits { 152 QM_SUPPORT_DB_ISOLATION = 0x0, 153 QM_SUPPORT_FUNC_QOS, 154 QM_SUPPORT_STOP_QP, 155 QM_SUPPORT_STOP_FUNC, 156 QM_SUPPORT_MB_COMMAND, 157 QM_SUPPORT_SVA_PREFETCH, 158 QM_SUPPORT_RPM, 159 }; 160 161 struct qm_dev_alg { 162 u64 alg_msk; 163 const char *alg; 164 }; 165 166 struct qm_dev_dfx { 167 u32 dev_state; 168 u32 dev_timeout; 169 }; 170 171 struct dfx_diff_registers { 172 u32 *regs; 173 u32 reg_offset; 174 u32 reg_len; 175 }; 176 177 struct qm_dfx { 178 atomic64_t err_irq_cnt; 179 atomic64_t aeq_irq_cnt; 180 atomic64_t abnormal_irq_cnt; 181 atomic64_t create_qp_err_cnt; 182 atomic64_t mb_err_cnt; 183 }; 184 185 struct debugfs_file { 186 enum qm_debug_file index; 187 struct mutex lock; 188 struct qm_debug *debug; 189 }; 190 191 struct qm_debug { 192 u32 curr_qm_qp_num; 193 u32 sqe_mask_offset; 194 u32 sqe_mask_len; 195 struct qm_dfx dfx; 196 struct dentry *debug_root; 197 struct dentry *qm_d; 198 struct debugfs_file files[DEBUG_FILE_NUM]; 199 struct qm_dev_dfx dev_dfx; 200 unsigned int *qm_last_words; 201 /* ACC engines recoreding last regs */ 202 unsigned int *last_words; 203 struct dfx_diff_registers *qm_diff_regs; 204 struct dfx_diff_registers *acc_diff_regs; 205 }; 206 207 struct qm_shaper_factor { 208 u32 func_qos; 209 u64 cir_b; 210 u64 cir_u; 211 u64 cir_s; 212 u64 cbs_s; 213 }; 214 215 struct qm_dma { 216 void *va; 217 dma_addr_t dma; 218 size_t size; 219 }; 220 221 struct hisi_qm_status { 222 u32 eq_head; 223 bool eqc_phase; 224 u32 aeq_head; 225 bool aeqc_phase; 226 atomic_t flags; 227 int stop_reason; 228 }; 229 230 struct hisi_qm; 231 232 enum acc_err_result { 233 ACC_ERR_NONE, 234 ACC_ERR_NEED_RESET, 235 ACC_ERR_RECOVERED, 236 }; 237 238 struct hisi_qm_err_info { 239 char *acpi_rst; 240 u32 msi_wr_port; 241 u32 ecc_2bits_mask; 242 u32 qm_shutdown_mask; 243 u32 dev_shutdown_mask; 244 u32 qm_reset_mask; 245 u32 dev_reset_mask; 246 u32 ce; 247 u32 nfe; 248 u32 fe; 249 }; 250 251 struct hisi_qm_err_status { 252 u32 is_qm_ecc_mbit; 253 u32 is_dev_ecc_mbit; 254 }; 255 256 struct hisi_qm_err_ini { 257 int (*hw_init)(struct hisi_qm *qm); 258 void (*hw_err_enable)(struct hisi_qm *qm); 259 void (*hw_err_disable)(struct hisi_qm *qm); 260 u32 (*get_dev_hw_err_status)(struct hisi_qm *qm); 261 void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts); 262 void (*open_axi_master_ooo)(struct hisi_qm *qm); 263 void (*close_axi_master_ooo)(struct hisi_qm *qm); 264 void (*open_sva_prefetch)(struct hisi_qm *qm); 265 void (*close_sva_prefetch)(struct hisi_qm *qm); 266 void (*show_last_dfx_regs)(struct hisi_qm *qm); 267 void (*err_info_init)(struct hisi_qm *qm); 268 enum acc_err_result (*get_err_result)(struct hisi_qm *qm); 269 }; 270 271 struct hisi_qm_cap_info { 272 u32 type; 273 /* Register offset */ 274 u32 offset; 275 /* Bit offset in register */ 276 u32 shift; 277 u32 mask; 278 u32 v1_val; 279 u32 v2_val; 280 u32 v3_val; 281 }; 282 283 struct hisi_qm_cap_query_info { 284 u32 type; 285 const char *name; 286 u32 offset; 287 u32 v1_val; 288 u32 v2_val; 289 u32 v3_val; 290 }; 291 292 struct hisi_qm_cap_record { 293 u32 type; 294 const char *name; 295 u32 cap_val; 296 }; 297 298 struct hisi_qm_cap_tables { 299 u32 qm_cap_size; 300 struct hisi_qm_cap_record *qm_cap_table; 301 u32 dev_cap_size; 302 struct hisi_qm_cap_record *dev_cap_table; 303 }; 304 305 struct hisi_qm_list { 306 struct mutex lock; 307 struct list_head list; 308 int (*register_to_crypto)(struct hisi_qm *qm); 309 void (*unregister_from_crypto)(struct hisi_qm *qm); 310 }; 311 312 struct hisi_qm_poll_data { 313 struct hisi_qm *qm; 314 struct work_struct work; 315 u16 *qp_finish_id; 316 u16 eqe_num; 317 }; 318 319 /** 320 * struct qm_err_isolate 321 * @isolate_lock: protects device error log 322 * @err_threshold: user config error threshold which triggers isolation 323 * @is_isolate: device isolation state 324 * @uacce_hw_errs: index into qm device error list 325 */ 326 struct qm_err_isolate { 327 struct mutex isolate_lock; 328 u32 err_threshold; 329 bool is_isolate; 330 struct list_head qm_hw_errs; 331 }; 332 333 struct qm_rsv_buf { 334 struct qm_sqc *sqc; 335 struct qm_cqc *cqc; 336 struct qm_eqc *eqc; 337 struct qm_aeqc *aeqc; 338 dma_addr_t sqc_dma; 339 dma_addr_t cqc_dma; 340 dma_addr_t eqc_dma; 341 dma_addr_t aeqc_dma; 342 struct qm_dma qcdma; 343 }; 344 345 struct hisi_qm { 346 enum qm_hw_ver ver; 347 enum qm_fun_type fun_type; 348 const char *dev_name; 349 struct pci_dev *pdev; 350 void __iomem *io_base; 351 void __iomem *db_io_base; 352 353 /* Capbility version, 0: not supports */ 354 u32 cap_ver; 355 u32 sqe_size; 356 u32 qp_base; 357 u32 qp_num; 358 u32 qp_in_used; 359 u32 ctrl_qp_num; 360 u32 max_qp_num; 361 u32 vfs_num; 362 u32 db_interval; 363 u16 eq_depth; 364 u16 aeq_depth; 365 struct list_head list; 366 struct hisi_qm_list *qm_list; 367 368 struct qm_dma qdma; 369 struct qm_sqc *sqc; 370 struct qm_cqc *cqc; 371 struct qm_eqe *eqe; 372 struct qm_aeqe *aeqe; 373 dma_addr_t sqc_dma; 374 dma_addr_t cqc_dma; 375 dma_addr_t eqe_dma; 376 dma_addr_t aeqe_dma; 377 struct qm_rsv_buf xqc_buf; 378 379 struct hisi_qm_status status; 380 const struct hisi_qm_err_ini *err_ini; 381 struct hisi_qm_err_info err_info; 382 struct hisi_qm_err_status err_status; 383 /* driver removing and reset sched */ 384 unsigned long misc_ctl; 385 /* Device capability bit */ 386 unsigned long caps; 387 388 struct rw_semaphore qps_lock; 389 struct idr qp_idr; 390 struct hisi_qp *qp_array; 391 struct hisi_qm_poll_data *poll_data; 392 393 struct mutex mailbox_lock; 394 395 const struct hisi_qm_hw_ops *ops; 396 397 struct qm_debug debug; 398 399 u32 error_mask; 400 401 struct workqueue_struct *wq; 402 struct work_struct rst_work; 403 struct work_struct cmd_process; 404 405 bool use_sva; 406 407 resource_size_t phys_base; 408 resource_size_t db_phys_base; 409 struct uacce_device *uacce; 410 int mode; 411 struct qm_shaper_factor *factor; 412 u32 mb_qos; 413 u32 type_rate; 414 struct qm_err_isolate isolate_data; 415 416 struct hisi_qm_cap_tables cap_tables; 417 }; 418 419 struct hisi_qp_status { 420 atomic_t used; 421 u16 sq_tail; 422 u16 cq_head; 423 bool cqc_phase; 424 atomic_t flags; 425 }; 426 427 struct hisi_qp_ops { 428 int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm); 429 }; 430 431 struct hisi_qp { 432 u32 qp_id; 433 u16 sq_depth; 434 u16 cq_depth; 435 u8 alg_type; 436 u8 req_type; 437 438 struct qm_dma qdma; 439 void *sqe; 440 struct qm_cqe *cqe; 441 dma_addr_t sqe_dma; 442 dma_addr_t cqe_dma; 443 444 struct hisi_qp_status qp_status; 445 struct hisi_qp_ops *hw_ops; 446 void *qp_ctx; 447 void (*req_cb)(struct hisi_qp *qp, void *data); 448 void (*event_cb)(struct hisi_qp *qp); 449 450 struct hisi_qm *qm; 451 bool is_resetting; 452 bool is_in_kernel; 453 u16 pasid; 454 struct uacce_queue *uacce_q; 455 }; 456 457 static inline int vfs_num_set(const char *val, const struct kernel_param *kp) 458 { 459 u32 n; 460 int ret; 461 462 if (!val) 463 return -EINVAL; 464 465 ret = kstrtou32(val, 10, &n); 466 if (ret < 0) 467 return ret; 468 469 if (n > QM_MAX_VFS_NUM_V2) 470 return -EINVAL; 471 472 return param_set_int(val, kp); 473 } 474 475 static inline int mode_set(const char *val, const struct kernel_param *kp) 476 { 477 u32 n; 478 int ret; 479 480 if (!val) 481 return -EINVAL; 482 483 ret = kstrtou32(val, 10, &n); 484 if (ret != 0 || (n != UACCE_MODE_SVA && 485 n != UACCE_MODE_NOUACCE)) 486 return -EINVAL; 487 488 return param_set_int(val, kp); 489 } 490 491 static inline int uacce_mode_set(const char *val, const struct kernel_param *kp) 492 { 493 return mode_set(val, kp); 494 } 495 496 static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list) 497 { 498 INIT_LIST_HEAD(&qm_list->list); 499 mutex_init(&qm_list->lock); 500 } 501 502 static inline void hisi_qm_add_list(struct hisi_qm *qm, struct hisi_qm_list *qm_list) 503 { 504 mutex_lock(&qm_list->lock); 505 list_add_tail(&qm->list, &qm_list->list); 506 mutex_unlock(&qm_list->lock); 507 } 508 509 static inline void hisi_qm_del_list(struct hisi_qm *qm, struct hisi_qm_list *qm_list) 510 { 511 mutex_lock(&qm_list->lock); 512 list_del(&qm->list); 513 mutex_unlock(&qm_list->lock); 514 } 515 516 int hisi_qm_q_num_set(const char *val, const struct kernel_param *kp, 517 unsigned int device); 518 int hisi_qm_init(struct hisi_qm *qm); 519 void hisi_qm_uninit(struct hisi_qm *qm); 520 int hisi_qm_start(struct hisi_qm *qm); 521 int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r); 522 int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg); 523 void hisi_qm_stop_qp(struct hisi_qp *qp); 524 int hisi_qp_send(struct hisi_qp *qp, const void *msg); 525 void hisi_qm_debug_init(struct hisi_qm *qm); 526 void hisi_qm_debug_regs_clear(struct hisi_qm *qm); 527 int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs); 528 int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen); 529 int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs); 530 void hisi_qm_dev_err_init(struct hisi_qm *qm); 531 void hisi_qm_dev_err_uninit(struct hisi_qm *qm); 532 int hisi_qm_regs_debugfs_init(struct hisi_qm *qm, 533 struct dfx_diff_registers *dregs, u32 reg_len); 534 void hisi_qm_regs_debugfs_uninit(struct hisi_qm *qm, u32 reg_len); 535 void hisi_qm_acc_diff_regs_dump(struct hisi_qm *qm, struct seq_file *s, 536 struct dfx_diff_registers *dregs, u32 regs_len); 537 538 pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev, 539 pci_channel_state_t state); 540 pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev); 541 void hisi_qm_reset_prepare(struct pci_dev *pdev); 542 void hisi_qm_reset_done(struct pci_dev *pdev); 543 544 int hisi_qm_wait_mb_ready(struct hisi_qm *qm); 545 int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue, 546 bool op); 547 548 struct hisi_acc_sgl_pool; 549 struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev, 550 struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool, 551 u32 index, dma_addr_t *hw_sgl_dma); 552 void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl, 553 struct hisi_acc_hw_sgl *hw_sgl); 554 struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev, 555 u32 count, u32 sge_nr); 556 void hisi_acc_free_sgl_pool(struct device *dev, 557 struct hisi_acc_sgl_pool *pool); 558 int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num, 559 u8 alg_type, int node, struct hisi_qp **qps); 560 void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num); 561 void hisi_qm_dev_shutdown(struct pci_dev *pdev); 562 void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list); 563 int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard); 564 void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard); 565 int hisi_qm_resume(struct device *dev); 566 int hisi_qm_suspend(struct device *dev); 567 void hisi_qm_pm_uninit(struct hisi_qm *qm); 568 void hisi_qm_pm_init(struct hisi_qm *qm); 569 int hisi_qm_get_dfx_access(struct hisi_qm *qm); 570 void hisi_qm_put_dfx_access(struct hisi_qm *qm); 571 void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset); 572 u32 hisi_qm_get_hw_info(struct hisi_qm *qm, 573 const struct hisi_qm_cap_info *info_table, 574 u32 index, bool is_read); 575 u32 hisi_qm_get_cap_value(struct hisi_qm *qm, 576 const struct hisi_qm_cap_query_info *info_table, 577 u32 index, bool is_read); 578 int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs, 579 u32 dev_algs_size); 580 581 /* Used by VFIO ACC live migration driver */ 582 struct pci_driver *hisi_sec_get_pf_driver(void); 583 struct pci_driver *hisi_hpre_get_pf_driver(void); 584 struct pci_driver *hisi_zip_get_pf_driver(void); 585 #endif 586