1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __LINUX_GPIO_DRIVER_H 3 #define __LINUX_GPIO_DRIVER_H 4 5 #include <linux/bits.h> 6 #include <linux/cleanup.h> 7 #include <linux/err.h> 8 #include <linux/irqchip/chained_irq.h> 9 #include <linux/irqdomain.h> 10 #include <linux/irqhandler.h> 11 #include <linux/lockdep.h> 12 #include <linux/pinctrl/pinconf-generic.h> 13 #include <linux/pinctrl/pinctrl.h> 14 #include <linux/property.h> 15 #include <linux/spinlock_types.h> 16 #include <linux/types.h> 17 #include <linux/util_macros.h> 18 19 #ifdef CONFIG_GENERIC_MSI_IRQ 20 #include <asm/msi.h> 21 #endif 22 23 struct device; 24 struct irq_chip; 25 struct irq_data; 26 struct module; 27 struct of_phandle_args; 28 struct pinctrl_dev; 29 struct seq_file; 30 31 struct gpio_chip; 32 struct gpio_desc; 33 struct gpio_device; 34 35 enum gpio_lookup_flags; 36 enum gpiod_flags; 37 38 union gpio_irq_fwspec { 39 struct irq_fwspec fwspec; 40 #ifdef CONFIG_GENERIC_MSI_IRQ 41 msi_alloc_info_t msiinfo; 42 #endif 43 }; 44 45 #define GPIO_LINE_DIRECTION_IN 1 46 #define GPIO_LINE_DIRECTION_OUT 0 47 48 /** 49 * struct gpio_irq_chip - GPIO interrupt controller 50 */ 51 struct gpio_irq_chip { 52 /** 53 * @chip: 54 * 55 * GPIO IRQ chip implementation, provided by GPIO driver. 56 */ 57 struct irq_chip *chip; 58 59 /** 60 * @domain: 61 * 62 * Interrupt translation domain; responsible for mapping between GPIO 63 * hwirq number and Linux IRQ number. 64 */ 65 struct irq_domain *domain; 66 67 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 68 /** 69 * @fwnode: 70 * 71 * Firmware node corresponding to this gpiochip/irqchip, necessary 72 * for hierarchical irqdomain support. 73 */ 74 struct fwnode_handle *fwnode; 75 76 /** 77 * @parent_domain: 78 * 79 * If non-NULL, will be set as the parent of this GPIO interrupt 80 * controller's IRQ domain to establish a hierarchical interrupt 81 * domain. The presence of this will activate the hierarchical 82 * interrupt support. 83 */ 84 struct irq_domain *parent_domain; 85 86 /** 87 * @child_to_parent_hwirq: 88 * 89 * This callback translates a child hardware IRQ offset to a parent 90 * hardware IRQ offset on a hierarchical interrupt chip. The child 91 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the 92 * ngpio field of struct gpio_chip) and the corresponding parent 93 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by 94 * the driver. The driver can calculate this from an offset or using 95 * a lookup table or whatever method is best for this chip. Return 96 * 0 on successful translation in the driver. 97 * 98 * If some ranges of hardware IRQs do not have a corresponding parent 99 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and 100 * @need_valid_mask to make these GPIO lines unavailable for 101 * translation. 102 */ 103 int (*child_to_parent_hwirq)(struct gpio_chip *gc, 104 unsigned int child_hwirq, 105 unsigned int child_type, 106 unsigned int *parent_hwirq, 107 unsigned int *parent_type); 108 109 /** 110 * @populate_parent_alloc_arg : 111 * 112 * This optional callback allocates and populates the specific struct 113 * for the parent's IRQ domain. If this is not specified, then 114 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell 115 * variant named &gpiochip_populate_parent_fwspec_fourcell is also 116 * available. 117 */ 118 int (*populate_parent_alloc_arg)(struct gpio_chip *gc, 119 union gpio_irq_fwspec *fwspec, 120 unsigned int parent_hwirq, 121 unsigned int parent_type); 122 123 /** 124 * @child_offset_to_irq: 125 * 126 * This optional callback is used to translate the child's GPIO line 127 * offset on the GPIO chip to an IRQ number for the GPIO to_irq() 128 * callback. If this is not specified, then a default callback will be 129 * provided that returns the line offset. 130 */ 131 unsigned int (*child_offset_to_irq)(struct gpio_chip *gc, 132 unsigned int pin); 133 134 /** 135 * @child_irq_domain_ops: 136 * 137 * The IRQ domain operations that will be used for this GPIO IRQ 138 * chip. If no operations are provided, then default callbacks will 139 * be populated to setup the IRQ hierarchy. Some drivers need to 140 * supply their own translate function. 141 */ 142 struct irq_domain_ops child_irq_domain_ops; 143 #endif 144 145 /** 146 * @handler: 147 * 148 * The IRQ handler to use (often a predefined IRQ core function) for 149 * GPIO IRQs, provided by GPIO driver. 150 */ 151 irq_flow_handler_t handler; 152 153 /** 154 * @default_type: 155 * 156 * Default IRQ triggering type applied during GPIO driver 157 * initialization, provided by GPIO driver. 158 */ 159 unsigned int default_type; 160 161 /** 162 * @lock_key: 163 * 164 * Per GPIO IRQ chip lockdep class for IRQ lock. 165 */ 166 struct lock_class_key *lock_key; 167 168 /** 169 * @request_key: 170 * 171 * Per GPIO IRQ chip lockdep class for IRQ request. 172 */ 173 struct lock_class_key *request_key; 174 175 /** 176 * @parent_handler: 177 * 178 * The interrupt handler for the GPIO chip's parent interrupts, may be 179 * NULL if the parent interrupts are nested rather than cascaded. 180 */ 181 irq_flow_handler_t parent_handler; 182 183 union { 184 /** 185 * @parent_handler_data: 186 * 187 * If @per_parent_data is false, @parent_handler_data is a 188 * single pointer used as the data associated with every 189 * parent interrupt. 190 */ 191 void *parent_handler_data; 192 193 /** 194 * @parent_handler_data_array: 195 * 196 * If @per_parent_data is true, @parent_handler_data_array is 197 * an array of @num_parents pointers, and is used to associate 198 * different data for each parent. This cannot be NULL if 199 * @per_parent_data is true. 200 */ 201 void **parent_handler_data_array; 202 }; 203 204 /** 205 * @num_parents: 206 * 207 * The number of interrupt parents of a GPIO chip. 208 */ 209 unsigned int num_parents; 210 211 /** 212 * @parents: 213 * 214 * A list of interrupt parents of a GPIO chip. This is owned by the 215 * driver, so the core will only reference this list, not modify it. 216 */ 217 unsigned int *parents; 218 219 /** 220 * @map: 221 * 222 * A list of interrupt parents for each line of a GPIO chip. 223 */ 224 unsigned int *map; 225 226 /** 227 * @threaded: 228 * 229 * True if set the interrupt handling uses nested threads. 230 */ 231 bool threaded; 232 233 /** 234 * @per_parent_data: 235 * 236 * True if parent_handler_data_array describes a @num_parents 237 * sized array to be used as parent data. 238 */ 239 bool per_parent_data; 240 241 /** 242 * @initialized: 243 * 244 * Flag to track GPIO chip irq member's initialization. 245 * This flag will make sure GPIO chip irq members are not used 246 * before they are initialized. 247 */ 248 bool initialized; 249 250 /** 251 * @domain_is_allocated_externally: 252 * 253 * True it the irq_domain was allocated outside of gpiolib, in which 254 * case gpiolib won't free the irq_domain itself. 255 */ 256 bool domain_is_allocated_externally; 257 258 /** 259 * @init_hw: optional routine to initialize hardware before 260 * an IRQ chip will be added. This is quite useful when 261 * a particular driver wants to clear IRQ related registers 262 * in order to avoid undesired events. 263 */ 264 int (*init_hw)(struct gpio_chip *gc); 265 266 /** 267 * @init_valid_mask: optional routine to initialize @valid_mask, to be 268 * used if not all GPIO lines are valid interrupts. Sometimes some 269 * lines just cannot fire interrupts, and this routine, when defined, 270 * is passed a bitmap in "valid_mask" and it will have ngpios 271 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can 272 * then directly set some bits to "0" if they cannot be used for 273 * interrupts. 274 */ 275 void (*init_valid_mask)(struct gpio_chip *gc, 276 unsigned long *valid_mask, 277 unsigned int ngpios); 278 279 /** 280 * @valid_mask: 281 * 282 * If not %NULL, holds bitmask of GPIOs which are valid to be included 283 * in IRQ domain of the chip. 284 */ 285 unsigned long *valid_mask; 286 287 /** 288 * @first: 289 * 290 * Required for static IRQ allocation. If set, irq_domain_add_simple() 291 * will allocate and map all IRQs during initialization. 292 */ 293 unsigned int first; 294 295 /** 296 * @irq_enable: 297 * 298 * Store old irq_chip irq_enable callback 299 */ 300 void (*irq_enable)(struct irq_data *data); 301 302 /** 303 * @irq_disable: 304 * 305 * Store old irq_chip irq_disable callback 306 */ 307 void (*irq_disable)(struct irq_data *data); 308 /** 309 * @irq_unmask: 310 * 311 * Store old irq_chip irq_unmask callback 312 */ 313 void (*irq_unmask)(struct irq_data *data); 314 315 /** 316 * @irq_mask: 317 * 318 * Store old irq_chip irq_mask callback 319 */ 320 void (*irq_mask)(struct irq_data *data); 321 }; 322 323 /** 324 * struct gpio_chip - abstract a GPIO controller 325 * @label: a functional name for the GPIO device, such as a part 326 * number or the name of the SoC IP-block implementing it. 327 * @gpiodev: the internal state holder, opaque struct 328 * @parent: optional parent device providing the GPIOs 329 * @fwnode: optional fwnode providing this controller's properties 330 * @owner: helps prevent removal of modules exporting active GPIOs 331 * @request: optional hook for chip-specific activation, such as 332 * enabling module power and clock; may sleep; must return 0 on success 333 * or negative error number on failure 334 * @free: optional hook for chip-specific deactivation, such as 335 * disabling module power and clock; may sleep 336 * @get_direction: returns direction for signal "offset", 0=out, 1=in, 337 * (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN), 338 * or negative error. It is recommended to always implement this 339 * function, even on input-only or output-only gpio chips. 340 * @direction_input: configures signal "offset" as input, returns 0 on success 341 * or a negative error number. This can be omitted on input-only or 342 * output-only gpio chips. 343 * @direction_output: configures signal "offset" as output, returns 0 on 344 * success or a negative error number. This can be omitted on input-only 345 * or output-only gpio chips. 346 * @get: returns value for signal "offset", 0=low, 1=high, or negative error 347 * @get_multiple: reads values for multiple signals defined by "mask" and 348 * stores them in "bits", returns 0 on success or negative error 349 * @set: **DEPRECATED** - please use set_rv() instead 350 * @set_multiple: **DEPRECATED** - please use set_multiple_rv() instead 351 * @set_rv: assigns output value for signal "offset", returns 0 on success or 352 * negative error value 353 * @set_multiple_rv: assigns output values for multiple signals defined by 354 * "mask", returns 0 on success or negative error value 355 * @set_config: optional hook for all kinds of settings. Uses the same 356 * packed config format as generic pinconf. Must return 0 on success and 357 * a negative error number on failure. 358 * @to_irq: optional hook supporting non-static gpiod_to_irq() mappings; 359 * implementation may not sleep 360 * @dbg_show: optional routine to show contents in debugfs; default code 361 * will be used when this is omitted, but custom code can show extra 362 * state (such as pullup/pulldown configuration). 363 * @init_valid_mask: optional routine to initialize @valid_mask, to be used if 364 * not all GPIOs are valid. 365 * @add_pin_ranges: optional routine to initialize pin ranges, to be used when 366 * requires special mapping of the pins that provides GPIO functionality. 367 * It is called after adding GPIO chip and before adding IRQ chip. 368 * @en_hw_timestamp: Dependent on GPIO chip, an optional routine to 369 * enable hardware timestamp. 370 * @dis_hw_timestamp: Dependent on GPIO chip, an optional routine to 371 * disable hardware timestamp. 372 * @base: identifies the first GPIO number handled by this chip; 373 * or, if negative during registration, requests dynamic ID allocation. 374 * DEPRECATION: providing anything non-negative and nailing the base 375 * offset of GPIO chips is deprecated. Please pass -1 as base to 376 * let gpiolib select the chip base in all possible cases. We want to 377 * get rid of the static GPIO number space in the long run. 378 * @ngpio: the number of GPIOs handled by this controller; the last GPIO 379 * handled is (base + ngpio - 1). 380 * @offset: when multiple gpio chips belong to the same device this 381 * can be used as offset within the device so friendly names can 382 * be properly assigned. 383 * @names: if set, must be an array of strings to use as alternative 384 * names for the GPIOs in this chip. Any entry in the array 385 * may be NULL if there is no alias for the GPIO, however the 386 * array must be @ngpio entries long. 387 * @can_sleep: flag must be set iff get()/set() methods sleep, as they 388 * must while accessing GPIO expander chips over I2C or SPI. This 389 * implies that if the chip supports IRQs, these IRQs need to be threaded 390 * as the chip access may sleep when e.g. reading out the IRQ status 391 * registers. 392 * @read_reg: reader function for generic GPIO 393 * @write_reg: writer function for generic GPIO 394 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing 395 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the 396 * generic GPIO core. It is for internal housekeeping only. 397 * @reg_dat: data (in) register for generic GPIO 398 * @reg_set: output set register (out=high) for generic GPIO 399 * @reg_clr: output clear register (out=low) for generic GPIO 400 * @reg_dir_out: direction out setting register for generic GPIO 401 * @reg_dir_in: direction in setting register for generic GPIO 402 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot 403 * be read and we need to rely on out internal state tracking. 404 * @bgpio_pinctrl: the generic GPIO uses a pin control backend. 405 * @bgpio_bits: number of register bits used for a generic GPIO i.e. 406 * <register width> * 8 407 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep 408 * shadowed and real data registers writes together. 409 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits 410 * safely. 411 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set 412 * direction safely. A "1" in this word means the line is set as 413 * output. 414 * 415 * A gpio_chip can help platforms abstract various sources of GPIOs so 416 * they can all be accessed through a common programming interface. 417 * Example sources would be SOC controllers, FPGAs, multifunction 418 * chips, dedicated GPIO expanders, and so on. 419 * 420 * Each chip controls a number of signals, identified in method calls 421 * by "offset" values in the range 0..(@ngpio - 1). When those signals 422 * are referenced through calls like gpio_get_value(gpio), the offset 423 * is calculated by subtracting @base from the gpio number. 424 */ 425 struct gpio_chip { 426 const char *label; 427 struct gpio_device *gpiodev; 428 struct device *parent; 429 struct fwnode_handle *fwnode; 430 struct module *owner; 431 432 int (*request)(struct gpio_chip *gc, 433 unsigned int offset); 434 void (*free)(struct gpio_chip *gc, 435 unsigned int offset); 436 int (*get_direction)(struct gpio_chip *gc, 437 unsigned int offset); 438 int (*direction_input)(struct gpio_chip *gc, 439 unsigned int offset); 440 int (*direction_output)(struct gpio_chip *gc, 441 unsigned int offset, int value); 442 int (*get)(struct gpio_chip *gc, 443 unsigned int offset); 444 int (*get_multiple)(struct gpio_chip *gc, 445 unsigned long *mask, 446 unsigned long *bits); 447 void (*set)(struct gpio_chip *gc, 448 unsigned int offset, int value); 449 void (*set_multiple)(struct gpio_chip *gc, 450 unsigned long *mask, 451 unsigned long *bits); 452 int (*set_rv)(struct gpio_chip *gc, 453 unsigned int offset, 454 int value); 455 int (*set_multiple_rv)(struct gpio_chip *gc, 456 unsigned long *mask, 457 unsigned long *bits); 458 int (*set_config)(struct gpio_chip *gc, 459 unsigned int offset, 460 unsigned long config); 461 int (*to_irq)(struct gpio_chip *gc, 462 unsigned int offset); 463 464 void (*dbg_show)(struct seq_file *s, 465 struct gpio_chip *gc); 466 467 int (*init_valid_mask)(struct gpio_chip *gc, 468 unsigned long *valid_mask, 469 unsigned int ngpios); 470 471 int (*add_pin_ranges)(struct gpio_chip *gc); 472 473 int (*en_hw_timestamp)(struct gpio_chip *gc, 474 u32 offset, 475 unsigned long flags); 476 int (*dis_hw_timestamp)(struct gpio_chip *gc, 477 u32 offset, 478 unsigned long flags); 479 int base; 480 u16 ngpio; 481 u16 offset; 482 const char *const *names; 483 bool can_sleep; 484 485 #if IS_ENABLED(CONFIG_GPIO_GENERIC) 486 unsigned long (*read_reg)(void __iomem *reg); 487 void (*write_reg)(void __iomem *reg, unsigned long data); 488 bool be_bits; 489 void __iomem *reg_dat; 490 void __iomem *reg_set; 491 void __iomem *reg_clr; 492 void __iomem *reg_dir_out; 493 void __iomem *reg_dir_in; 494 bool bgpio_dir_unreadable; 495 bool bgpio_pinctrl; 496 int bgpio_bits; 497 raw_spinlock_t bgpio_lock; 498 unsigned long bgpio_data; 499 unsigned long bgpio_dir; 500 #endif /* CONFIG_GPIO_GENERIC */ 501 502 #ifdef CONFIG_GPIOLIB_IRQCHIP 503 /* 504 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib 505 * to handle IRQs for most practical cases. 506 */ 507 508 /** 509 * @irq: 510 * 511 * Integrates interrupt chip functionality with the GPIO chip. Can be 512 * used to handle IRQs for most practical cases. 513 */ 514 struct gpio_irq_chip irq; 515 #endif /* CONFIG_GPIOLIB_IRQCHIP */ 516 517 /** 518 * @valid_mask: 519 * 520 * If not %NULL, holds bitmask of GPIOs which are valid to be used 521 * from the chip. 522 */ 523 unsigned long *valid_mask; 524 525 #if defined(CONFIG_OF_GPIO) 526 /* 527 * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in 528 * the device tree automatically may have an OF translation 529 */ 530 531 /** 532 * @of_gpio_n_cells: 533 * 534 * Number of cells used to form the GPIO specifier. The standard is 2 535 * cells: 536 * 537 * gpios = <&gpio offset flags>; 538 * 539 * some complex GPIO controllers instantiate more than one chip per 540 * device tree node and have 3 cells: 541 * 542 * gpios = <&gpio instance offset flags>; 543 * 544 * Legacy GPIO controllers may even have 1 cell: 545 * 546 * gpios = <&gpio offset>; 547 */ 548 unsigned int of_gpio_n_cells; 549 550 /** 551 * of_node_instance_match: 552 * 553 * Determine if a chip is the right instance. Must be implemented by 554 * any driver using more than one gpio_chip per device tree node. 555 * Returns true if gc is the instance indicated by i (which is the 556 * first cell in the phandles for GPIO lines and gpio-ranges). 557 */ 558 bool (*of_node_instance_match)(struct gpio_chip *gc, unsigned int i); 559 560 /** 561 * @of_xlate: 562 * 563 * Callback to translate a device tree GPIO specifier into a chip- 564 * relative GPIO number and flags. 565 */ 566 int (*of_xlate)(struct gpio_chip *gc, 567 const struct of_phandle_args *gpiospec, u32 *flags); 568 #endif /* CONFIG_OF_GPIO */ 569 }; 570 571 char *gpiochip_dup_line_label(struct gpio_chip *gc, unsigned int offset); 572 573 574 struct _gpiochip_for_each_data { 575 const char **label; 576 unsigned int *i; 577 }; 578 579 DEFINE_CLASS(_gpiochip_for_each_data, 580 struct _gpiochip_for_each_data, 581 if (*_T.label) kfree(*_T.label), 582 ({ 583 struct _gpiochip_for_each_data _data = { label, i }; 584 *_data.i = 0; 585 _data; 586 }), 587 const char **label, int *i) 588 589 /** 590 * for_each_hwgpio_in_range - Iterates over all GPIOs in a given range 591 * @_chip: Chip to iterate over. 592 * @_i: Loop counter. 593 * @_base: First GPIO in the ranger. 594 * @_size: Amount of GPIOs to check starting from @base. 595 * @_label: Place to store the address of the label if the GPIO is requested. 596 * Set to NULL for unused GPIOs. 597 */ 598 #define for_each_hwgpio_in_range(_chip, _i, _base, _size, _label) \ 599 for (CLASS(_gpiochip_for_each_data, _data)(&_label, &_i); \ 600 _i < _size; \ 601 _i++, kfree(_label), _label = NULL) \ 602 for_each_if(!IS_ERR(_label = gpiochip_dup_line_label(_chip, _base + _i))) 603 604 /** 605 * for_each_hwgpio - Iterates over all GPIOs for given chip. 606 * @_chip: Chip to iterate over. 607 * @_i: Loop counter. 608 * @_label: Place to store the address of the label if the GPIO is requested. 609 * Set to NULL for unused GPIOs. 610 */ 611 #define for_each_hwgpio(_chip, _i, _label) \ 612 for_each_hwgpio_in_range(_chip, _i, 0, _chip->ngpio, _label) 613 614 /** 615 * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range 616 * @_chip: the chip to query 617 * @_i: loop variable 618 * @_base: first GPIO in the range 619 * @_size: amount of GPIOs to check starting from @base 620 * @_label: label of current GPIO 621 */ 622 #define for_each_requested_gpio_in_range(_chip, _i, _base, _size, _label) \ 623 for_each_hwgpio_in_range(_chip, _i, _base, _size, _label) \ 624 for_each_if(_label) 625 626 /* Iterates over all requested GPIO of the given @chip */ 627 #define for_each_requested_gpio(chip, i, label) \ 628 for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label) 629 630 /* add/remove chips */ 631 int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data, 632 struct lock_class_key *lock_key, 633 struct lock_class_key *request_key); 634 635 /** 636 * gpiochip_add_data() - register a gpio_chip 637 * @gc: the chip to register, with gc->base initialized 638 * @data: driver-private data associated with this chip 639 * 640 * Context: potentially before irqs will work 641 * 642 * When gpiochip_add_data() is called very early during boot, so that GPIOs 643 * can be freely used, the gc->parent device must be registered before 644 * the gpio framework's arch_initcall(). Otherwise sysfs initialization 645 * for GPIOs will fail rudely. 646 * 647 * gpiochip_add_data() must only be called after gpiolib initialization, 648 * i.e. after core_initcall(). 649 * 650 * If gc->base is negative, this requests dynamic assignment of 651 * a range of valid GPIOs. 652 * 653 * Returns: 654 * A negative errno if the chip can't be registered, such as because the 655 * gc->base is invalid or already associated with a different chip. 656 * Otherwise it returns zero as a success code. 657 */ 658 #ifdef CONFIG_LOCKDEP 659 #define gpiochip_add_data(gc, data) ({ \ 660 static struct lock_class_key lock_key; \ 661 static struct lock_class_key request_key; \ 662 gpiochip_add_data_with_key(gc, data, &lock_key, \ 663 &request_key); \ 664 }) 665 #define devm_gpiochip_add_data(dev, gc, data) ({ \ 666 static struct lock_class_key lock_key; \ 667 static struct lock_class_key request_key; \ 668 devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \ 669 &request_key); \ 670 }) 671 #else 672 #define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL) 673 #define devm_gpiochip_add_data(dev, gc, data) \ 674 devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL) 675 #endif /* CONFIG_LOCKDEP */ 676 677 void gpiochip_remove(struct gpio_chip *gc); 678 int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, 679 void *data, struct lock_class_key *lock_key, 680 struct lock_class_key *request_key); 681 682 struct gpio_device *gpio_device_find(const void *data, 683 int (*match)(struct gpio_chip *gc, 684 const void *data)); 685 686 struct gpio_device *gpio_device_get(struct gpio_device *gdev); 687 void gpio_device_put(struct gpio_device *gdev); 688 689 DEFINE_FREE(gpio_device_put, struct gpio_device *, 690 if (!IS_ERR_OR_NULL(_T)) gpio_device_put(_T)) 691 692 struct device *gpio_device_to_device(struct gpio_device *gdev); 693 694 bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset); 695 int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset); 696 void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset); 697 void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset); 698 void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset); 699 700 /* irq_data versions of the above */ 701 int gpiochip_irq_reqres(struct irq_data *data); 702 void gpiochip_irq_relres(struct irq_data *data); 703 704 /* Paste this in your irq_chip structure */ 705 #define GPIOCHIP_IRQ_RESOURCE_HELPERS \ 706 .irq_request_resources = gpiochip_irq_reqres, \ 707 .irq_release_resources = gpiochip_irq_relres 708 709 static inline void gpio_irq_chip_set_chip(struct gpio_irq_chip *girq, 710 const struct irq_chip *chip) 711 { 712 /* Yes, dropping const is ugly, but it isn't like we have a choice */ 713 girq->chip = (struct irq_chip *)chip; 714 } 715 716 /* Line status inquiry for drivers */ 717 bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset); 718 bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset); 719 720 /* Sleep persistence inquiry for drivers */ 721 bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset); 722 bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset); 723 724 /* get driver data */ 725 void *gpiochip_get_data(struct gpio_chip *gc); 726 727 struct bgpio_pdata { 728 const char *label; 729 int base; 730 int ngpio; 731 }; 732 733 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 734 735 int gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc, 736 union gpio_irq_fwspec *gfwspec, 737 unsigned int parent_hwirq, 738 unsigned int parent_type); 739 int gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc, 740 union gpio_irq_fwspec *gfwspec, 741 unsigned int parent_hwirq, 742 unsigned int parent_type); 743 744 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ 745 746 int bgpio_init(struct gpio_chip *gc, struct device *dev, 747 unsigned long sz, void __iomem *dat, void __iomem *set, 748 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 749 unsigned long flags); 750 751 #define BGPIOF_BIG_ENDIAN BIT(0) 752 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */ 753 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */ 754 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3) 755 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */ 756 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */ 757 #define BGPIOF_NO_SET_ON_INPUT BIT(6) 758 #define BGPIOF_PINCTRL_BACKEND BIT(7) /* Call pinctrl direction setters */ 759 760 #ifdef CONFIG_GPIOLIB_IRQCHIP 761 int gpiochip_irqchip_add_domain(struct gpio_chip *gc, 762 struct irq_domain *domain); 763 #else 764 765 #include <asm/bug.h> 766 767 static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc, 768 struct irq_domain *domain) 769 { 770 WARN_ON(1); 771 return -EINVAL; 772 } 773 #endif 774 775 int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset); 776 void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset); 777 int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset, 778 unsigned long config); 779 780 /** 781 * struct gpio_pin_range - pin range controlled by a gpio chip 782 * @node: list for maintaining set of pin ranges, used internally 783 * @pctldev: pinctrl device which handles corresponding pins 784 * @range: actual range of pins controlled by a gpio controller 785 */ 786 struct gpio_pin_range { 787 struct list_head node; 788 struct pinctrl_dev *pctldev; 789 struct pinctrl_gpio_range range; 790 }; 791 792 #ifdef CONFIG_PINCTRL 793 794 int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, 795 unsigned int gpio_offset, unsigned int pin_offset, 796 unsigned int npins); 797 int gpiochip_add_pingroup_range(struct gpio_chip *gc, 798 struct pinctrl_dev *pctldev, 799 unsigned int gpio_offset, const char *pin_group); 800 void gpiochip_remove_pin_ranges(struct gpio_chip *gc); 801 802 #else /* ! CONFIG_PINCTRL */ 803 804 static inline int 805 gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, 806 unsigned int gpio_offset, unsigned int pin_offset, 807 unsigned int npins) 808 { 809 return 0; 810 } 811 static inline int 812 gpiochip_add_pingroup_range(struct gpio_chip *gc, 813 struct pinctrl_dev *pctldev, 814 unsigned int gpio_offset, const char *pin_group) 815 { 816 return 0; 817 } 818 819 static inline void 820 gpiochip_remove_pin_ranges(struct gpio_chip *gc) 821 { 822 } 823 824 #endif /* CONFIG_PINCTRL */ 825 826 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc, 827 unsigned int hwnum, 828 const char *label, 829 enum gpio_lookup_flags lflags, 830 enum gpiod_flags dflags); 831 void gpiochip_free_own_desc(struct gpio_desc *desc); 832 833 struct gpio_desc * 834 gpio_device_get_desc(struct gpio_device *gdev, unsigned int hwnum); 835 836 struct gpio_chip *gpio_device_get_chip(struct gpio_device *gdev); 837 838 #ifdef CONFIG_GPIOLIB 839 840 /* lock/unlock as IRQ */ 841 int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset); 842 void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset); 843 844 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc); 845 struct gpio_device *gpiod_to_gpio_device(struct gpio_desc *desc); 846 847 /* struct gpio_device getters */ 848 int gpio_device_get_base(struct gpio_device *gdev); 849 const char *gpio_device_get_label(struct gpio_device *gdev); 850 851 struct gpio_device *gpio_device_find_by_label(const char *label); 852 struct gpio_device *gpio_device_find_by_fwnode(const struct fwnode_handle *fwnode); 853 854 #else /* CONFIG_GPIOLIB */ 855 856 #include <asm/bug.h> 857 858 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc) 859 { 860 /* GPIO can never have been requested */ 861 WARN_ON(1); 862 return ERR_PTR(-ENODEV); 863 } 864 865 static inline struct gpio_device *gpiod_to_gpio_device(struct gpio_desc *desc) 866 { 867 WARN_ON(1); 868 return ERR_PTR(-ENODEV); 869 } 870 871 static inline int gpio_device_get_base(struct gpio_device *gdev) 872 { 873 WARN_ON(1); 874 return -ENODEV; 875 } 876 877 static inline const char *gpio_device_get_label(struct gpio_device *gdev) 878 { 879 WARN_ON(1); 880 return NULL; 881 } 882 883 static inline struct gpio_device *gpio_device_find_by_label(const char *label) 884 { 885 WARN_ON(1); 886 return NULL; 887 } 888 889 static inline struct gpio_device *gpio_device_find_by_fwnode(const struct fwnode_handle *fwnode) 890 { 891 WARN_ON(1); 892 return NULL; 893 } 894 895 static inline int gpiochip_lock_as_irq(struct gpio_chip *gc, 896 unsigned int offset) 897 { 898 WARN_ON(1); 899 return -EINVAL; 900 } 901 902 static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc, 903 unsigned int offset) 904 { 905 WARN_ON(1); 906 } 907 #endif /* CONFIG_GPIOLIB */ 908 909 #define for_each_gpiochip_node(dev, child) \ 910 device_for_each_child_node(dev, child) \ 911 for_each_if(fwnode_property_present(child, "gpio-controller")) 912 913 static inline unsigned int gpiochip_node_count(struct device *dev) 914 { 915 struct fwnode_handle *child; 916 unsigned int count = 0; 917 918 for_each_gpiochip_node(dev, child) 919 count++; 920 921 return count; 922 } 923 924 static inline struct fwnode_handle *gpiochip_node_get_first(struct device *dev) 925 { 926 struct fwnode_handle *fwnode; 927 928 for_each_gpiochip_node(dev, fwnode) 929 return fwnode; 930 931 return NULL; 932 } 933 934 #endif /* __LINUX_GPIO_DRIVER_H */ 935