1 #ifndef __LINUX_GPIO_DRIVER_H 2 #define __LINUX_GPIO_DRIVER_H 3 4 #include <linux/device.h> 5 #include <linux/types.h> 6 #include <linux/irq.h> 7 #include <linux/irqchip/chained_irq.h> 8 #include <linux/irqdomain.h> 9 #include <linux/lockdep.h> 10 #include <linux/pinctrl/pinctrl.h> 11 #include <linux/kconfig.h> 12 13 struct gpio_desc; 14 struct of_phandle_args; 15 struct device_node; 16 struct seq_file; 17 struct gpio_device; 18 struct module; 19 20 #ifdef CONFIG_GPIOLIB 21 22 /** 23 * enum single_ended_mode - mode for single ended operation 24 * @LINE_MODE_PUSH_PULL: normal mode for a GPIO line, drive actively high/low 25 * @LINE_MODE_OPEN_DRAIN: set line to be open drain 26 * @LINE_MODE_OPEN_SOURCE: set line to be open source 27 */ 28 enum single_ended_mode { 29 LINE_MODE_PUSH_PULL, 30 LINE_MODE_OPEN_DRAIN, 31 LINE_MODE_OPEN_SOURCE, 32 }; 33 34 /** 35 * struct gpio_chip - abstract a GPIO controller 36 * @label: a functional name for the GPIO device, such as a part 37 * number or the name of the SoC IP-block implementing it. 38 * @gpiodev: the internal state holder, opaque struct 39 * @parent: optional parent device providing the GPIOs 40 * @owner: helps prevent removal of modules exporting active GPIOs 41 * @request: optional hook for chip-specific activation, such as 42 * enabling module power and clock; may sleep 43 * @free: optional hook for chip-specific deactivation, such as 44 * disabling module power and clock; may sleep 45 * @get_direction: returns direction for signal "offset", 0=out, 1=in, 46 * (same as GPIOF_DIR_XXX), or negative error 47 * @direction_input: configures signal "offset" as input, or returns error 48 * @direction_output: configures signal "offset" as output, or returns error 49 * @get: returns value for signal "offset", 0=low, 1=high, or negative error 50 * @set: assigns output value for signal "offset" 51 * @set_multiple: assigns output values for multiple signals defined by "mask" 52 * @set_debounce: optional hook for setting debounce time for specified gpio in 53 * interrupt triggered gpio chips 54 * @set_single_ended: optional hook for setting a line as open drain, open 55 * source, or non-single ended (restore from open drain/source to normal 56 * push-pull mode) this should be implemented if the hardware supports 57 * open drain or open source settings. The GPIOlib will otherwise try 58 * to emulate open drain/source by not actively driving lines high/low 59 * if a consumer request this. The driver may return -ENOTSUPP if e.g. 60 * it supports just open drain but not open source and is called 61 * with LINE_MODE_OPEN_SOURCE as mode argument. 62 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings; 63 * implementation may not sleep 64 * @dbg_show: optional routine to show contents in debugfs; default code 65 * will be used when this is omitted, but custom code can show extra 66 * state (such as pullup/pulldown configuration). 67 * @base: identifies the first GPIO number handled by this chip; 68 * or, if negative during registration, requests dynamic ID allocation. 69 * DEPRECATION: providing anything non-negative and nailing the base 70 * offset of GPIO chips is deprecated. Please pass -1 as base to 71 * let gpiolib select the chip base in all possible cases. We want to 72 * get rid of the static GPIO number space in the long run. 73 * @ngpio: the number of GPIOs handled by this controller; the last GPIO 74 * handled is (base + ngpio - 1). 75 * @names: if set, must be an array of strings to use as alternative 76 * names for the GPIOs in this chip. Any entry in the array 77 * may be NULL if there is no alias for the GPIO, however the 78 * array must be @ngpio entries long. A name can include a single printk 79 * format specifier for an unsigned int. It is substituted by the actual 80 * number of the gpio. 81 * @can_sleep: flag must be set iff get()/set() methods sleep, as they 82 * must while accessing GPIO expander chips over I2C or SPI. This 83 * implies that if the chip supports IRQs, these IRQs need to be threaded 84 * as the chip access may sleep when e.g. reading out the IRQ status 85 * registers. 86 * @irq_not_threaded: flag must be set if @can_sleep is set but the 87 * IRQs don't need to be threaded 88 * @read_reg: reader function for generic GPIO 89 * @write_reg: writer function for generic GPIO 90 * @pin2mask: some generic GPIO controllers work with the big-endian bits 91 * notation, e.g. in a 8-bits register, GPIO7 is the least significant 92 * bit. This callback assigns the right bit mask. 93 * @reg_dat: data (in) register for generic GPIO 94 * @reg_set: output set register (out=high) for generic GPIO 95 * @reg_clk: output clear register (out=low) for generic GPIO 96 * @reg_dir: direction setting register for generic GPIO 97 * @bgpio_bits: number of register bits used for a generic GPIO i.e. 98 * <register width> * 8 99 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep 100 * shadowed and real data registers writes together. 101 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits 102 * safely. 103 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set 104 * direction safely. 105 * @irqchip: GPIO IRQ chip impl, provided by GPIO driver 106 * @irqdomain: Interrupt translation domain; responsible for mapping 107 * between GPIO hwirq number and linux irq number 108 * @irq_base: first linux IRQ number assigned to GPIO IRQ chip (deprecated) 109 * @irq_handler: the irq handler to use (often a predefined irq core function) 110 * for GPIO IRQs, provided by GPIO driver 111 * @irq_default_type: default IRQ triggering type applied during GPIO driver 112 * initialization, provided by GPIO driver 113 * @irq_parent: GPIO IRQ chip parent/bank linux irq number, 114 * provided by GPIO driver 115 * @irq_need_valid_mask: If set core allocates @irq_valid_mask with all 116 * bits set to one 117 * @irq_valid_mask: If not %NULL holds bitmask of GPIOs which are valid to 118 * be included in IRQ domain of the chip 119 * @lock_key: per GPIO IRQ chip lockdep class 120 * 121 * A gpio_chip can help platforms abstract various sources of GPIOs so 122 * they can all be accessed through a common programing interface. 123 * Example sources would be SOC controllers, FPGAs, multifunction 124 * chips, dedicated GPIO expanders, and so on. 125 * 126 * Each chip controls a number of signals, identified in method calls 127 * by "offset" values in the range 0..(@ngpio - 1). When those signals 128 * are referenced through calls like gpio_get_value(gpio), the offset 129 * is calculated by subtracting @base from the gpio number. 130 */ 131 struct gpio_chip { 132 const char *label; 133 struct gpio_device *gpiodev; 134 struct device *parent; 135 struct module *owner; 136 137 int (*request)(struct gpio_chip *chip, 138 unsigned offset); 139 void (*free)(struct gpio_chip *chip, 140 unsigned offset); 141 int (*get_direction)(struct gpio_chip *chip, 142 unsigned offset); 143 int (*direction_input)(struct gpio_chip *chip, 144 unsigned offset); 145 int (*direction_output)(struct gpio_chip *chip, 146 unsigned offset, int value); 147 int (*get)(struct gpio_chip *chip, 148 unsigned offset); 149 void (*set)(struct gpio_chip *chip, 150 unsigned offset, int value); 151 void (*set_multiple)(struct gpio_chip *chip, 152 unsigned long *mask, 153 unsigned long *bits); 154 int (*set_debounce)(struct gpio_chip *chip, 155 unsigned offset, 156 unsigned debounce); 157 int (*set_single_ended)(struct gpio_chip *chip, 158 unsigned offset, 159 enum single_ended_mode mode); 160 161 int (*to_irq)(struct gpio_chip *chip, 162 unsigned offset); 163 164 void (*dbg_show)(struct seq_file *s, 165 struct gpio_chip *chip); 166 int base; 167 u16 ngpio; 168 const char *const *names; 169 bool can_sleep; 170 bool irq_not_threaded; 171 172 #if IS_ENABLED(CONFIG_GPIO_GENERIC) 173 unsigned long (*read_reg)(void __iomem *reg); 174 void (*write_reg)(void __iomem *reg, unsigned long data); 175 unsigned long (*pin2mask)(struct gpio_chip *gc, unsigned int pin); 176 void __iomem *reg_dat; 177 void __iomem *reg_set; 178 void __iomem *reg_clr; 179 void __iomem *reg_dir; 180 int bgpio_bits; 181 spinlock_t bgpio_lock; 182 unsigned long bgpio_data; 183 unsigned long bgpio_dir; 184 #endif 185 186 #ifdef CONFIG_GPIOLIB_IRQCHIP 187 /* 188 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib 189 * to handle IRQs for most practical cases. 190 */ 191 struct irq_chip *irqchip; 192 struct irq_domain *irqdomain; 193 unsigned int irq_base; 194 irq_flow_handler_t irq_handler; 195 unsigned int irq_default_type; 196 int irq_parent; 197 bool irq_need_valid_mask; 198 unsigned long *irq_valid_mask; 199 struct lock_class_key *lock_key; 200 #endif 201 202 #if defined(CONFIG_OF_GPIO) 203 /* 204 * If CONFIG_OF is enabled, then all GPIO controllers described in the 205 * device tree automatically may have an OF translation 206 */ 207 struct device_node *of_node; 208 int of_gpio_n_cells; 209 int (*of_xlate)(struct gpio_chip *gc, 210 const struct of_phandle_args *gpiospec, u32 *flags); 211 #endif 212 }; 213 214 extern const char *gpiochip_is_requested(struct gpio_chip *chip, 215 unsigned offset); 216 217 /* add/remove chips */ 218 extern int gpiochip_add_data(struct gpio_chip *chip, void *data); 219 static inline int gpiochip_add(struct gpio_chip *chip) 220 { 221 return gpiochip_add_data(chip, NULL); 222 } 223 extern void gpiochip_remove(struct gpio_chip *chip); 224 extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip, 225 void *data); 226 extern void devm_gpiochip_remove(struct device *dev, struct gpio_chip *chip); 227 228 extern struct gpio_chip *gpiochip_find(void *data, 229 int (*match)(struct gpio_chip *chip, void *data)); 230 231 /* lock/unlock as IRQ */ 232 int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset); 233 void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset); 234 bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset); 235 236 /* Line status inquiry for drivers */ 237 bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset); 238 bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset); 239 240 /* get driver data */ 241 void *gpiochip_get_data(struct gpio_chip *chip); 242 243 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc); 244 245 struct bgpio_pdata { 246 const char *label; 247 int base; 248 int ngpio; 249 }; 250 251 #if IS_ENABLED(CONFIG_GPIO_GENERIC) 252 253 int bgpio_init(struct gpio_chip *gc, struct device *dev, 254 unsigned long sz, void __iomem *dat, void __iomem *set, 255 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 256 unsigned long flags); 257 258 #define BGPIOF_BIG_ENDIAN BIT(0) 259 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */ 260 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */ 261 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3) 262 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */ 263 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */ 264 265 #endif 266 267 #ifdef CONFIG_GPIOLIB_IRQCHIP 268 269 void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip, 270 struct irq_chip *irqchip, 271 int parent_irq, 272 irq_flow_handler_t parent_handler); 273 274 int _gpiochip_irqchip_add(struct gpio_chip *gpiochip, 275 struct irq_chip *irqchip, 276 unsigned int first_irq, 277 irq_flow_handler_t handler, 278 unsigned int type, 279 struct lock_class_key *lock_key); 280 281 #ifdef CONFIG_LOCKDEP 282 #define gpiochip_irqchip_add(...) \ 283 ( \ 284 ({ \ 285 static struct lock_class_key _key; \ 286 _gpiochip_irqchip_add(__VA_ARGS__, &_key); \ 287 }) \ 288 ) 289 #else 290 #define gpiochip_irqchip_add(...) \ 291 _gpiochip_irqchip_add(__VA_ARGS__, NULL) 292 #endif 293 294 #endif /* CONFIG_GPIOLIB_IRQCHIP */ 295 296 int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset); 297 void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset); 298 299 #ifdef CONFIG_PINCTRL 300 301 /** 302 * struct gpio_pin_range - pin range controlled by a gpio chip 303 * @head: list for maintaining set of pin ranges, used internally 304 * @pctldev: pinctrl device which handles corresponding pins 305 * @range: actual range of pins controlled by a gpio controller 306 */ 307 308 struct gpio_pin_range { 309 struct list_head node; 310 struct pinctrl_dev *pctldev; 311 struct pinctrl_gpio_range range; 312 }; 313 314 int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, 315 unsigned int gpio_offset, unsigned int pin_offset, 316 unsigned int npins); 317 int gpiochip_add_pingroup_range(struct gpio_chip *chip, 318 struct pinctrl_dev *pctldev, 319 unsigned int gpio_offset, const char *pin_group); 320 void gpiochip_remove_pin_ranges(struct gpio_chip *chip); 321 322 #else 323 324 static inline int 325 gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, 326 unsigned int gpio_offset, unsigned int pin_offset, 327 unsigned int npins) 328 { 329 return 0; 330 } 331 static inline int 332 gpiochip_add_pingroup_range(struct gpio_chip *chip, 333 struct pinctrl_dev *pctldev, 334 unsigned int gpio_offset, const char *pin_group) 335 { 336 return 0; 337 } 338 339 static inline void 340 gpiochip_remove_pin_ranges(struct gpio_chip *chip) 341 { 342 } 343 344 #endif /* CONFIG_PINCTRL */ 345 346 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum, 347 const char *label); 348 void gpiochip_free_own_desc(struct gpio_desc *desc); 349 350 #else /* CONFIG_GPIOLIB */ 351 352 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc) 353 { 354 /* GPIO can never have been requested */ 355 WARN_ON(1); 356 return ERR_PTR(-ENODEV); 357 } 358 359 #endif /* CONFIG_GPIOLIB */ 360 361 #endif 362