1 /* Freescale Integrated Flash Controller 2 * 3 * Copyright 2011 Freescale Semiconductor, Inc 4 * 5 * Author: Dipen Dudhat <[email protected]> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 22 #ifndef __ASM_FSL_IFC_H 23 #define __ASM_FSL_IFC_H 24 25 #include <linux/compiler.h> 26 #include <linux/types.h> 27 #include <linux/io.h> 28 29 #include <linux/of_platform.h> 30 #include <linux/interrupt.h> 31 32 #define FSL_IFC_BANK_COUNT 4 33 34 /* 35 * CSPR - Chip Select Property Register 36 */ 37 #define CSPR_BA 0xFFFF0000 38 #define CSPR_BA_SHIFT 16 39 #define CSPR_PORT_SIZE 0x00000180 40 #define CSPR_PORT_SIZE_SHIFT 7 41 /* Port Size 8 bit */ 42 #define CSPR_PORT_SIZE_8 0x00000080 43 /* Port Size 16 bit */ 44 #define CSPR_PORT_SIZE_16 0x00000100 45 /* Port Size 32 bit */ 46 #define CSPR_PORT_SIZE_32 0x00000180 47 /* Write Protect */ 48 #define CSPR_WP 0x00000040 49 #define CSPR_WP_SHIFT 6 50 /* Machine Select */ 51 #define CSPR_MSEL 0x00000006 52 #define CSPR_MSEL_SHIFT 1 53 /* NOR */ 54 #define CSPR_MSEL_NOR 0x00000000 55 /* NAND */ 56 #define CSPR_MSEL_NAND 0x00000002 57 /* GPCM */ 58 #define CSPR_MSEL_GPCM 0x00000004 59 /* Bank Valid */ 60 #define CSPR_V 0x00000001 61 #define CSPR_V_SHIFT 0 62 63 /* 64 * Address Mask Register 65 */ 66 #define IFC_AMASK_MASK 0xFFFF0000 67 #define IFC_AMASK_SHIFT 16 68 #define IFC_AMASK(n) (IFC_AMASK_MASK << \ 69 (__ilog2(n) - IFC_AMASK_SHIFT)) 70 71 /* 72 * Chip Select Option Register IFC_NAND Machine 73 */ 74 /* Enable ECC Encoder */ 75 #define CSOR_NAND_ECC_ENC_EN 0x80000000 76 #define CSOR_NAND_ECC_MODE_MASK 0x30000000 77 /* 4 bit correction per 520 Byte sector */ 78 #define CSOR_NAND_ECC_MODE_4 0x00000000 79 /* 8 bit correction per 528 Byte sector */ 80 #define CSOR_NAND_ECC_MODE_8 0x10000000 81 /* Enable ECC Decoder */ 82 #define CSOR_NAND_ECC_DEC_EN 0x04000000 83 /* Row Address Length */ 84 #define CSOR_NAND_RAL_MASK 0x01800000 85 #define CSOR_NAND_RAL_SHIFT 20 86 #define CSOR_NAND_RAL_1 0x00000000 87 #define CSOR_NAND_RAL_2 0x00800000 88 #define CSOR_NAND_RAL_3 0x01000000 89 #define CSOR_NAND_RAL_4 0x01800000 90 /* Page Size 512b, 2k, 4k */ 91 #define CSOR_NAND_PGS_MASK 0x00180000 92 #define CSOR_NAND_PGS_SHIFT 16 93 #define CSOR_NAND_PGS_512 0x00000000 94 #define CSOR_NAND_PGS_2K 0x00080000 95 #define CSOR_NAND_PGS_4K 0x00100000 96 #define CSOR_NAND_PGS_8K 0x00180000 97 /* Spare region Size */ 98 #define CSOR_NAND_SPRZ_MASK 0x0000E000 99 #define CSOR_NAND_SPRZ_SHIFT 13 100 #define CSOR_NAND_SPRZ_16 0x00000000 101 #define CSOR_NAND_SPRZ_64 0x00002000 102 #define CSOR_NAND_SPRZ_128 0x00004000 103 #define CSOR_NAND_SPRZ_210 0x00006000 104 #define CSOR_NAND_SPRZ_218 0x00008000 105 #define CSOR_NAND_SPRZ_224 0x0000A000 106 #define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 107 /* Pages Per Block */ 108 #define CSOR_NAND_PB_MASK 0x00000700 109 #define CSOR_NAND_PB_SHIFT 8 110 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) 111 /* Time for Read Enable High to Output High Impedance */ 112 #define CSOR_NAND_TRHZ_MASK 0x0000001C 113 #define CSOR_NAND_TRHZ_SHIFT 2 114 #define CSOR_NAND_TRHZ_20 0x00000000 115 #define CSOR_NAND_TRHZ_40 0x00000004 116 #define CSOR_NAND_TRHZ_60 0x00000008 117 #define CSOR_NAND_TRHZ_80 0x0000000C 118 #define CSOR_NAND_TRHZ_100 0x00000010 119 /* Buffer control disable */ 120 #define CSOR_NAND_BCTLD 0x00000001 121 122 /* 123 * Chip Select Option Register - NOR Flash Mode 124 */ 125 /* Enable Address shift Mode */ 126 #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 127 /* Page Read Enable from NOR device */ 128 #define CSOR_NOR_PGRD_EN 0x10000000 129 /* AVD Toggle Enable during Burst Program */ 130 #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 131 /* Address Data Multiplexing Shift */ 132 #define CSOR_NOR_ADM_MASK 0x0003E000 133 #define CSOR_NOR_ADM_SHIFT_SHIFT 13 134 #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) 135 /* Type of the NOR device hooked */ 136 #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 137 #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 138 /* Time for Read Enable High to Output High Impedance */ 139 #define CSOR_NOR_TRHZ_MASK 0x0000001C 140 #define CSOR_NOR_TRHZ_SHIFT 2 141 #define CSOR_NOR_TRHZ_20 0x00000000 142 #define CSOR_NOR_TRHZ_40 0x00000004 143 #define CSOR_NOR_TRHZ_60 0x00000008 144 #define CSOR_NOR_TRHZ_80 0x0000000C 145 #define CSOR_NOR_TRHZ_100 0x00000010 146 /* Buffer control disable */ 147 #define CSOR_NOR_BCTLD 0x00000001 148 149 /* 150 * Chip Select Option Register - GPCM Mode 151 */ 152 /* GPCM Mode - Normal */ 153 #define CSOR_GPCM_GPMODE_NORMAL 0x00000000 154 /* GPCM Mode - GenericASIC */ 155 #define CSOR_GPCM_GPMODE_ASIC 0x80000000 156 /* Parity Mode odd/even */ 157 #define CSOR_GPCM_PARITY_EVEN 0x40000000 158 /* Parity Checking enable/disable */ 159 #define CSOR_GPCM_PAR_EN 0x20000000 160 /* GPCM Timeout Count */ 161 #define CSOR_GPCM_GPTO_MASK 0x0F000000 162 #define CSOR_GPCM_GPTO_SHIFT 24 163 #define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) 164 /* GPCM External Access Termination mode for read access */ 165 #define CSOR_GPCM_RGETA_EXT 0x00080000 166 /* GPCM External Access Termination mode for write access */ 167 #define CSOR_GPCM_WGETA_EXT 0x00040000 168 /* Address Data Multiplexing Shift */ 169 #define CSOR_GPCM_ADM_MASK 0x0003E000 170 #define CSOR_GPCM_ADM_SHIFT_SHIFT 13 171 #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) 172 /* Generic ASIC Parity error indication delay */ 173 #define CSOR_GPCM_GAPERRD_MASK 0x00000180 174 #define CSOR_GPCM_GAPERRD_SHIFT 7 175 #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) 176 /* Time for Read Enable High to Output High Impedance */ 177 #define CSOR_GPCM_TRHZ_MASK 0x0000001C 178 #define CSOR_GPCM_TRHZ_20 0x00000000 179 #define CSOR_GPCM_TRHZ_40 0x00000004 180 #define CSOR_GPCM_TRHZ_60 0x00000008 181 #define CSOR_GPCM_TRHZ_80 0x0000000C 182 #define CSOR_GPCM_TRHZ_100 0x00000010 183 /* Buffer control disable */ 184 #define CSOR_GPCM_BCTLD 0x00000001 185 186 /* 187 * Ready Busy Status Register (RB_STAT) 188 */ 189 /* CSn is READY */ 190 #define IFC_RB_STAT_READY_CS0 0x80000000 191 #define IFC_RB_STAT_READY_CS1 0x40000000 192 #define IFC_RB_STAT_READY_CS2 0x20000000 193 #define IFC_RB_STAT_READY_CS3 0x10000000 194 195 /* 196 * General Control Register (GCR) 197 */ 198 #define IFC_GCR_MASK 0x8000F800 199 /* reset all IFC hardware */ 200 #define IFC_GCR_SOFT_RST_ALL 0x80000000 201 /* Turnaroud Time of external buffer */ 202 #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 203 #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 204 205 /* 206 * Common Event and Error Status Register (CM_EVTER_STAT) 207 */ 208 /* Chip select error */ 209 #define IFC_CM_EVTER_STAT_CSER 0x80000000 210 211 /* 212 * Common Event and Error Enable Register (CM_EVTER_EN) 213 */ 214 /* Chip select error checking enable */ 215 #define IFC_CM_EVTER_EN_CSEREN 0x80000000 216 217 /* 218 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) 219 */ 220 /* Chip select error interrupt enable */ 221 #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 222 223 /* 224 * Common Transfer Error Attribute Register-0 (CM_ERATTR0) 225 */ 226 /* transaction type of error Read/Write */ 227 #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 228 #define IFC_CM_ERATTR0_ERAID 0x0FF00000 229 #define IFC_CM_ERATTR0_ERAID_SHIFT 20 230 #define IFC_CM_ERATTR0_ESRCID 0x0000FF00 231 #define IFC_CM_ERATTR0_ESRCID_SHIFT 8 232 233 /* 234 * Clock Control Register (CCR) 235 */ 236 #define IFC_CCR_MASK 0x0F0F8800 237 /* Clock division ratio */ 238 #define IFC_CCR_CLK_DIV_MASK 0x0F000000 239 #define IFC_CCR_CLK_DIV_SHIFT 24 240 #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) 241 /* IFC Clock Delay */ 242 #define IFC_CCR_CLK_DLY_MASK 0x000F0000 243 #define IFC_CCR_CLK_DLY_SHIFT 16 244 #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) 245 /* Invert IFC clock before sending out */ 246 #define IFC_CCR_INV_CLK_EN 0x00008000 247 /* Fedback IFC Clock */ 248 #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 249 250 /* 251 * Clock Status Register (CSR) 252 */ 253 /* Clk is stable */ 254 #define IFC_CSR_CLK_STAT_STABLE 0x80000000 255 256 /* 257 * IFC_NAND Machine Specific Registers 258 */ 259 /* 260 * NAND Configuration Register (NCFGR) 261 */ 262 /* Auto Boot Mode */ 263 #define IFC_NAND_NCFGR_BOOT 0x80000000 264 /* Addressing Mode-ROW0+n/COL0 */ 265 #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 266 /* Addressing Mode-ROW0+n/COL0+n */ 267 #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 268 /* Number of loop iterations of FIR sequences for multi page operations */ 269 #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 270 #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 271 #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) 272 /* Number of wait cycles */ 273 #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF 274 #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 275 276 /* 277 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) 278 */ 279 /* General purpose FCM flash command bytes CMD0-CMD7 */ 280 #define IFC_NAND_FCR0_CMD0 0xFF000000 281 #define IFC_NAND_FCR0_CMD0_SHIFT 24 282 #define IFC_NAND_FCR0_CMD1 0x00FF0000 283 #define IFC_NAND_FCR0_CMD1_SHIFT 16 284 #define IFC_NAND_FCR0_CMD2 0x0000FF00 285 #define IFC_NAND_FCR0_CMD2_SHIFT 8 286 #define IFC_NAND_FCR0_CMD3 0x000000FF 287 #define IFC_NAND_FCR0_CMD3_SHIFT 0 288 #define IFC_NAND_FCR1_CMD4 0xFF000000 289 #define IFC_NAND_FCR1_CMD4_SHIFT 24 290 #define IFC_NAND_FCR1_CMD5 0x00FF0000 291 #define IFC_NAND_FCR1_CMD5_SHIFT 16 292 #define IFC_NAND_FCR1_CMD6 0x0000FF00 293 #define IFC_NAND_FCR1_CMD6_SHIFT 8 294 #define IFC_NAND_FCR1_CMD7 0x000000FF 295 #define IFC_NAND_FCR1_CMD7_SHIFT 0 296 297 /* 298 * Flash ROW and COL Address Register (ROWn, COLn) 299 */ 300 /* Main/spare region locator */ 301 #define IFC_NAND_COL_MS 0x80000000 302 /* Column Address */ 303 #define IFC_NAND_COL_CA_MASK 0x00000FFF 304 305 /* 306 * NAND Flash Byte Count Register (NAND_BC) 307 */ 308 /* Byte Count for read/Write */ 309 #define IFC_NAND_BC 0x000001FF 310 311 /* 312 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) 313 */ 314 /* NAND Machine specific opcodes OP0-OP14*/ 315 #define IFC_NAND_FIR0_OP0 0xFC000000 316 #define IFC_NAND_FIR0_OP0_SHIFT 26 317 #define IFC_NAND_FIR0_OP1 0x03F00000 318 #define IFC_NAND_FIR0_OP1_SHIFT 20 319 #define IFC_NAND_FIR0_OP2 0x000FC000 320 #define IFC_NAND_FIR0_OP2_SHIFT 14 321 #define IFC_NAND_FIR0_OP3 0x00003F00 322 #define IFC_NAND_FIR0_OP3_SHIFT 8 323 #define IFC_NAND_FIR0_OP4 0x000000FC 324 #define IFC_NAND_FIR0_OP4_SHIFT 2 325 #define IFC_NAND_FIR1_OP5 0xFC000000 326 #define IFC_NAND_FIR1_OP5_SHIFT 26 327 #define IFC_NAND_FIR1_OP6 0x03F00000 328 #define IFC_NAND_FIR1_OP6_SHIFT 20 329 #define IFC_NAND_FIR1_OP7 0x000FC000 330 #define IFC_NAND_FIR1_OP7_SHIFT 14 331 #define IFC_NAND_FIR1_OP8 0x00003F00 332 #define IFC_NAND_FIR1_OP8_SHIFT 8 333 #define IFC_NAND_FIR1_OP9 0x000000FC 334 #define IFC_NAND_FIR1_OP9_SHIFT 2 335 #define IFC_NAND_FIR2_OP10 0xFC000000 336 #define IFC_NAND_FIR2_OP10_SHIFT 26 337 #define IFC_NAND_FIR2_OP11 0x03F00000 338 #define IFC_NAND_FIR2_OP11_SHIFT 20 339 #define IFC_NAND_FIR2_OP12 0x000FC000 340 #define IFC_NAND_FIR2_OP12_SHIFT 14 341 #define IFC_NAND_FIR2_OP13 0x00003F00 342 #define IFC_NAND_FIR2_OP13_SHIFT 8 343 #define IFC_NAND_FIR2_OP14 0x000000FC 344 #define IFC_NAND_FIR2_OP14_SHIFT 2 345 346 /* 347 * Instruction opcodes to be programmed 348 * in FIR registers- 6bits 349 */ 350 enum ifc_nand_fir_opcodes { 351 IFC_FIR_OP_NOP, 352 IFC_FIR_OP_CA0, 353 IFC_FIR_OP_CA1, 354 IFC_FIR_OP_CA2, 355 IFC_FIR_OP_CA3, 356 IFC_FIR_OP_RA0, 357 IFC_FIR_OP_RA1, 358 IFC_FIR_OP_RA2, 359 IFC_FIR_OP_RA3, 360 IFC_FIR_OP_CMD0, 361 IFC_FIR_OP_CMD1, 362 IFC_FIR_OP_CMD2, 363 IFC_FIR_OP_CMD3, 364 IFC_FIR_OP_CMD4, 365 IFC_FIR_OP_CMD5, 366 IFC_FIR_OP_CMD6, 367 IFC_FIR_OP_CMD7, 368 IFC_FIR_OP_CW0, 369 IFC_FIR_OP_CW1, 370 IFC_FIR_OP_CW2, 371 IFC_FIR_OP_CW3, 372 IFC_FIR_OP_CW4, 373 IFC_FIR_OP_CW5, 374 IFC_FIR_OP_CW6, 375 IFC_FIR_OP_CW7, 376 IFC_FIR_OP_WBCD, 377 IFC_FIR_OP_RBCD, 378 IFC_FIR_OP_BTRD, 379 IFC_FIR_OP_RDSTAT, 380 IFC_FIR_OP_NWAIT, 381 IFC_FIR_OP_WFR, 382 IFC_FIR_OP_SBRD, 383 IFC_FIR_OP_UA, 384 IFC_FIR_OP_RB, 385 }; 386 387 /* 388 * NAND Chip Select Register (NAND_CSEL) 389 */ 390 #define IFC_NAND_CSEL 0x0C000000 391 #define IFC_NAND_CSEL_SHIFT 26 392 #define IFC_NAND_CSEL_CS0 0x00000000 393 #define IFC_NAND_CSEL_CS1 0x04000000 394 #define IFC_NAND_CSEL_CS2 0x08000000 395 #define IFC_NAND_CSEL_CS3 0x0C000000 396 397 /* 398 * NAND Operation Sequence Start (NANDSEQ_STRT) 399 */ 400 /* NAND Flash Operation Start */ 401 #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 402 /* Automatic Erase */ 403 #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 404 /* Automatic Program */ 405 #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 406 /* Automatic Copyback */ 407 #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 408 /* Automatic Read Operation */ 409 #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 410 /* Automatic Status Read */ 411 #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 412 413 /* 414 * NAND Event and Error Status Register (NAND_EVTER_STAT) 415 */ 416 /* Operation Complete */ 417 #define IFC_NAND_EVTER_STAT_OPC 0x80000000 418 /* Flash Timeout Error */ 419 #define IFC_NAND_EVTER_STAT_FTOER 0x08000000 420 /* Write Protect Error */ 421 #define IFC_NAND_EVTER_STAT_WPER 0x04000000 422 /* ECC Error */ 423 #define IFC_NAND_EVTER_STAT_ECCER 0x02000000 424 /* RCW Load Done */ 425 #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 426 /* Boot Loadr Done */ 427 #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 428 /* Bad Block Indicator search select */ 429 #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 430 431 /* 432 * NAND Flash Page Read Completion Event Status Register 433 * (PGRDCMPL_EVT_STAT) 434 */ 435 #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 436 /* Small Page 0-15 Done */ 437 #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) 438 /* Large Page(2K) 0-3 Done */ 439 #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) 440 /* Large Page(4K) 0-1 Done */ 441 #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) 442 443 /* 444 * NAND Event and Error Enable Register (NAND_EVTER_EN) 445 */ 446 /* Operation complete event enable */ 447 #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 448 /* Page read complete event enable */ 449 #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 450 /* Flash Timeout error enable */ 451 #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 452 /* Write Protect error enable */ 453 #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 454 /* ECC error logging enable */ 455 #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 456 457 /* 458 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) 459 */ 460 /* Enable interrupt for operation complete */ 461 #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 462 /* Enable interrupt for Page read complete */ 463 #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 464 /* Enable interrupt for Flash timeout error */ 465 #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 466 /* Enable interrupt for Write protect error */ 467 #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 468 /* Enable interrupt for ECC error*/ 469 #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 470 471 /* 472 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) 473 */ 474 #define IFC_NAND_ERATTR0_MASK 0x0C080000 475 /* Error on CS0-3 for NAND */ 476 #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 477 #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 478 #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 479 #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 480 /* Transaction type of error Read/Write */ 481 #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 482 483 /* 484 * NAND Flash Status Register (NAND_FSR) 485 */ 486 /* First byte of data read from read status op */ 487 #define IFC_NAND_NFSR_RS0 0xFF000000 488 /* Second byte of data read from read status op */ 489 #define IFC_NAND_NFSR_RS1 0x00FF0000 490 491 /* 492 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) 493 */ 494 /* Number of ECC errors on sector n (n = 0-15) */ 495 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 496 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 497 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 498 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 499 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 500 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 501 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F 502 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 503 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 504 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 505 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 506 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 507 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 508 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 509 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F 510 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 511 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 512 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 513 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 514 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 515 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 516 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 517 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F 518 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 519 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 520 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 521 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 522 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 523 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 524 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 525 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F 526 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 527 528 /* 529 * NAND Control Register (NANDCR) 530 */ 531 #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 532 #define IFC_NAND_NCR_FTOCNT_SHIFT 25 533 #define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) 534 535 /* 536 * NAND_AUTOBOOT_TRGR 537 */ 538 /* Trigger RCW load */ 539 #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 540 /* Trigget Auto Boot */ 541 #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 542 543 /* 544 * NAND_MDR 545 */ 546 /* 1st read data byte when opcode SBRD */ 547 #define IFC_NAND_MDR_RDATA0 0xFF000000 548 /* 2nd read data byte when opcode SBRD */ 549 #define IFC_NAND_MDR_RDATA1 0x00FF0000 550 551 /* 552 * NOR Machine Specific Registers 553 */ 554 /* 555 * NOR Event and Error Status Register (NOR_EVTER_STAT) 556 */ 557 /* NOR Command Sequence Operation Complete */ 558 #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 559 /* Write Protect Error */ 560 #define IFC_NOR_EVTER_STAT_WPER 0x04000000 561 /* Command Sequence Timeout Error */ 562 #define IFC_NOR_EVTER_STAT_STOER 0x01000000 563 564 /* 565 * NOR Event and Error Enable Register (NOR_EVTER_EN) 566 */ 567 /* NOR Command Seq complete event enable */ 568 #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 569 /* Write Protect Error Checking Enable */ 570 #define IFC_NOR_EVTER_EN_WPEREN 0x04000000 571 /* Timeout Error Enable */ 572 #define IFC_NOR_EVTER_EN_STOEREN 0x01000000 573 574 /* 575 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) 576 */ 577 /* Enable interrupt for OPC complete */ 578 #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 579 /* Enable interrupt for write protect error */ 580 #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 581 /* Enable interrupt for timeout error */ 582 #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 583 584 /* 585 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) 586 */ 587 /* Source ID for error transaction */ 588 #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 589 /* AXI ID for error transation */ 590 #define IFC_NOR_ERATTR0_ERAID 0x000FF000 591 /* Chip select corresponds to NOR error */ 592 #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 593 #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 594 #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 595 #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 596 /* Type of transaction read/write */ 597 #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 598 599 /* 600 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) 601 */ 602 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 603 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 604 605 /* 606 * NOR Control Register (NORCR) 607 */ 608 #define IFC_NORCR_MASK 0x0F0F0000 609 /* No. of Address/Data Phase */ 610 #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 611 #define IFC_NORCR_NUM_PHASE_SHIFT 24 612 #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) 613 /* Sequence Timeout Count */ 614 #define IFC_NORCR_STOCNT_MASK 0x000F0000 615 #define IFC_NORCR_STOCNT_SHIFT 16 616 #define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) 617 618 /* 619 * GPCM Machine specific registers 620 */ 621 /* 622 * GPCM Event and Error Status Register (GPCM_EVTER_STAT) 623 */ 624 /* Timeout error */ 625 #define IFC_GPCM_EVTER_STAT_TOER 0x04000000 626 /* Parity error */ 627 #define IFC_GPCM_EVTER_STAT_PER 0x01000000 628 629 /* 630 * GPCM Event and Error Enable Register (GPCM_EVTER_EN) 631 */ 632 /* Timeout error enable */ 633 #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 634 /* Parity error enable */ 635 #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 636 637 /* 638 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) 639 */ 640 /* Enable Interrupt for timeout error */ 641 #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 642 /* Enable Interrupt for Parity error */ 643 #define IFC_GPCM_EEIER_PERIR_EN 0x01000000 644 645 /* 646 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) 647 */ 648 /* Source ID for error transaction */ 649 #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 650 /* AXI ID for error transaction */ 651 #define IFC_GPCM_ERATTR0_ERAID 0x000FF000 652 /* Chip select corresponds to GPCM error */ 653 #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 654 #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 655 #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 656 #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 657 /* Type of transaction read/Write */ 658 #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 659 660 /* 661 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) 662 */ 663 /* On which beat of address/data parity error is observed */ 664 #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 665 /* Parity Error on byte */ 666 #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 667 /* Parity Error reported in addr or data phase */ 668 #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 669 670 /* 671 * GPCM Status Register (GPCM_STAT) 672 */ 673 #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ 674 675 /* 676 * IFC Controller NAND Machine registers 677 */ 678 struct fsl_ifc_nand { 679 __be32 ncfgr; 680 u32 res1[0x4]; 681 __be32 nand_fcr0; 682 __be32 nand_fcr1; 683 u32 res2[0x8]; 684 __be32 row0; 685 u32 res3; 686 __be32 col0; 687 u32 res4; 688 __be32 row1; 689 u32 res5; 690 __be32 col1; 691 u32 res6; 692 __be32 row2; 693 u32 res7; 694 __be32 col2; 695 u32 res8; 696 __be32 row3; 697 u32 res9; 698 __be32 col3; 699 u32 res10[0x24]; 700 __be32 nand_fbcr; 701 u32 res11; 702 __be32 nand_fir0; 703 __be32 nand_fir1; 704 __be32 nand_fir2; 705 u32 res12[0x10]; 706 __be32 nand_csel; 707 u32 res13; 708 __be32 nandseq_strt; 709 u32 res14; 710 __be32 nand_evter_stat; 711 u32 res15; 712 __be32 pgrdcmpl_evt_stat; 713 u32 res16[0x2]; 714 __be32 nand_evter_en; 715 u32 res17[0x2]; 716 __be32 nand_evter_intr_en; 717 u32 res18[0x2]; 718 __be32 nand_erattr0; 719 __be32 nand_erattr1; 720 u32 res19[0x10]; 721 __be32 nand_fsr; 722 u32 res20; 723 __be32 nand_eccstat[4]; 724 u32 res21[0x20]; 725 __be32 nanndcr; 726 u32 res22[0x2]; 727 __be32 nand_autoboot_trgr; 728 u32 res23; 729 __be32 nand_mdr; 730 u32 res24[0x5C]; 731 }; 732 733 /* 734 * IFC controller NOR Machine registers 735 */ 736 struct fsl_ifc_nor { 737 __be32 nor_evter_stat; 738 u32 res1[0x2]; 739 __be32 nor_evter_en; 740 u32 res2[0x2]; 741 __be32 nor_evter_intr_en; 742 u32 res3[0x2]; 743 __be32 nor_erattr0; 744 __be32 nor_erattr1; 745 __be32 nor_erattr2; 746 u32 res4[0x4]; 747 __be32 norcr; 748 u32 res5[0xEF]; 749 }; 750 751 /* 752 * IFC controller GPCM Machine registers 753 */ 754 struct fsl_ifc_gpcm { 755 __be32 gpcm_evter_stat; 756 u32 res1[0x2]; 757 __be32 gpcm_evter_en; 758 u32 res2[0x2]; 759 __be32 gpcm_evter_intr_en; 760 u32 res3[0x2]; 761 __be32 gpcm_erattr0; 762 __be32 gpcm_erattr1; 763 __be32 gpcm_erattr2; 764 __be32 gpcm_stat; 765 u32 res4[0x1F3]; 766 }; 767 768 /* 769 * IFC Controller Registers 770 */ 771 struct fsl_ifc_regs { 772 __be32 ifc_rev; 773 u32 res1[0x2]; 774 struct { 775 __be32 cspr_ext; 776 __be32 cspr; 777 u32 res2; 778 } cspr_cs[FSL_IFC_BANK_COUNT]; 779 u32 res3[0x19]; 780 struct { 781 __be32 amask; 782 u32 res4[0x2]; 783 } amask_cs[FSL_IFC_BANK_COUNT]; 784 u32 res5[0x17]; 785 struct { 786 __be32 csor_ext; 787 __be32 csor; 788 u32 res6; 789 } csor_cs[FSL_IFC_BANK_COUNT]; 790 u32 res7[0x19]; 791 struct { 792 __be32 ftim[4]; 793 u32 res8[0x8]; 794 } ftim_cs[FSL_IFC_BANK_COUNT]; 795 u32 res9[0x60]; 796 __be32 rb_stat; 797 u32 res10[0x2]; 798 __be32 ifc_gcr; 799 u32 res11[0x2]; 800 __be32 cm_evter_stat; 801 u32 res12[0x2]; 802 __be32 cm_evter_en; 803 u32 res13[0x2]; 804 __be32 cm_evter_intr_en; 805 u32 res14[0x2]; 806 __be32 cm_erattr0; 807 __be32 cm_erattr1; 808 u32 res15[0x2]; 809 __be32 ifc_ccr; 810 __be32 ifc_csr; 811 u32 res16[0x2EB]; 812 struct fsl_ifc_nand ifc_nand; 813 struct fsl_ifc_nor ifc_nor; 814 struct fsl_ifc_gpcm ifc_gpcm; 815 }; 816 817 extern unsigned int convert_ifc_address(phys_addr_t addr_base); 818 extern int fsl_ifc_find(phys_addr_t addr_base); 819 820 /* overview of the fsl ifc controller */ 821 822 struct fsl_ifc_ctrl { 823 /* device info */ 824 struct device *dev; 825 struct fsl_ifc_regs __iomem *regs; 826 int irq; 827 int nand_irq; 828 spinlock_t lock; 829 void *nand; 830 831 u32 nand_stat; 832 wait_queue_head_t nand_wait; 833 }; 834 835 extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev; 836 837 838 #endif /* __ASM_FSL_IFC_H */ 839