1*cdff4314SPatrick Havelange // SPDX-License-Identifier: GPL-2.0 2*cdff4314SPatrick Havelange #ifndef __FSL_FTM_H__ 3*cdff4314SPatrick Havelange #define __FSL_FTM_H__ 4*cdff4314SPatrick Havelange 5*cdff4314SPatrick Havelange #define FTM_SC 0x0 /* Status And Control */ 6*cdff4314SPatrick Havelange #define FTM_CNT 0x4 /* Counter */ 7*cdff4314SPatrick Havelange #define FTM_MOD 0x8 /* Modulo */ 8*cdff4314SPatrick Havelange 9*cdff4314SPatrick Havelange #define FTM_CNTIN 0x4C /* Counter Initial Value */ 10*cdff4314SPatrick Havelange #define FTM_STATUS 0x50 /* Capture And Compare Status */ 11*cdff4314SPatrick Havelange #define FTM_MODE 0x54 /* Features Mode Selection */ 12*cdff4314SPatrick Havelange #define FTM_SYNC 0x58 /* Synchronization */ 13*cdff4314SPatrick Havelange #define FTM_OUTINIT 0x5C /* Initial State For Channels Output */ 14*cdff4314SPatrick Havelange #define FTM_OUTMASK 0x60 /* Output Mask */ 15*cdff4314SPatrick Havelange #define FTM_COMBINE 0x64 /* Function For Linked Channels */ 16*cdff4314SPatrick Havelange #define FTM_DEADTIME 0x68 /* Deadtime Insertion Control */ 17*cdff4314SPatrick Havelange #define FTM_EXTTRIG 0x6C /* FTM External Trigger */ 18*cdff4314SPatrick Havelange #define FTM_POL 0x70 /* Channels Polarity */ 19*cdff4314SPatrick Havelange #define FTM_FMS 0x74 /* Fault Mode Status */ 20*cdff4314SPatrick Havelange #define FTM_FILTER 0x78 /* Input Capture Filter Control */ 21*cdff4314SPatrick Havelange #define FTM_FLTCTRL 0x7C /* Fault Control */ 22*cdff4314SPatrick Havelange #define FTM_QDCTRL 0x80 /* Quadrature Decoder Control And Status */ 23*cdff4314SPatrick Havelange #define FTM_CONF 0x84 /* Configuration */ 24*cdff4314SPatrick Havelange #define FTM_FLTPOL 0x88 /* FTM Fault Input Polarity */ 25*cdff4314SPatrick Havelange #define FTM_SYNCONF 0x8C /* Synchronization Configuration */ 26*cdff4314SPatrick Havelange #define FTM_INVCTRL 0x90 /* FTM Inverting Control */ 27*cdff4314SPatrick Havelange #define FTM_SWOCTRL 0x94 /* FTM Software Output Control */ 28*cdff4314SPatrick Havelange #define FTM_PWMLOAD 0x98 /* FTM PWM Load */ 29*cdff4314SPatrick Havelange 30*cdff4314SPatrick Havelange #define FTM_SC_CLK_MASK_SHIFT 3 31*cdff4314SPatrick Havelange #define FTM_SC_CLK_MASK (3 << FTM_SC_CLK_MASK_SHIFT) 32*cdff4314SPatrick Havelange #define FTM_SC_TOF 0x80 33*cdff4314SPatrick Havelange #define FTM_SC_TOIE 0x40 34*cdff4314SPatrick Havelange #define FTM_SC_CPWMS 0x20 35*cdff4314SPatrick Havelange #define FTM_SC_CLKS 0x18 36*cdff4314SPatrick Havelange #define FTM_SC_PS_1 0x0 37*cdff4314SPatrick Havelange #define FTM_SC_PS_2 0x1 38*cdff4314SPatrick Havelange #define FTM_SC_PS_4 0x2 39*cdff4314SPatrick Havelange #define FTM_SC_PS_8 0x3 40*cdff4314SPatrick Havelange #define FTM_SC_PS_16 0x4 41*cdff4314SPatrick Havelange #define FTM_SC_PS_32 0x5 42*cdff4314SPatrick Havelange #define FTM_SC_PS_64 0x6 43*cdff4314SPatrick Havelange #define FTM_SC_PS_128 0x7 44*cdff4314SPatrick Havelange #define FTM_SC_PS_MASK 0x7 45*cdff4314SPatrick Havelange 46*cdff4314SPatrick Havelange #define FTM_MODE_FAULTIE 0x80 47*cdff4314SPatrick Havelange #define FTM_MODE_FAULTM 0x60 48*cdff4314SPatrick Havelange #define FTM_MODE_CAPTEST 0x10 49*cdff4314SPatrick Havelange #define FTM_MODE_PWMSYNC 0x8 50*cdff4314SPatrick Havelange #define FTM_MODE_WPDIS 0x4 51*cdff4314SPatrick Havelange #define FTM_MODE_INIT 0x2 52*cdff4314SPatrick Havelange #define FTM_MODE_FTMEN 0x1 53*cdff4314SPatrick Havelange 54*cdff4314SPatrick Havelange /* NXP Errata: The PHAFLTREN and PHBFLTREN bits are tide to zero internally 55*cdff4314SPatrick Havelange * and these bits cannot be set. Flextimer cannot use Filter in 56*cdff4314SPatrick Havelange * Quadrature Decoder Mode. 57*cdff4314SPatrick Havelange * https://community.nxp.com/thread/467648#comment-1010319 58*cdff4314SPatrick Havelange */ 59*cdff4314SPatrick Havelange #define FTM_QDCTRL_PHAFLTREN 0x80 60*cdff4314SPatrick Havelange #define FTM_QDCTRL_PHBFLTREN 0x40 61*cdff4314SPatrick Havelange #define FTM_QDCTRL_PHAPOL 0x20 62*cdff4314SPatrick Havelange #define FTM_QDCTRL_PHBPOL 0x10 63*cdff4314SPatrick Havelange #define FTM_QDCTRL_QUADMODE 0x8 64*cdff4314SPatrick Havelange #define FTM_QDCTRL_QUADDIR 0x4 65*cdff4314SPatrick Havelange #define FTM_QDCTRL_TOFDIR 0x2 66*cdff4314SPatrick Havelange #define FTM_QDCTRL_QUADEN 0x1 67*cdff4314SPatrick Havelange 68*cdff4314SPatrick Havelange #define FTM_FMS_FAULTF 0x80 69*cdff4314SPatrick Havelange #define FTM_FMS_WPEN 0x40 70*cdff4314SPatrick Havelange #define FTM_FMS_FAULTIN 0x10 71*cdff4314SPatrick Havelange #define FTM_FMS_FAULTF3 0x8 72*cdff4314SPatrick Havelange #define FTM_FMS_FAULTF2 0x4 73*cdff4314SPatrick Havelange #define FTM_FMS_FAULTF1 0x2 74*cdff4314SPatrick Havelange #define FTM_FMS_FAULTF0 0x1 75*cdff4314SPatrick Havelange 76*cdff4314SPatrick Havelange #define FTM_CSC_BASE 0xC 77*cdff4314SPatrick Havelange #define FTM_CSC_MSB 0x20 78*cdff4314SPatrick Havelange #define FTM_CSC_MSA 0x10 79*cdff4314SPatrick Havelange #define FTM_CSC_ELSB 0x8 80*cdff4314SPatrick Havelange #define FTM_CSC_ELSA 0x4 81*cdff4314SPatrick Havelange #define FTM_CSC(_channel) (FTM_CSC_BASE + ((_channel) * 8)) 82*cdff4314SPatrick Havelange 83*cdff4314SPatrick Havelange #define FTM_CV_BASE 0x10 84*cdff4314SPatrick Havelange #define FTM_CV(_channel) (FTM_CV_BASE + ((_channel) * 8)) 85*cdff4314SPatrick Havelange 86*cdff4314SPatrick Havelange #define FTM_PS_MAX 7 87*cdff4314SPatrick Havelange 88*cdff4314SPatrick Havelange #endif 89