1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2023 Meta Platforms, Inc. and affiliates 4 * Copyright (c) 2023 Intel and affiliates 5 */ 6 7 #ifndef __DPLL_H__ 8 #define __DPLL_H__ 9 10 #include <uapi/linux/dpll.h> 11 #include <linux/device.h> 12 #include <linux/netlink.h> 13 14 struct dpll_device; 15 struct dpll_pin; 16 17 struct dpll_device_ops { 18 int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv, 19 enum dpll_mode *mode, struct netlink_ext_ack *extack); 20 bool (*mode_supported)(const struct dpll_device *dpll, void *dpll_priv, 21 const enum dpll_mode mode, 22 struct netlink_ext_ack *extack); 23 int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv, 24 enum dpll_lock_status *status, 25 struct netlink_ext_ack *extack); 26 int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv, 27 s32 *temp, struct netlink_ext_ack *extack); 28 }; 29 30 struct dpll_pin_ops { 31 int (*frequency_set)(const struct dpll_pin *pin, void *pin_priv, 32 const struct dpll_device *dpll, void *dpll_priv, 33 const u64 frequency, 34 struct netlink_ext_ack *extack); 35 int (*frequency_get)(const struct dpll_pin *pin, void *pin_priv, 36 const struct dpll_device *dpll, void *dpll_priv, 37 u64 *frequency, struct netlink_ext_ack *extack); 38 int (*direction_set)(const struct dpll_pin *pin, void *pin_priv, 39 const struct dpll_device *dpll, void *dpll_priv, 40 const enum dpll_pin_direction direction, 41 struct netlink_ext_ack *extack); 42 int (*direction_get)(const struct dpll_pin *pin, void *pin_priv, 43 const struct dpll_device *dpll, void *dpll_priv, 44 enum dpll_pin_direction *direction, 45 struct netlink_ext_ack *extack); 46 int (*state_on_pin_get)(const struct dpll_pin *pin, void *pin_priv, 47 const struct dpll_pin *parent_pin, 48 void *parent_pin_priv, 49 enum dpll_pin_state *state, 50 struct netlink_ext_ack *extack); 51 int (*state_on_dpll_get)(const struct dpll_pin *pin, void *pin_priv, 52 const struct dpll_device *dpll, 53 void *dpll_priv, enum dpll_pin_state *state, 54 struct netlink_ext_ack *extack); 55 int (*state_on_pin_set)(const struct dpll_pin *pin, void *pin_priv, 56 const struct dpll_pin *parent_pin, 57 void *parent_pin_priv, 58 const enum dpll_pin_state state, 59 struct netlink_ext_ack *extack); 60 int (*state_on_dpll_set)(const struct dpll_pin *pin, void *pin_priv, 61 const struct dpll_device *dpll, 62 void *dpll_priv, 63 const enum dpll_pin_state state, 64 struct netlink_ext_ack *extack); 65 int (*prio_get)(const struct dpll_pin *pin, void *pin_priv, 66 const struct dpll_device *dpll, void *dpll_priv, 67 u32 *prio, struct netlink_ext_ack *extack); 68 int (*prio_set)(const struct dpll_pin *pin, void *pin_priv, 69 const struct dpll_device *dpll, void *dpll_priv, 70 const u32 prio, struct netlink_ext_ack *extack); 71 }; 72 73 struct dpll_pin_frequency { 74 u64 min; 75 u64 max; 76 }; 77 78 #define DPLL_PIN_FREQUENCY_RANGE(_min, _max) \ 79 { \ 80 .min = _min, \ 81 .max = _max, \ 82 } 83 84 #define DPLL_PIN_FREQUENCY(_val) DPLL_PIN_FREQUENCY_RANGE(_val, _val) 85 #define DPLL_PIN_FREQUENCY_1PPS \ 86 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_1_HZ) 87 #define DPLL_PIN_FREQUENCY_10MHZ \ 88 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_MHZ) 89 #define DPLL_PIN_FREQUENCY_IRIG_B \ 90 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_KHZ) 91 #define DPLL_PIN_FREQUENCY_DCF77 \ 92 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ) 93 94 struct dpll_pin_properties { 95 const char *board_label; 96 const char *panel_label; 97 const char *package_label; 98 enum dpll_pin_type type; 99 unsigned long capabilities; 100 u32 freq_supported_num; 101 struct dpll_pin_frequency *freq_supported; 102 }; 103 104 #if IS_ENABLED(CONFIG_DPLL) 105 size_t dpll_msg_pin_handle_size(struct dpll_pin *pin); 106 int dpll_msg_add_pin_handle(struct sk_buff *msg, struct dpll_pin *pin); 107 #else 108 static inline size_t dpll_msg_pin_handle_size(struct dpll_pin *pin) 109 { 110 return 0; 111 } 112 113 static inline int dpll_msg_add_pin_handle(struct sk_buff *msg, struct dpll_pin *pin) 114 { 115 return 0; 116 } 117 #endif 118 119 struct dpll_device * 120 dpll_device_get(u64 clock_id, u32 dev_driver_id, struct module *module); 121 122 void dpll_device_put(struct dpll_device *dpll); 123 124 int dpll_device_register(struct dpll_device *dpll, enum dpll_type type, 125 const struct dpll_device_ops *ops, void *priv); 126 127 void dpll_device_unregister(struct dpll_device *dpll, 128 const struct dpll_device_ops *ops, void *priv); 129 130 struct dpll_pin * 131 dpll_pin_get(u64 clock_id, u32 dev_driver_id, struct module *module, 132 const struct dpll_pin_properties *prop); 133 134 int dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin, 135 const struct dpll_pin_ops *ops, void *priv); 136 137 void dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin, 138 const struct dpll_pin_ops *ops, void *priv); 139 140 void dpll_pin_put(struct dpll_pin *pin); 141 142 int dpll_pin_on_pin_register(struct dpll_pin *parent, struct dpll_pin *pin, 143 const struct dpll_pin_ops *ops, void *priv); 144 145 void dpll_pin_on_pin_unregister(struct dpll_pin *parent, struct dpll_pin *pin, 146 const struct dpll_pin_ops *ops, void *priv); 147 148 int dpll_device_change_ntf(struct dpll_device *dpll); 149 150 int dpll_pin_change_ntf(struct dpll_pin *pin); 151 152 #endif 153