1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2023 Meta Platforms, Inc. and affiliates 4 * Copyright (c) 2023 Intel and affiliates 5 */ 6 7 #ifndef __DPLL_H__ 8 #define __DPLL_H__ 9 10 #include <uapi/linux/dpll.h> 11 #include <linux/device.h> 12 #include <linux/netlink.h> 13 14 struct dpll_device; 15 struct dpll_pin; 16 17 struct dpll_device_ops { 18 int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv, 19 enum dpll_mode *mode, struct netlink_ext_ack *extack); 20 int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv, 21 enum dpll_lock_status *status, 22 struct netlink_ext_ack *extack); 23 int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv, 24 s32 *temp, struct netlink_ext_ack *extack); 25 }; 26 27 struct dpll_pin_ops { 28 int (*frequency_set)(const struct dpll_pin *pin, void *pin_priv, 29 const struct dpll_device *dpll, void *dpll_priv, 30 const u64 frequency, 31 struct netlink_ext_ack *extack); 32 int (*frequency_get)(const struct dpll_pin *pin, void *pin_priv, 33 const struct dpll_device *dpll, void *dpll_priv, 34 u64 *frequency, struct netlink_ext_ack *extack); 35 int (*direction_set)(const struct dpll_pin *pin, void *pin_priv, 36 const struct dpll_device *dpll, void *dpll_priv, 37 const enum dpll_pin_direction direction, 38 struct netlink_ext_ack *extack); 39 int (*direction_get)(const struct dpll_pin *pin, void *pin_priv, 40 const struct dpll_device *dpll, void *dpll_priv, 41 enum dpll_pin_direction *direction, 42 struct netlink_ext_ack *extack); 43 int (*state_on_pin_get)(const struct dpll_pin *pin, void *pin_priv, 44 const struct dpll_pin *parent_pin, 45 void *parent_pin_priv, 46 enum dpll_pin_state *state, 47 struct netlink_ext_ack *extack); 48 int (*state_on_dpll_get)(const struct dpll_pin *pin, void *pin_priv, 49 const struct dpll_device *dpll, 50 void *dpll_priv, enum dpll_pin_state *state, 51 struct netlink_ext_ack *extack); 52 int (*state_on_pin_set)(const struct dpll_pin *pin, void *pin_priv, 53 const struct dpll_pin *parent_pin, 54 void *parent_pin_priv, 55 const enum dpll_pin_state state, 56 struct netlink_ext_ack *extack); 57 int (*state_on_dpll_set)(const struct dpll_pin *pin, void *pin_priv, 58 const struct dpll_device *dpll, 59 void *dpll_priv, 60 const enum dpll_pin_state state, 61 struct netlink_ext_ack *extack); 62 int (*prio_get)(const struct dpll_pin *pin, void *pin_priv, 63 const struct dpll_device *dpll, void *dpll_priv, 64 u32 *prio, struct netlink_ext_ack *extack); 65 int (*prio_set)(const struct dpll_pin *pin, void *pin_priv, 66 const struct dpll_device *dpll, void *dpll_priv, 67 const u32 prio, struct netlink_ext_ack *extack); 68 int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv, 69 const struct dpll_device *dpll, void *dpll_priv, 70 s64 *phase_offset, 71 struct netlink_ext_ack *extack); 72 int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv, 73 const struct dpll_device *dpll, void *dpll_priv, 74 s32 *phase_adjust, 75 struct netlink_ext_ack *extack); 76 int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv, 77 const struct dpll_device *dpll, void *dpll_priv, 78 const s32 phase_adjust, 79 struct netlink_ext_ack *extack); 80 }; 81 82 struct dpll_pin_frequency { 83 u64 min; 84 u64 max; 85 }; 86 87 #define DPLL_PIN_FREQUENCY_RANGE(_min, _max) \ 88 { \ 89 .min = _min, \ 90 .max = _max, \ 91 } 92 93 #define DPLL_PIN_FREQUENCY(_val) DPLL_PIN_FREQUENCY_RANGE(_val, _val) 94 #define DPLL_PIN_FREQUENCY_1PPS \ 95 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_1_HZ) 96 #define DPLL_PIN_FREQUENCY_10MHZ \ 97 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_MHZ) 98 #define DPLL_PIN_FREQUENCY_IRIG_B \ 99 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_KHZ) 100 #define DPLL_PIN_FREQUENCY_DCF77 \ 101 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ) 102 103 struct dpll_pin_phase_adjust_range { 104 s32 min; 105 s32 max; 106 }; 107 108 struct dpll_pin_properties { 109 const char *board_label; 110 const char *panel_label; 111 const char *package_label; 112 enum dpll_pin_type type; 113 unsigned long capabilities; 114 u32 freq_supported_num; 115 struct dpll_pin_frequency *freq_supported; 116 struct dpll_pin_phase_adjust_range phase_range; 117 }; 118 119 #if IS_ENABLED(CONFIG_DPLL) 120 size_t dpll_msg_pin_handle_size(struct dpll_pin *pin); 121 int dpll_msg_add_pin_handle(struct sk_buff *msg, struct dpll_pin *pin); 122 #else 123 static inline size_t dpll_msg_pin_handle_size(struct dpll_pin *pin) 124 { 125 return 0; 126 } 127 128 static inline int dpll_msg_add_pin_handle(struct sk_buff *msg, struct dpll_pin *pin) 129 { 130 return 0; 131 } 132 #endif 133 134 struct dpll_device * 135 dpll_device_get(u64 clock_id, u32 dev_driver_id, struct module *module); 136 137 void dpll_device_put(struct dpll_device *dpll); 138 139 int dpll_device_register(struct dpll_device *dpll, enum dpll_type type, 140 const struct dpll_device_ops *ops, void *priv); 141 142 void dpll_device_unregister(struct dpll_device *dpll, 143 const struct dpll_device_ops *ops, void *priv); 144 145 struct dpll_pin * 146 dpll_pin_get(u64 clock_id, u32 dev_driver_id, struct module *module, 147 const struct dpll_pin_properties *prop); 148 149 int dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin, 150 const struct dpll_pin_ops *ops, void *priv); 151 152 void dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin, 153 const struct dpll_pin_ops *ops, void *priv); 154 155 void dpll_pin_put(struct dpll_pin *pin); 156 157 int dpll_pin_on_pin_register(struct dpll_pin *parent, struct dpll_pin *pin, 158 const struct dpll_pin_ops *ops, void *priv); 159 160 void dpll_pin_on_pin_unregister(struct dpll_pin *parent, struct dpll_pin *pin, 161 const struct dpll_pin_ops *ops, void *priv); 162 163 int dpll_device_change_ntf(struct dpll_device *dpll); 164 165 int dpll_pin_change_ntf(struct dpll_pin *pin); 166 167 #endif 168