1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2023 Meta Platforms, Inc. and affiliates 4 * Copyright (c) 2023 Intel and affiliates 5 */ 6 7 #ifndef __DPLL_H__ 8 #define __DPLL_H__ 9 10 #include <uapi/linux/dpll.h> 11 #include <linux/device.h> 12 #include <linux/netlink.h> 13 14 struct dpll_device; 15 struct dpll_pin; 16 17 struct dpll_device_ops { 18 int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv, 19 enum dpll_mode *mode, struct netlink_ext_ack *extack); 20 int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv, 21 enum dpll_lock_status *status, 22 enum dpll_lock_status_error *status_error, 23 struct netlink_ext_ack *extack); 24 int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv, 25 s32 *temp, struct netlink_ext_ack *extack); 26 }; 27 28 struct dpll_pin_ops { 29 int (*frequency_set)(const struct dpll_pin *pin, void *pin_priv, 30 const struct dpll_device *dpll, void *dpll_priv, 31 const u64 frequency, 32 struct netlink_ext_ack *extack); 33 int (*frequency_get)(const struct dpll_pin *pin, void *pin_priv, 34 const struct dpll_device *dpll, void *dpll_priv, 35 u64 *frequency, struct netlink_ext_ack *extack); 36 int (*direction_set)(const struct dpll_pin *pin, void *pin_priv, 37 const struct dpll_device *dpll, void *dpll_priv, 38 const enum dpll_pin_direction direction, 39 struct netlink_ext_ack *extack); 40 int (*direction_get)(const struct dpll_pin *pin, void *pin_priv, 41 const struct dpll_device *dpll, void *dpll_priv, 42 enum dpll_pin_direction *direction, 43 struct netlink_ext_ack *extack); 44 int (*state_on_pin_get)(const struct dpll_pin *pin, void *pin_priv, 45 const struct dpll_pin *parent_pin, 46 void *parent_pin_priv, 47 enum dpll_pin_state *state, 48 struct netlink_ext_ack *extack); 49 int (*state_on_dpll_get)(const struct dpll_pin *pin, void *pin_priv, 50 const struct dpll_device *dpll, 51 void *dpll_priv, enum dpll_pin_state *state, 52 struct netlink_ext_ack *extack); 53 int (*state_on_pin_set)(const struct dpll_pin *pin, void *pin_priv, 54 const struct dpll_pin *parent_pin, 55 void *parent_pin_priv, 56 const enum dpll_pin_state state, 57 struct netlink_ext_ack *extack); 58 int (*state_on_dpll_set)(const struct dpll_pin *pin, void *pin_priv, 59 const struct dpll_device *dpll, 60 void *dpll_priv, 61 const enum dpll_pin_state state, 62 struct netlink_ext_ack *extack); 63 int (*prio_get)(const struct dpll_pin *pin, void *pin_priv, 64 const struct dpll_device *dpll, void *dpll_priv, 65 u32 *prio, struct netlink_ext_ack *extack); 66 int (*prio_set)(const struct dpll_pin *pin, void *pin_priv, 67 const struct dpll_device *dpll, void *dpll_priv, 68 const u32 prio, struct netlink_ext_ack *extack); 69 int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv, 70 const struct dpll_device *dpll, void *dpll_priv, 71 s64 *phase_offset, 72 struct netlink_ext_ack *extack); 73 int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv, 74 const struct dpll_device *dpll, void *dpll_priv, 75 s32 *phase_adjust, 76 struct netlink_ext_ack *extack); 77 int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv, 78 const struct dpll_device *dpll, void *dpll_priv, 79 const s32 phase_adjust, 80 struct netlink_ext_ack *extack); 81 int (*ffo_get)(const struct dpll_pin *pin, void *pin_priv, 82 const struct dpll_device *dpll, void *dpll_priv, 83 s64 *ffo, struct netlink_ext_ack *extack); 84 }; 85 86 struct dpll_pin_frequency { 87 u64 min; 88 u64 max; 89 }; 90 91 #define DPLL_PIN_FREQUENCY_RANGE(_min, _max) \ 92 { \ 93 .min = _min, \ 94 .max = _max, \ 95 } 96 97 #define DPLL_PIN_FREQUENCY(_val) DPLL_PIN_FREQUENCY_RANGE(_val, _val) 98 #define DPLL_PIN_FREQUENCY_1PPS \ 99 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_1_HZ) 100 #define DPLL_PIN_FREQUENCY_10MHZ \ 101 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_MHZ) 102 #define DPLL_PIN_FREQUENCY_IRIG_B \ 103 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_KHZ) 104 #define DPLL_PIN_FREQUENCY_DCF77 \ 105 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ) 106 107 struct dpll_pin_phase_adjust_range { 108 s32 min; 109 s32 max; 110 }; 111 112 struct dpll_pin_properties { 113 const char *board_label; 114 const char *panel_label; 115 const char *package_label; 116 enum dpll_pin_type type; 117 unsigned long capabilities; 118 u32 freq_supported_num; 119 struct dpll_pin_frequency *freq_supported; 120 struct dpll_pin_phase_adjust_range phase_range; 121 }; 122 123 #if IS_ENABLED(CONFIG_DPLL) 124 size_t dpll_msg_pin_handle_size(struct dpll_pin *pin); 125 int dpll_msg_add_pin_handle(struct sk_buff *msg, struct dpll_pin *pin); 126 #else 127 static inline size_t dpll_msg_pin_handle_size(struct dpll_pin *pin) 128 { 129 return 0; 130 } 131 132 static inline int dpll_msg_add_pin_handle(struct sk_buff *msg, struct dpll_pin *pin) 133 { 134 return 0; 135 } 136 #endif 137 138 struct dpll_device * 139 dpll_device_get(u64 clock_id, u32 dev_driver_id, struct module *module); 140 141 void dpll_device_put(struct dpll_device *dpll); 142 143 int dpll_device_register(struct dpll_device *dpll, enum dpll_type type, 144 const struct dpll_device_ops *ops, void *priv); 145 146 void dpll_device_unregister(struct dpll_device *dpll, 147 const struct dpll_device_ops *ops, void *priv); 148 149 struct dpll_pin * 150 dpll_pin_get(u64 clock_id, u32 dev_driver_id, struct module *module, 151 const struct dpll_pin_properties *prop); 152 153 int dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin, 154 const struct dpll_pin_ops *ops, void *priv); 155 156 void dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin, 157 const struct dpll_pin_ops *ops, void *priv); 158 159 void dpll_pin_put(struct dpll_pin *pin); 160 161 int dpll_pin_on_pin_register(struct dpll_pin *parent, struct dpll_pin *pin, 162 const struct dpll_pin_ops *ops, void *priv); 163 164 void dpll_pin_on_pin_unregister(struct dpll_pin *parent, struct dpll_pin *pin, 165 const struct dpll_pin_ops *ops, void *priv); 166 167 int dpll_device_change_ntf(struct dpll_device *dpll); 168 169 int dpll_pin_change_ntf(struct dpll_pin *pin); 170 171 #endif 172