1 /* 2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called COPYING. 16 */ 17 #ifndef LINUX_DMAENGINE_H 18 #define LINUX_DMAENGINE_H 19 20 #include <linux/device.h> 21 #include <linux/err.h> 22 #include <linux/uio.h> 23 #include <linux/bug.h> 24 #include <linux/scatterlist.h> 25 #include <linux/bitmap.h> 26 #include <linux/types.h> 27 #include <asm/page.h> 28 29 /** 30 * typedef dma_cookie_t - an opaque DMA cookie 31 * 32 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code 33 */ 34 typedef s32 dma_cookie_t; 35 #define DMA_MIN_COOKIE 1 36 37 static inline int dma_submit_error(dma_cookie_t cookie) 38 { 39 return cookie < 0 ? cookie : 0; 40 } 41 42 /** 43 * enum dma_status - DMA transaction status 44 * @DMA_COMPLETE: transaction completed 45 * @DMA_IN_PROGRESS: transaction not yet processed 46 * @DMA_PAUSED: transaction is paused 47 * @DMA_ERROR: transaction failed 48 */ 49 enum dma_status { 50 DMA_COMPLETE, 51 DMA_IN_PROGRESS, 52 DMA_PAUSED, 53 DMA_ERROR, 54 }; 55 56 /** 57 * enum dma_transaction_type - DMA transaction types/indexes 58 * 59 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is 60 * automatically set as dma devices are registered. 61 */ 62 enum dma_transaction_type { 63 DMA_MEMCPY, 64 DMA_XOR, 65 DMA_PQ, 66 DMA_XOR_VAL, 67 DMA_PQ_VAL, 68 DMA_MEMSET, 69 DMA_MEMSET_SG, 70 DMA_INTERRUPT, 71 DMA_SG, 72 DMA_PRIVATE, 73 DMA_ASYNC_TX, 74 DMA_SLAVE, 75 DMA_CYCLIC, 76 DMA_INTERLEAVE, 77 /* last transaction type for creation of the capabilities mask */ 78 DMA_TX_TYPE_END, 79 }; 80 81 /** 82 * enum dma_transfer_direction - dma transfer mode and direction indicator 83 * @DMA_MEM_TO_MEM: Async/Memcpy mode 84 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device 85 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory 86 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device 87 */ 88 enum dma_transfer_direction { 89 DMA_MEM_TO_MEM, 90 DMA_MEM_TO_DEV, 91 DMA_DEV_TO_MEM, 92 DMA_DEV_TO_DEV, 93 DMA_TRANS_NONE, 94 }; 95 96 /** 97 * Interleaved Transfer Request 98 * ---------------------------- 99 * A chunk is collection of contiguous bytes to be transfered. 100 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG). 101 * ICGs may or maynot change between chunks. 102 * A FRAME is the smallest series of contiguous {chunk,icg} pairs, 103 * that when repeated an integral number of times, specifies the transfer. 104 * A transfer template is specification of a Frame, the number of times 105 * it is to be repeated and other per-transfer attributes. 106 * 107 * Practically, a client driver would have ready a template for each 108 * type of transfer it is going to need during its lifetime and 109 * set only 'src_start' and 'dst_start' before submitting the requests. 110 * 111 * 112 * | Frame-1 | Frame-2 | ~ | Frame-'numf' | 113 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...| 114 * 115 * == Chunk size 116 * ... ICG 117 */ 118 119 /** 120 * struct data_chunk - Element of scatter-gather list that makes a frame. 121 * @size: Number of bytes to read from source. 122 * size_dst := fn(op, size_src), so doesn't mean much for destination. 123 * @icg: Number of bytes to jump after last src/dst address of this 124 * chunk and before first src/dst address for next chunk. 125 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false. 126 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false. 127 * @dst_icg: Number of bytes to jump after last dst address of this 128 * chunk and before the first dst address for next chunk. 129 * Ignored if dst_inc is true and dst_sgl is false. 130 * @src_icg: Number of bytes to jump after last src address of this 131 * chunk and before the first src address for next chunk. 132 * Ignored if src_inc is true and src_sgl is false. 133 */ 134 struct data_chunk { 135 size_t size; 136 size_t icg; 137 size_t dst_icg; 138 size_t src_icg; 139 }; 140 141 /** 142 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern 143 * and attributes. 144 * @src_start: Bus address of source for the first chunk. 145 * @dst_start: Bus address of destination for the first chunk. 146 * @dir: Specifies the type of Source and Destination. 147 * @src_inc: If the source address increments after reading from it. 148 * @dst_inc: If the destination address increments after writing to it. 149 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read). 150 * Otherwise, source is read contiguously (icg ignored). 151 * Ignored if src_inc is false. 152 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write). 153 * Otherwise, destination is filled contiguously (icg ignored). 154 * Ignored if dst_inc is false. 155 * @numf: Number of frames in this template. 156 * @frame_size: Number of chunks in a frame i.e, size of sgl[]. 157 * @sgl: Array of {chunk,icg} pairs that make up a frame. 158 */ 159 struct dma_interleaved_template { 160 dma_addr_t src_start; 161 dma_addr_t dst_start; 162 enum dma_transfer_direction dir; 163 bool src_inc; 164 bool dst_inc; 165 bool src_sgl; 166 bool dst_sgl; 167 size_t numf; 168 size_t frame_size; 169 struct data_chunk sgl[0]; 170 }; 171 172 /** 173 * enum dma_ctrl_flags - DMA flags to augment operation preparation, 174 * control completion, and communicate status. 175 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of 176 * this transaction 177 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client 178 * acknowledges receipt, i.e. has has a chance to establish any dependency 179 * chains 180 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q 181 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P 182 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as 183 * sources that were the result of a previous operation, in the case of a PQ 184 * operation it continues the calculation with new sources 185 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend 186 * on the result of this operation 187 * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till 188 * cleared or freed 189 */ 190 enum dma_ctrl_flags { 191 DMA_PREP_INTERRUPT = (1 << 0), 192 DMA_CTRL_ACK = (1 << 1), 193 DMA_PREP_PQ_DISABLE_P = (1 << 2), 194 DMA_PREP_PQ_DISABLE_Q = (1 << 3), 195 DMA_PREP_CONTINUE = (1 << 4), 196 DMA_PREP_FENCE = (1 << 5), 197 DMA_CTRL_REUSE = (1 << 6), 198 }; 199 200 /** 201 * enum sum_check_bits - bit position of pq_check_flags 202 */ 203 enum sum_check_bits { 204 SUM_CHECK_P = 0, 205 SUM_CHECK_Q = 1, 206 }; 207 208 /** 209 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations 210 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise 211 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise 212 */ 213 enum sum_check_flags { 214 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P), 215 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q), 216 }; 217 218 219 /** 220 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. 221 * See linux/cpumask.h 222 */ 223 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; 224 225 /** 226 * struct dma_chan_percpu - the per-CPU part of struct dma_chan 227 * @memcpy_count: transaction counter 228 * @bytes_transferred: byte counter 229 */ 230 231 struct dma_chan_percpu { 232 /* stats */ 233 unsigned long memcpy_count; 234 unsigned long bytes_transferred; 235 }; 236 237 /** 238 * struct dma_router - DMA router structure 239 * @dev: pointer to the DMA router device 240 * @route_free: function to be called when the route can be disconnected 241 */ 242 struct dma_router { 243 struct device *dev; 244 void (*route_free)(struct device *dev, void *route_data); 245 }; 246 247 /** 248 * struct dma_chan - devices supply DMA channels, clients use them 249 * @device: ptr to the dma device who supplies this channel, always !%NULL 250 * @cookie: last cookie value returned to client 251 * @completed_cookie: last completed cookie for this channel 252 * @chan_id: channel ID for sysfs 253 * @dev: class device for sysfs 254 * @device_node: used to add this to the device chan list 255 * @local: per-cpu pointer to a struct dma_chan_percpu 256 * @client_count: how many clients are using this channel 257 * @table_count: number of appearances in the mem-to-mem allocation table 258 * @router: pointer to the DMA router structure 259 * @route_data: channel specific data for the router 260 * @private: private data for certain client-channel associations 261 */ 262 struct dma_chan { 263 struct dma_device *device; 264 dma_cookie_t cookie; 265 dma_cookie_t completed_cookie; 266 267 /* sysfs */ 268 int chan_id; 269 struct dma_chan_dev *dev; 270 271 struct list_head device_node; 272 struct dma_chan_percpu __percpu *local; 273 int client_count; 274 int table_count; 275 276 /* DMA router */ 277 struct dma_router *router; 278 void *route_data; 279 280 void *private; 281 }; 282 283 /** 284 * struct dma_chan_dev - relate sysfs device node to backing channel device 285 * @chan: driver channel device 286 * @device: sysfs device 287 * @dev_id: parent dma_device dev_id 288 * @idr_ref: reference count to gate release of dma_device dev_id 289 */ 290 struct dma_chan_dev { 291 struct dma_chan *chan; 292 struct device device; 293 int dev_id; 294 atomic_t *idr_ref; 295 }; 296 297 /** 298 * enum dma_slave_buswidth - defines bus width of the DMA slave 299 * device, source or target buses 300 */ 301 enum dma_slave_buswidth { 302 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, 303 DMA_SLAVE_BUSWIDTH_1_BYTE = 1, 304 DMA_SLAVE_BUSWIDTH_2_BYTES = 2, 305 DMA_SLAVE_BUSWIDTH_3_BYTES = 3, 306 DMA_SLAVE_BUSWIDTH_4_BYTES = 4, 307 DMA_SLAVE_BUSWIDTH_8_BYTES = 8, 308 DMA_SLAVE_BUSWIDTH_16_BYTES = 16, 309 DMA_SLAVE_BUSWIDTH_32_BYTES = 32, 310 DMA_SLAVE_BUSWIDTH_64_BYTES = 64, 311 }; 312 313 /** 314 * struct dma_slave_config - dma slave channel runtime config 315 * @direction: whether the data shall go in or out on this slave 316 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are 317 * legal values. DEPRECATED, drivers should use the direction argument 318 * to the device_prep_slave_sg and device_prep_dma_cyclic functions or 319 * the dir field in the dma_interleaved_template structure. 320 * @src_addr: this is the physical address where DMA slave data 321 * should be read (RX), if the source is memory this argument is 322 * ignored. 323 * @dst_addr: this is the physical address where DMA slave data 324 * should be written (TX), if the source is memory this argument 325 * is ignored. 326 * @src_addr_width: this is the width in bytes of the source (RX) 327 * register where DMA data shall be read. If the source 328 * is memory this may be ignored depending on architecture. 329 * Legal values: 1, 2, 4, 8. 330 * @dst_addr_width: same as src_addr_width but for destination 331 * target (TX) mutatis mutandis. 332 * @src_maxburst: the maximum number of words (note: words, as in 333 * units of the src_addr_width member, not bytes) that can be sent 334 * in one burst to the device. Typically something like half the 335 * FIFO depth on I/O peripherals so you don't overflow it. This 336 * may or may not be applicable on memory sources. 337 * @dst_maxburst: same as src_maxburst but for destination target 338 * mutatis mutandis. 339 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill 340 * with 'true' if peripheral should be flow controller. Direction will be 341 * selected at Runtime. 342 * @slave_id: Slave requester id. Only valid for slave channels. The dma 343 * slave peripheral will have unique id as dma requester which need to be 344 * pass as slave config. 345 * 346 * This struct is passed in as configuration data to a DMA engine 347 * in order to set up a certain channel for DMA transport at runtime. 348 * The DMA device/engine has to provide support for an additional 349 * callback in the dma_device structure, device_config and this struct 350 * will then be passed in as an argument to the function. 351 * 352 * The rationale for adding configuration information to this struct is as 353 * follows: if it is likely that more than one DMA slave controllers in 354 * the world will support the configuration option, then make it generic. 355 * If not: if it is fixed so that it be sent in static from the platform 356 * data, then prefer to do that. 357 */ 358 struct dma_slave_config { 359 enum dma_transfer_direction direction; 360 dma_addr_t src_addr; 361 dma_addr_t dst_addr; 362 enum dma_slave_buswidth src_addr_width; 363 enum dma_slave_buswidth dst_addr_width; 364 u32 src_maxburst; 365 u32 dst_maxburst; 366 bool device_fc; 367 unsigned int slave_id; 368 }; 369 370 /** 371 * enum dma_residue_granularity - Granularity of the reported transfer residue 372 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The 373 * DMA channel is only able to tell whether a descriptor has been completed or 374 * not, which means residue reporting is not supported by this channel. The 375 * residue field of the dma_tx_state field will always be 0. 376 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully 377 * completed segment of the transfer (For cyclic transfers this is after each 378 * period). This is typically implemented by having the hardware generate an 379 * interrupt after each transferred segment and then the drivers updates the 380 * outstanding residue by the size of the segment. Another possibility is if 381 * the hardware supports scatter-gather and the segment descriptor has a field 382 * which gets set after the segment has been completed. The driver then counts 383 * the number of segments without the flag set to compute the residue. 384 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred 385 * burst. This is typically only supported if the hardware has a progress 386 * register of some sort (E.g. a register with the current read/write address 387 * or a register with the amount of bursts/beats/bytes that have been 388 * transferred or still need to be transferred). 389 */ 390 enum dma_residue_granularity { 391 DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0, 392 DMA_RESIDUE_GRANULARITY_SEGMENT = 1, 393 DMA_RESIDUE_GRANULARITY_BURST = 2, 394 }; 395 396 /* struct dma_slave_caps - expose capabilities of a slave channel only 397 * 398 * @src_addr_widths: bit mask of src addr widths the channel supports 399 * @dst_addr_widths: bit mask of dstn addr widths the channel supports 400 * @directions: bit mask of slave direction the channel supported 401 * since the enum dma_transfer_direction is not defined as bits for each 402 * type of direction, the dma controller should fill (1 << <TYPE>) and same 403 * should be checked by controller as well 404 * @cmd_pause: true, if pause and thereby resume is supported 405 * @cmd_terminate: true, if terminate cmd is supported 406 * @residue_granularity: granularity of the reported transfer residue 407 * @descriptor_reuse: if a descriptor can be reused by client and 408 * resubmitted multiple times 409 */ 410 struct dma_slave_caps { 411 u32 src_addr_widths; 412 u32 dst_addr_widths; 413 u32 directions; 414 bool cmd_pause; 415 bool cmd_terminate; 416 enum dma_residue_granularity residue_granularity; 417 bool descriptor_reuse; 418 }; 419 420 static inline const char *dma_chan_name(struct dma_chan *chan) 421 { 422 return dev_name(&chan->dev->device); 423 } 424 425 void dma_chan_cleanup(struct kref *kref); 426 427 /** 428 * typedef dma_filter_fn - callback filter for dma_request_channel 429 * @chan: channel to be reviewed 430 * @filter_param: opaque parameter passed through dma_request_channel 431 * 432 * When this optional parameter is specified in a call to dma_request_channel a 433 * suitable channel is passed to this routine for further dispositioning before 434 * being returned. Where 'suitable' indicates a non-busy channel that 435 * satisfies the given capability mask. It returns 'true' to indicate that the 436 * channel is suitable. 437 */ 438 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); 439 440 typedef void (*dma_async_tx_callback)(void *dma_async_param); 441 442 struct dmaengine_unmap_data { 443 u8 map_cnt; 444 u8 to_cnt; 445 u8 from_cnt; 446 u8 bidi_cnt; 447 struct device *dev; 448 struct kref kref; 449 size_t len; 450 dma_addr_t addr[0]; 451 }; 452 453 /** 454 * struct dma_async_tx_descriptor - async transaction descriptor 455 * ---dma generic offload fields--- 456 * @cookie: tracking cookie for this transaction, set to -EBUSY if 457 * this tx is sitting on a dependency list 458 * @flags: flags to augment operation preparation, control completion, and 459 * communicate status 460 * @phys: physical address of the descriptor 461 * @chan: target channel for this operation 462 * @tx_submit: accept the descriptor, assign ordered cookie and mark the 463 * descriptor pending. To be pushed on .issue_pending() call 464 * @callback: routine to call after this operation is complete 465 * @callback_param: general parameter to pass to the callback routine 466 * ---async_tx api specific fields--- 467 * @next: at completion submit this descriptor 468 * @parent: pointer to the next level up in the dependency chain 469 * @lock: protect the parent and next pointers 470 */ 471 struct dma_async_tx_descriptor { 472 dma_cookie_t cookie; 473 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ 474 dma_addr_t phys; 475 struct dma_chan *chan; 476 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); 477 int (*desc_free)(struct dma_async_tx_descriptor *tx); 478 dma_async_tx_callback callback; 479 void *callback_param; 480 struct dmaengine_unmap_data *unmap; 481 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH 482 struct dma_async_tx_descriptor *next; 483 struct dma_async_tx_descriptor *parent; 484 spinlock_t lock; 485 #endif 486 }; 487 488 #ifdef CONFIG_DMA_ENGINE 489 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, 490 struct dmaengine_unmap_data *unmap) 491 { 492 kref_get(&unmap->kref); 493 tx->unmap = unmap; 494 } 495 496 struct dmaengine_unmap_data * 497 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags); 498 void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap); 499 #else 500 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, 501 struct dmaengine_unmap_data *unmap) 502 { 503 } 504 static inline struct dmaengine_unmap_data * 505 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags) 506 { 507 return NULL; 508 } 509 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap) 510 { 511 } 512 #endif 513 514 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx) 515 { 516 if (tx->unmap) { 517 dmaengine_unmap_put(tx->unmap); 518 tx->unmap = NULL; 519 } 520 } 521 522 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH 523 static inline void txd_lock(struct dma_async_tx_descriptor *txd) 524 { 525 } 526 static inline void txd_unlock(struct dma_async_tx_descriptor *txd) 527 { 528 } 529 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) 530 { 531 BUG(); 532 } 533 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) 534 { 535 } 536 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) 537 { 538 } 539 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) 540 { 541 return NULL; 542 } 543 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) 544 { 545 return NULL; 546 } 547 548 #else 549 static inline void txd_lock(struct dma_async_tx_descriptor *txd) 550 { 551 spin_lock_bh(&txd->lock); 552 } 553 static inline void txd_unlock(struct dma_async_tx_descriptor *txd) 554 { 555 spin_unlock_bh(&txd->lock); 556 } 557 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) 558 { 559 txd->next = next; 560 next->parent = txd; 561 } 562 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) 563 { 564 txd->parent = NULL; 565 } 566 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) 567 { 568 txd->next = NULL; 569 } 570 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) 571 { 572 return txd->parent; 573 } 574 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) 575 { 576 return txd->next; 577 } 578 #endif 579 580 /** 581 * struct dma_tx_state - filled in to report the status of 582 * a transfer. 583 * @last: last completed DMA cookie 584 * @used: last issued DMA cookie (i.e. the one in progress) 585 * @residue: the remaining number of bytes left to transmit 586 * on the selected transfer for states DMA_IN_PROGRESS and 587 * DMA_PAUSED if this is implemented in the driver, else 0 588 */ 589 struct dma_tx_state { 590 dma_cookie_t last; 591 dma_cookie_t used; 592 u32 residue; 593 }; 594 595 /** 596 * enum dmaengine_alignment - defines alignment of the DMA async tx 597 * buffers 598 */ 599 enum dmaengine_alignment { 600 DMAENGINE_ALIGN_1_BYTE = 0, 601 DMAENGINE_ALIGN_2_BYTES = 1, 602 DMAENGINE_ALIGN_4_BYTES = 2, 603 DMAENGINE_ALIGN_8_BYTES = 3, 604 DMAENGINE_ALIGN_16_BYTES = 4, 605 DMAENGINE_ALIGN_32_BYTES = 5, 606 DMAENGINE_ALIGN_64_BYTES = 6, 607 }; 608 609 /** 610 * struct dma_slave_map - associates slave device and it's slave channel with 611 * parameter to be used by a filter function 612 * @devname: name of the device 613 * @slave: slave channel name 614 * @param: opaque parameter to pass to struct dma_filter.fn 615 */ 616 struct dma_slave_map { 617 const char *devname; 618 const char *slave; 619 void *param; 620 }; 621 622 /** 623 * struct dma_filter - information for slave device/channel to filter_fn/param 624 * mapping 625 * @fn: filter function callback 626 * @mapcnt: number of slave device/channel in the map 627 * @map: array of channel to filter mapping data 628 */ 629 struct dma_filter { 630 dma_filter_fn fn; 631 int mapcnt; 632 const struct dma_slave_map *map; 633 }; 634 635 /** 636 * struct dma_device - info on the entity supplying DMA services 637 * @chancnt: how many DMA channels are supported 638 * @privatecnt: how many DMA channels are requested by dma_request_channel 639 * @channels: the list of struct dma_chan 640 * @global_node: list_head for global dma_device_list 641 * @filter: information for device/slave to filter function/param mapping 642 * @cap_mask: one or more dma_capability flags 643 * @max_xor: maximum number of xor sources, 0 if no capability 644 * @max_pq: maximum number of PQ sources and PQ-continue capability 645 * @copy_align: alignment shift for memcpy operations 646 * @xor_align: alignment shift for xor operations 647 * @pq_align: alignment shift for pq operations 648 * @fill_align: alignment shift for memset operations 649 * @dev_id: unique device ID 650 * @dev: struct device reference for dma mapping api 651 * @src_addr_widths: bit mask of src addr widths the device supports 652 * @dst_addr_widths: bit mask of dst addr widths the device supports 653 * @directions: bit mask of slave direction the device supports since 654 * the enum dma_transfer_direction is not defined as bits for 655 * each type of direction, the dma controller should fill (1 << 656 * <TYPE>) and same should be checked by controller as well 657 * @residue_granularity: granularity of the transfer residue reported 658 * by tx_status 659 * @device_alloc_chan_resources: allocate resources and return the 660 * number of allocated descriptors 661 * @device_free_chan_resources: release DMA channel's resources 662 * @device_prep_dma_memcpy: prepares a memcpy operation 663 * @device_prep_dma_xor: prepares a xor operation 664 * @device_prep_dma_xor_val: prepares a xor validation operation 665 * @device_prep_dma_pq: prepares a pq operation 666 * @device_prep_dma_pq_val: prepares a pqzero_sum operation 667 * @device_prep_dma_memset: prepares a memset operation 668 * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list 669 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation 670 * @device_prep_slave_sg: prepares a slave dma operation 671 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio. 672 * The function takes a buffer of size buf_len. The callback function will 673 * be called after period_len bytes have been transferred. 674 * @device_prep_interleaved_dma: Transfer expression in a generic way. 675 * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address 676 * @device_config: Pushes a new configuration to a channel, return 0 or an error 677 * code 678 * @device_pause: Pauses any transfer happening on a channel. Returns 679 * 0 or an error code 680 * @device_resume: Resumes any transfer on a channel previously 681 * paused. Returns 0 or an error code 682 * @device_terminate_all: Aborts all transfers on a channel. Returns 0 683 * or an error code 684 * @device_synchronize: Synchronizes the termination of a transfers to the 685 * current context. 686 * @device_tx_status: poll for transaction completion, the optional 687 * txstate parameter can be supplied with a pointer to get a 688 * struct with auxiliary transfer status information, otherwise the call 689 * will just return a simple status code 690 * @device_issue_pending: push pending transactions to hardware 691 * @descriptor_reuse: a submitted transfer can be resubmitted after completion 692 */ 693 struct dma_device { 694 695 unsigned int chancnt; 696 unsigned int privatecnt; 697 struct list_head channels; 698 struct list_head global_node; 699 struct dma_filter filter; 700 dma_cap_mask_t cap_mask; 701 unsigned short max_xor; 702 unsigned short max_pq; 703 enum dmaengine_alignment copy_align; 704 enum dmaengine_alignment xor_align; 705 enum dmaengine_alignment pq_align; 706 enum dmaengine_alignment fill_align; 707 #define DMA_HAS_PQ_CONTINUE (1 << 15) 708 709 int dev_id; 710 struct device *dev; 711 712 u32 src_addr_widths; 713 u32 dst_addr_widths; 714 u32 directions; 715 bool descriptor_reuse; 716 enum dma_residue_granularity residue_granularity; 717 718 int (*device_alloc_chan_resources)(struct dma_chan *chan); 719 void (*device_free_chan_resources)(struct dma_chan *chan); 720 721 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( 722 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, 723 size_t len, unsigned long flags); 724 struct dma_async_tx_descriptor *(*device_prep_dma_xor)( 725 struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, 726 unsigned int src_cnt, size_t len, unsigned long flags); 727 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( 728 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, 729 size_t len, enum sum_check_flags *result, unsigned long flags); 730 struct dma_async_tx_descriptor *(*device_prep_dma_pq)( 731 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, 732 unsigned int src_cnt, const unsigned char *scf, 733 size_t len, unsigned long flags); 734 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)( 735 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, 736 unsigned int src_cnt, const unsigned char *scf, size_t len, 737 enum sum_check_flags *pqres, unsigned long flags); 738 struct dma_async_tx_descriptor *(*device_prep_dma_memset)( 739 struct dma_chan *chan, dma_addr_t dest, int value, size_t len, 740 unsigned long flags); 741 struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)( 742 struct dma_chan *chan, struct scatterlist *sg, 743 unsigned int nents, int value, unsigned long flags); 744 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( 745 struct dma_chan *chan, unsigned long flags); 746 struct dma_async_tx_descriptor *(*device_prep_dma_sg)( 747 struct dma_chan *chan, 748 struct scatterlist *dst_sg, unsigned int dst_nents, 749 struct scatterlist *src_sg, unsigned int src_nents, 750 unsigned long flags); 751 752 struct dma_async_tx_descriptor *(*device_prep_slave_sg)( 753 struct dma_chan *chan, struct scatterlist *sgl, 754 unsigned int sg_len, enum dma_transfer_direction direction, 755 unsigned long flags, void *context); 756 struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)( 757 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 758 size_t period_len, enum dma_transfer_direction direction, 759 unsigned long flags); 760 struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( 761 struct dma_chan *chan, struct dma_interleaved_template *xt, 762 unsigned long flags); 763 struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)( 764 struct dma_chan *chan, dma_addr_t dst, u64 data, 765 unsigned long flags); 766 767 int (*device_config)(struct dma_chan *chan, 768 struct dma_slave_config *config); 769 int (*device_pause)(struct dma_chan *chan); 770 int (*device_resume)(struct dma_chan *chan); 771 int (*device_terminate_all)(struct dma_chan *chan); 772 void (*device_synchronize)(struct dma_chan *chan); 773 774 enum dma_status (*device_tx_status)(struct dma_chan *chan, 775 dma_cookie_t cookie, 776 struct dma_tx_state *txstate); 777 void (*device_issue_pending)(struct dma_chan *chan); 778 }; 779 780 static inline int dmaengine_slave_config(struct dma_chan *chan, 781 struct dma_slave_config *config) 782 { 783 if (chan->device->device_config) 784 return chan->device->device_config(chan, config); 785 786 return -ENOSYS; 787 } 788 789 static inline bool is_slave_direction(enum dma_transfer_direction direction) 790 { 791 return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM); 792 } 793 794 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single( 795 struct dma_chan *chan, dma_addr_t buf, size_t len, 796 enum dma_transfer_direction dir, unsigned long flags) 797 { 798 struct scatterlist sg; 799 sg_init_table(&sg, 1); 800 sg_dma_address(&sg) = buf; 801 sg_dma_len(&sg) = len; 802 803 return chan->device->device_prep_slave_sg(chan, &sg, 1, 804 dir, flags, NULL); 805 } 806 807 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg( 808 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, 809 enum dma_transfer_direction dir, unsigned long flags) 810 { 811 return chan->device->device_prep_slave_sg(chan, sgl, sg_len, 812 dir, flags, NULL); 813 } 814 815 #ifdef CONFIG_RAPIDIO_DMA_ENGINE 816 struct rio_dma_ext; 817 static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg( 818 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, 819 enum dma_transfer_direction dir, unsigned long flags, 820 struct rio_dma_ext *rio_ext) 821 { 822 return chan->device->device_prep_slave_sg(chan, sgl, sg_len, 823 dir, flags, rio_ext); 824 } 825 #endif 826 827 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic( 828 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 829 size_t period_len, enum dma_transfer_direction dir, 830 unsigned long flags) 831 { 832 return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len, 833 period_len, dir, flags); 834 } 835 836 static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma( 837 struct dma_chan *chan, struct dma_interleaved_template *xt, 838 unsigned long flags) 839 { 840 return chan->device->device_prep_interleaved_dma(chan, xt, flags); 841 } 842 843 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset( 844 struct dma_chan *chan, dma_addr_t dest, int value, size_t len, 845 unsigned long flags) 846 { 847 if (!chan || !chan->device) 848 return NULL; 849 850 return chan->device->device_prep_dma_memset(chan, dest, value, 851 len, flags); 852 } 853 854 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg( 855 struct dma_chan *chan, 856 struct scatterlist *dst_sg, unsigned int dst_nents, 857 struct scatterlist *src_sg, unsigned int src_nents, 858 unsigned long flags) 859 { 860 return chan->device->device_prep_dma_sg(chan, dst_sg, dst_nents, 861 src_sg, src_nents, flags); 862 } 863 864 /** 865 * dmaengine_terminate_all() - Terminate all active DMA transfers 866 * @chan: The channel for which to terminate the transfers 867 * 868 * This function is DEPRECATED use either dmaengine_terminate_sync() or 869 * dmaengine_terminate_async() instead. 870 */ 871 static inline int dmaengine_terminate_all(struct dma_chan *chan) 872 { 873 if (chan->device->device_terminate_all) 874 return chan->device->device_terminate_all(chan); 875 876 return -ENOSYS; 877 } 878 879 /** 880 * dmaengine_terminate_async() - Terminate all active DMA transfers 881 * @chan: The channel for which to terminate the transfers 882 * 883 * Calling this function will terminate all active and pending descriptors 884 * that have previously been submitted to the channel. It is not guaranteed 885 * though that the transfer for the active descriptor has stopped when the 886 * function returns. Furthermore it is possible the complete callback of a 887 * submitted transfer is still running when this function returns. 888 * 889 * dmaengine_synchronize() needs to be called before it is safe to free 890 * any memory that is accessed by previously submitted descriptors or before 891 * freeing any resources accessed from within the completion callback of any 892 * perviously submitted descriptors. 893 * 894 * This function can be called from atomic context as well as from within a 895 * complete callback of a descriptor submitted on the same channel. 896 * 897 * If none of the two conditions above apply consider using 898 * dmaengine_terminate_sync() instead. 899 */ 900 static inline int dmaengine_terminate_async(struct dma_chan *chan) 901 { 902 if (chan->device->device_terminate_all) 903 return chan->device->device_terminate_all(chan); 904 905 return -EINVAL; 906 } 907 908 /** 909 * dmaengine_synchronize() - Synchronize DMA channel termination 910 * @chan: The channel to synchronize 911 * 912 * Synchronizes to the DMA channel termination to the current context. When this 913 * function returns it is guaranteed that all transfers for previously issued 914 * descriptors have stopped and and it is safe to free the memory assoicated 915 * with them. Furthermore it is guaranteed that all complete callback functions 916 * for a previously submitted descriptor have finished running and it is safe to 917 * free resources accessed from within the complete callbacks. 918 * 919 * The behavior of this function is undefined if dma_async_issue_pending() has 920 * been called between dmaengine_terminate_async() and this function. 921 * 922 * This function must only be called from non-atomic context and must not be 923 * called from within a complete callback of a descriptor submitted on the same 924 * channel. 925 */ 926 static inline void dmaengine_synchronize(struct dma_chan *chan) 927 { 928 might_sleep(); 929 930 if (chan->device->device_synchronize) 931 chan->device->device_synchronize(chan); 932 } 933 934 /** 935 * dmaengine_terminate_sync() - Terminate all active DMA transfers 936 * @chan: The channel for which to terminate the transfers 937 * 938 * Calling this function will terminate all active and pending transfers 939 * that have previously been submitted to the channel. It is similar to 940 * dmaengine_terminate_async() but guarantees that the DMA transfer has actually 941 * stopped and that all complete callbacks have finished running when the 942 * function returns. 943 * 944 * This function must only be called from non-atomic context and must not be 945 * called from within a complete callback of a descriptor submitted on the same 946 * channel. 947 */ 948 static inline int dmaengine_terminate_sync(struct dma_chan *chan) 949 { 950 int ret; 951 952 ret = dmaengine_terminate_async(chan); 953 if (ret) 954 return ret; 955 956 dmaengine_synchronize(chan); 957 958 return 0; 959 } 960 961 static inline int dmaengine_pause(struct dma_chan *chan) 962 { 963 if (chan->device->device_pause) 964 return chan->device->device_pause(chan); 965 966 return -ENOSYS; 967 } 968 969 static inline int dmaengine_resume(struct dma_chan *chan) 970 { 971 if (chan->device->device_resume) 972 return chan->device->device_resume(chan); 973 974 return -ENOSYS; 975 } 976 977 static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan, 978 dma_cookie_t cookie, struct dma_tx_state *state) 979 { 980 return chan->device->device_tx_status(chan, cookie, state); 981 } 982 983 static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc) 984 { 985 return desc->tx_submit(desc); 986 } 987 988 static inline bool dmaengine_check_align(enum dmaengine_alignment align, 989 size_t off1, size_t off2, size_t len) 990 { 991 size_t mask; 992 993 if (!align) 994 return true; 995 mask = (1 << align) - 1; 996 if (mask & (off1 | off2 | len)) 997 return false; 998 return true; 999 } 1000 1001 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1, 1002 size_t off2, size_t len) 1003 { 1004 return dmaengine_check_align(dev->copy_align, off1, off2, len); 1005 } 1006 1007 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1, 1008 size_t off2, size_t len) 1009 { 1010 return dmaengine_check_align(dev->xor_align, off1, off2, len); 1011 } 1012 1013 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1, 1014 size_t off2, size_t len) 1015 { 1016 return dmaengine_check_align(dev->pq_align, off1, off2, len); 1017 } 1018 1019 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, 1020 size_t off2, size_t len) 1021 { 1022 return dmaengine_check_align(dev->fill_align, off1, off2, len); 1023 } 1024 1025 static inline void 1026 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) 1027 { 1028 dma->max_pq = maxpq; 1029 if (has_pq_continue) 1030 dma->max_pq |= DMA_HAS_PQ_CONTINUE; 1031 } 1032 1033 static inline bool dmaf_continue(enum dma_ctrl_flags flags) 1034 { 1035 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; 1036 } 1037 1038 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) 1039 { 1040 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; 1041 1042 return (flags & mask) == mask; 1043 } 1044 1045 static inline bool dma_dev_has_pq_continue(struct dma_device *dma) 1046 { 1047 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; 1048 } 1049 1050 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma) 1051 { 1052 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; 1053 } 1054 1055 /* dma_maxpq - reduce maxpq in the face of continued operations 1056 * @dma - dma device with PQ capability 1057 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set 1058 * 1059 * When an engine does not support native continuation we need 3 extra 1060 * source slots to reuse P and Q with the following coefficients: 1061 * 1/ {00} * P : remove P from Q', but use it as a source for P' 1062 * 2/ {01} * Q : use Q to continue Q' calculation 1063 * 3/ {00} * Q : subtract Q from P' to cancel (2) 1064 * 1065 * In the case where P is disabled we only need 1 extra source: 1066 * 1/ {01} * Q : use Q to continue Q' calculation 1067 */ 1068 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) 1069 { 1070 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) 1071 return dma_dev_to_maxpq(dma); 1072 else if (dmaf_p_disabled_continue(flags)) 1073 return dma_dev_to_maxpq(dma) - 1; 1074 else if (dmaf_continue(flags)) 1075 return dma_dev_to_maxpq(dma) - 3; 1076 BUG(); 1077 } 1078 1079 static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg, 1080 size_t dir_icg) 1081 { 1082 if (inc) { 1083 if (dir_icg) 1084 return dir_icg; 1085 else if (sgl) 1086 return icg; 1087 } 1088 1089 return 0; 1090 } 1091 1092 static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt, 1093 struct data_chunk *chunk) 1094 { 1095 return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl, 1096 chunk->icg, chunk->dst_icg); 1097 } 1098 1099 static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt, 1100 struct data_chunk *chunk) 1101 { 1102 return dmaengine_get_icg(xt->src_inc, xt->src_sgl, 1103 chunk->icg, chunk->src_icg); 1104 } 1105 1106 /* --- public DMA engine API --- */ 1107 1108 #ifdef CONFIG_DMA_ENGINE 1109 void dmaengine_get(void); 1110 void dmaengine_put(void); 1111 #else 1112 static inline void dmaengine_get(void) 1113 { 1114 } 1115 static inline void dmaengine_put(void) 1116 { 1117 } 1118 #endif 1119 1120 #ifdef CONFIG_ASYNC_TX_DMA 1121 #define async_dmaengine_get() dmaengine_get() 1122 #define async_dmaengine_put() dmaengine_put() 1123 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH 1124 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) 1125 #else 1126 #define async_dma_find_channel(type) dma_find_channel(type) 1127 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */ 1128 #else 1129 static inline void async_dmaengine_get(void) 1130 { 1131 } 1132 static inline void async_dmaengine_put(void) 1133 { 1134 } 1135 static inline struct dma_chan * 1136 async_dma_find_channel(enum dma_transaction_type type) 1137 { 1138 return NULL; 1139 } 1140 #endif /* CONFIG_ASYNC_TX_DMA */ 1141 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, 1142 struct dma_chan *chan); 1143 1144 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) 1145 { 1146 tx->flags |= DMA_CTRL_ACK; 1147 } 1148 1149 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) 1150 { 1151 tx->flags &= ~DMA_CTRL_ACK; 1152 } 1153 1154 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) 1155 { 1156 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; 1157 } 1158 1159 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) 1160 static inline void 1161 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) 1162 { 1163 set_bit(tx_type, dstp->bits); 1164 } 1165 1166 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) 1167 static inline void 1168 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) 1169 { 1170 clear_bit(tx_type, dstp->bits); 1171 } 1172 1173 #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) 1174 static inline void __dma_cap_zero(dma_cap_mask_t *dstp) 1175 { 1176 bitmap_zero(dstp->bits, DMA_TX_TYPE_END); 1177 } 1178 1179 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) 1180 static inline int 1181 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) 1182 { 1183 return test_bit(tx_type, srcp->bits); 1184 } 1185 1186 #define for_each_dma_cap_mask(cap, mask) \ 1187 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END) 1188 1189 /** 1190 * dma_async_issue_pending - flush pending transactions to HW 1191 * @chan: target DMA channel 1192 * 1193 * This allows drivers to push copies to HW in batches, 1194 * reducing MMIO writes where possible. 1195 */ 1196 static inline void dma_async_issue_pending(struct dma_chan *chan) 1197 { 1198 chan->device->device_issue_pending(chan); 1199 } 1200 1201 /** 1202 * dma_async_is_tx_complete - poll for transaction completion 1203 * @chan: DMA channel 1204 * @cookie: transaction identifier to check status of 1205 * @last: returns last completed cookie, can be NULL 1206 * @used: returns last issued cookie, can be NULL 1207 * 1208 * If @last and @used are passed in, upon return they reflect the driver 1209 * internal state and can be used with dma_async_is_complete() to check 1210 * the status of multiple cookies without re-checking hardware state. 1211 */ 1212 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, 1213 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) 1214 { 1215 struct dma_tx_state state; 1216 enum dma_status status; 1217 1218 status = chan->device->device_tx_status(chan, cookie, &state); 1219 if (last) 1220 *last = state.last; 1221 if (used) 1222 *used = state.used; 1223 return status; 1224 } 1225 1226 /** 1227 * dma_async_is_complete - test a cookie against chan state 1228 * @cookie: transaction identifier to test status of 1229 * @last_complete: last know completed transaction 1230 * @last_used: last cookie value handed out 1231 * 1232 * dma_async_is_complete() is used in dma_async_is_tx_complete() 1233 * the test logic is separated for lightweight testing of multiple cookies 1234 */ 1235 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, 1236 dma_cookie_t last_complete, dma_cookie_t last_used) 1237 { 1238 if (last_complete <= last_used) { 1239 if ((cookie <= last_complete) || (cookie > last_used)) 1240 return DMA_COMPLETE; 1241 } else { 1242 if ((cookie <= last_complete) && (cookie > last_used)) 1243 return DMA_COMPLETE; 1244 } 1245 return DMA_IN_PROGRESS; 1246 } 1247 1248 static inline void 1249 dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue) 1250 { 1251 if (st) { 1252 st->last = last; 1253 st->used = used; 1254 st->residue = residue; 1255 } 1256 } 1257 1258 #ifdef CONFIG_DMA_ENGINE 1259 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); 1260 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); 1261 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); 1262 void dma_issue_pending_all(void); 1263 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, 1264 dma_filter_fn fn, void *fn_param); 1265 struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name); 1266 1267 struct dma_chan *dma_request_chan(struct device *dev, const char *name); 1268 struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask); 1269 1270 void dma_release_channel(struct dma_chan *chan); 1271 int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps); 1272 #else 1273 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) 1274 { 1275 return NULL; 1276 } 1277 static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) 1278 { 1279 return DMA_COMPLETE; 1280 } 1281 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) 1282 { 1283 return DMA_COMPLETE; 1284 } 1285 static inline void dma_issue_pending_all(void) 1286 { 1287 } 1288 static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, 1289 dma_filter_fn fn, void *fn_param) 1290 { 1291 return NULL; 1292 } 1293 static inline struct dma_chan *dma_request_slave_channel(struct device *dev, 1294 const char *name) 1295 { 1296 return NULL; 1297 } 1298 static inline struct dma_chan *dma_request_chan(struct device *dev, 1299 const char *name) 1300 { 1301 return ERR_PTR(-ENODEV); 1302 } 1303 static inline struct dma_chan *dma_request_chan_by_mask( 1304 const dma_cap_mask_t *mask) 1305 { 1306 return ERR_PTR(-ENODEV); 1307 } 1308 static inline void dma_release_channel(struct dma_chan *chan) 1309 { 1310 } 1311 static inline int dma_get_slave_caps(struct dma_chan *chan, 1312 struct dma_slave_caps *caps) 1313 { 1314 return -ENXIO; 1315 } 1316 #endif 1317 1318 #define dma_request_slave_channel_reason(dev, name) dma_request_chan(dev, name) 1319 1320 static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx) 1321 { 1322 struct dma_slave_caps caps; 1323 1324 dma_get_slave_caps(tx->chan, &caps); 1325 1326 if (caps.descriptor_reuse) { 1327 tx->flags |= DMA_CTRL_REUSE; 1328 return 0; 1329 } else { 1330 return -EPERM; 1331 } 1332 } 1333 1334 static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx) 1335 { 1336 tx->flags &= ~DMA_CTRL_REUSE; 1337 } 1338 1339 static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx) 1340 { 1341 return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE; 1342 } 1343 1344 static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc) 1345 { 1346 /* this is supported for reusable desc, so check that */ 1347 if (dmaengine_desc_test_reuse(desc)) 1348 return desc->desc_free(desc); 1349 else 1350 return -EPERM; 1351 } 1352 1353 /* --- DMA device --- */ 1354 1355 int dma_async_device_register(struct dma_device *device); 1356 void dma_async_device_unregister(struct dma_device *device); 1357 void dma_run_dependencies(struct dma_async_tx_descriptor *tx); 1358 struct dma_chan *dma_get_slave_channel(struct dma_chan *chan); 1359 struct dma_chan *dma_get_any_slave_channel(struct dma_device *device); 1360 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) 1361 #define dma_request_slave_channel_compat(mask, x, y, dev, name) \ 1362 __dma_request_slave_channel_compat(&(mask), x, y, dev, name) 1363 1364 static inline struct dma_chan 1365 *__dma_request_slave_channel_compat(const dma_cap_mask_t *mask, 1366 dma_filter_fn fn, void *fn_param, 1367 struct device *dev, const char *name) 1368 { 1369 struct dma_chan *chan; 1370 1371 chan = dma_request_slave_channel(dev, name); 1372 if (chan) 1373 return chan; 1374 1375 if (!fn || !fn_param) 1376 return NULL; 1377 1378 return __dma_request_channel(mask, fn, fn_param); 1379 } 1380 #endif /* DMAENGINE_H */ 1381