1 /* 2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called COPYING. 16 */ 17 #ifndef LINUX_DMAENGINE_H 18 #define LINUX_DMAENGINE_H 19 20 #include <linux/device.h> 21 #include <linux/err.h> 22 #include <linux/uio.h> 23 #include <linux/bug.h> 24 #include <linux/scatterlist.h> 25 #include <linux/bitmap.h> 26 #include <linux/types.h> 27 #include <asm/page.h> 28 29 /** 30 * typedef dma_cookie_t - an opaque DMA cookie 31 * 32 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code 33 */ 34 typedef s32 dma_cookie_t; 35 #define DMA_MIN_COOKIE 1 36 37 static inline int dma_submit_error(dma_cookie_t cookie) 38 { 39 return cookie < 0 ? cookie : 0; 40 } 41 42 /** 43 * enum dma_status - DMA transaction status 44 * @DMA_COMPLETE: transaction completed 45 * @DMA_IN_PROGRESS: transaction not yet processed 46 * @DMA_PAUSED: transaction is paused 47 * @DMA_ERROR: transaction failed 48 */ 49 enum dma_status { 50 DMA_COMPLETE, 51 DMA_IN_PROGRESS, 52 DMA_PAUSED, 53 DMA_ERROR, 54 }; 55 56 /** 57 * enum dma_transaction_type - DMA transaction types/indexes 58 * 59 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is 60 * automatically set as dma devices are registered. 61 */ 62 enum dma_transaction_type { 63 DMA_MEMCPY, 64 DMA_XOR, 65 DMA_PQ, 66 DMA_XOR_VAL, 67 DMA_PQ_VAL, 68 DMA_MEMSET, 69 DMA_MEMSET_SG, 70 DMA_INTERRUPT, 71 DMA_SG, 72 DMA_PRIVATE, 73 DMA_ASYNC_TX, 74 DMA_SLAVE, 75 DMA_CYCLIC, 76 DMA_INTERLEAVE, 77 /* last transaction type for creation of the capabilities mask */ 78 DMA_TX_TYPE_END, 79 }; 80 81 /** 82 * enum dma_transfer_direction - dma transfer mode and direction indicator 83 * @DMA_MEM_TO_MEM: Async/Memcpy mode 84 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device 85 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory 86 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device 87 */ 88 enum dma_transfer_direction { 89 DMA_MEM_TO_MEM, 90 DMA_MEM_TO_DEV, 91 DMA_DEV_TO_MEM, 92 DMA_DEV_TO_DEV, 93 DMA_TRANS_NONE, 94 }; 95 96 /** 97 * Interleaved Transfer Request 98 * ---------------------------- 99 * A chunk is collection of contiguous bytes to be transfered. 100 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG). 101 * ICGs may or maynot change between chunks. 102 * A FRAME is the smallest series of contiguous {chunk,icg} pairs, 103 * that when repeated an integral number of times, specifies the transfer. 104 * A transfer template is specification of a Frame, the number of times 105 * it is to be repeated and other per-transfer attributes. 106 * 107 * Practically, a client driver would have ready a template for each 108 * type of transfer it is going to need during its lifetime and 109 * set only 'src_start' and 'dst_start' before submitting the requests. 110 * 111 * 112 * | Frame-1 | Frame-2 | ~ | Frame-'numf' | 113 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...| 114 * 115 * == Chunk size 116 * ... ICG 117 */ 118 119 /** 120 * struct data_chunk - Element of scatter-gather list that makes a frame. 121 * @size: Number of bytes to read from source. 122 * size_dst := fn(op, size_src), so doesn't mean much for destination. 123 * @icg: Number of bytes to jump after last src/dst address of this 124 * chunk and before first src/dst address for next chunk. 125 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false. 126 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false. 127 * @dst_icg: Number of bytes to jump after last dst address of this 128 * chunk and before the first dst address for next chunk. 129 * Ignored if dst_inc is true and dst_sgl is false. 130 * @src_icg: Number of bytes to jump after last src address of this 131 * chunk and before the first src address for next chunk. 132 * Ignored if src_inc is true and src_sgl is false. 133 */ 134 struct data_chunk { 135 size_t size; 136 size_t icg; 137 size_t dst_icg; 138 size_t src_icg; 139 }; 140 141 /** 142 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern 143 * and attributes. 144 * @src_start: Bus address of source for the first chunk. 145 * @dst_start: Bus address of destination for the first chunk. 146 * @dir: Specifies the type of Source and Destination. 147 * @src_inc: If the source address increments after reading from it. 148 * @dst_inc: If the destination address increments after writing to it. 149 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read). 150 * Otherwise, source is read contiguously (icg ignored). 151 * Ignored if src_inc is false. 152 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write). 153 * Otherwise, destination is filled contiguously (icg ignored). 154 * Ignored if dst_inc is false. 155 * @numf: Number of frames in this template. 156 * @frame_size: Number of chunks in a frame i.e, size of sgl[]. 157 * @sgl: Array of {chunk,icg} pairs that make up a frame. 158 */ 159 struct dma_interleaved_template { 160 dma_addr_t src_start; 161 dma_addr_t dst_start; 162 enum dma_transfer_direction dir; 163 bool src_inc; 164 bool dst_inc; 165 bool src_sgl; 166 bool dst_sgl; 167 size_t numf; 168 size_t frame_size; 169 struct data_chunk sgl[0]; 170 }; 171 172 /** 173 * enum dma_ctrl_flags - DMA flags to augment operation preparation, 174 * control completion, and communicate status. 175 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of 176 * this transaction 177 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client 178 * acknowledges receipt, i.e. has has a chance to establish any dependency 179 * chains 180 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q 181 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P 182 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as 183 * sources that were the result of a previous operation, in the case of a PQ 184 * operation it continues the calculation with new sources 185 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend 186 * on the result of this operation 187 * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till 188 * cleared or freed 189 */ 190 enum dma_ctrl_flags { 191 DMA_PREP_INTERRUPT = (1 << 0), 192 DMA_CTRL_ACK = (1 << 1), 193 DMA_PREP_PQ_DISABLE_P = (1 << 2), 194 DMA_PREP_PQ_DISABLE_Q = (1 << 3), 195 DMA_PREP_CONTINUE = (1 << 4), 196 DMA_PREP_FENCE = (1 << 5), 197 DMA_CTRL_REUSE = (1 << 6), 198 }; 199 200 /** 201 * enum sum_check_bits - bit position of pq_check_flags 202 */ 203 enum sum_check_bits { 204 SUM_CHECK_P = 0, 205 SUM_CHECK_Q = 1, 206 }; 207 208 /** 209 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations 210 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise 211 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise 212 */ 213 enum sum_check_flags { 214 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P), 215 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q), 216 }; 217 218 219 /** 220 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. 221 * See linux/cpumask.h 222 */ 223 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; 224 225 /** 226 * struct dma_chan_percpu - the per-CPU part of struct dma_chan 227 * @memcpy_count: transaction counter 228 * @bytes_transferred: byte counter 229 */ 230 231 struct dma_chan_percpu { 232 /* stats */ 233 unsigned long memcpy_count; 234 unsigned long bytes_transferred; 235 }; 236 237 /** 238 * struct dma_router - DMA router structure 239 * @dev: pointer to the DMA router device 240 * @route_free: function to be called when the route can be disconnected 241 */ 242 struct dma_router { 243 struct device *dev; 244 void (*route_free)(struct device *dev, void *route_data); 245 }; 246 247 /** 248 * struct dma_chan - devices supply DMA channels, clients use them 249 * @device: ptr to the dma device who supplies this channel, always !%NULL 250 * @cookie: last cookie value returned to client 251 * @completed_cookie: last completed cookie for this channel 252 * @chan_id: channel ID for sysfs 253 * @dev: class device for sysfs 254 * @device_node: used to add this to the device chan list 255 * @local: per-cpu pointer to a struct dma_chan_percpu 256 * @client_count: how many clients are using this channel 257 * @table_count: number of appearances in the mem-to-mem allocation table 258 * @router: pointer to the DMA router structure 259 * @route_data: channel specific data for the router 260 * @private: private data for certain client-channel associations 261 */ 262 struct dma_chan { 263 struct dma_device *device; 264 dma_cookie_t cookie; 265 dma_cookie_t completed_cookie; 266 267 /* sysfs */ 268 int chan_id; 269 struct dma_chan_dev *dev; 270 271 struct list_head device_node; 272 struct dma_chan_percpu __percpu *local; 273 int client_count; 274 int table_count; 275 276 /* DMA router */ 277 struct dma_router *router; 278 void *route_data; 279 280 void *private; 281 }; 282 283 /** 284 * struct dma_chan_dev - relate sysfs device node to backing channel device 285 * @chan: driver channel device 286 * @device: sysfs device 287 * @dev_id: parent dma_device dev_id 288 * @idr_ref: reference count to gate release of dma_device dev_id 289 */ 290 struct dma_chan_dev { 291 struct dma_chan *chan; 292 struct device device; 293 int dev_id; 294 atomic_t *idr_ref; 295 }; 296 297 /** 298 * enum dma_slave_buswidth - defines bus width of the DMA slave 299 * device, source or target buses 300 */ 301 enum dma_slave_buswidth { 302 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, 303 DMA_SLAVE_BUSWIDTH_1_BYTE = 1, 304 DMA_SLAVE_BUSWIDTH_2_BYTES = 2, 305 DMA_SLAVE_BUSWIDTH_3_BYTES = 3, 306 DMA_SLAVE_BUSWIDTH_4_BYTES = 4, 307 DMA_SLAVE_BUSWIDTH_8_BYTES = 8, 308 DMA_SLAVE_BUSWIDTH_16_BYTES = 16, 309 DMA_SLAVE_BUSWIDTH_32_BYTES = 32, 310 DMA_SLAVE_BUSWIDTH_64_BYTES = 64, 311 }; 312 313 /** 314 * struct dma_slave_config - dma slave channel runtime config 315 * @direction: whether the data shall go in or out on this slave 316 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are 317 * legal values. DEPRECATED, drivers should use the direction argument 318 * to the device_prep_slave_sg and device_prep_dma_cyclic functions or 319 * the dir field in the dma_interleaved_template structure. 320 * @src_addr: this is the physical address where DMA slave data 321 * should be read (RX), if the source is memory this argument is 322 * ignored. 323 * @dst_addr: this is the physical address where DMA slave data 324 * should be written (TX), if the source is memory this argument 325 * is ignored. 326 * @src_addr_width: this is the width in bytes of the source (RX) 327 * register where DMA data shall be read. If the source 328 * is memory this may be ignored depending on architecture. 329 * Legal values: 1, 2, 4, 8. 330 * @dst_addr_width: same as src_addr_width but for destination 331 * target (TX) mutatis mutandis. 332 * @src_maxburst: the maximum number of words (note: words, as in 333 * units of the src_addr_width member, not bytes) that can be sent 334 * in one burst to the device. Typically something like half the 335 * FIFO depth on I/O peripherals so you don't overflow it. This 336 * may or may not be applicable on memory sources. 337 * @dst_maxburst: same as src_maxburst but for destination target 338 * mutatis mutandis. 339 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill 340 * with 'true' if peripheral should be flow controller. Direction will be 341 * selected at Runtime. 342 * @slave_id: Slave requester id. Only valid for slave channels. The dma 343 * slave peripheral will have unique id as dma requester which need to be 344 * pass as slave config. 345 * 346 * This struct is passed in as configuration data to a DMA engine 347 * in order to set up a certain channel for DMA transport at runtime. 348 * The DMA device/engine has to provide support for an additional 349 * callback in the dma_device structure, device_config and this struct 350 * will then be passed in as an argument to the function. 351 * 352 * The rationale for adding configuration information to this struct is as 353 * follows: if it is likely that more than one DMA slave controllers in 354 * the world will support the configuration option, then make it generic. 355 * If not: if it is fixed so that it be sent in static from the platform 356 * data, then prefer to do that. 357 */ 358 struct dma_slave_config { 359 enum dma_transfer_direction direction; 360 phys_addr_t src_addr; 361 phys_addr_t dst_addr; 362 enum dma_slave_buswidth src_addr_width; 363 enum dma_slave_buswidth dst_addr_width; 364 u32 src_maxburst; 365 u32 dst_maxburst; 366 bool device_fc; 367 unsigned int slave_id; 368 }; 369 370 /** 371 * enum dma_residue_granularity - Granularity of the reported transfer residue 372 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The 373 * DMA channel is only able to tell whether a descriptor has been completed or 374 * not, which means residue reporting is not supported by this channel. The 375 * residue field of the dma_tx_state field will always be 0. 376 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully 377 * completed segment of the transfer (For cyclic transfers this is after each 378 * period). This is typically implemented by having the hardware generate an 379 * interrupt after each transferred segment and then the drivers updates the 380 * outstanding residue by the size of the segment. Another possibility is if 381 * the hardware supports scatter-gather and the segment descriptor has a field 382 * which gets set after the segment has been completed. The driver then counts 383 * the number of segments without the flag set to compute the residue. 384 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred 385 * burst. This is typically only supported if the hardware has a progress 386 * register of some sort (E.g. a register with the current read/write address 387 * or a register with the amount of bursts/beats/bytes that have been 388 * transferred or still need to be transferred). 389 */ 390 enum dma_residue_granularity { 391 DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0, 392 DMA_RESIDUE_GRANULARITY_SEGMENT = 1, 393 DMA_RESIDUE_GRANULARITY_BURST = 2, 394 }; 395 396 /* struct dma_slave_caps - expose capabilities of a slave channel only 397 * 398 * @src_addr_widths: bit mask of src addr widths the channel supports 399 * @dst_addr_widths: bit mask of dstn addr widths the channel supports 400 * @directions: bit mask of slave direction the channel supported 401 * since the enum dma_transfer_direction is not defined as bits for each 402 * type of direction, the dma controller should fill (1 << <TYPE>) and same 403 * should be checked by controller as well 404 * @max_burst: max burst capability per-transfer 405 * @cmd_pause: true, if pause and thereby resume is supported 406 * @cmd_terminate: true, if terminate cmd is supported 407 * @residue_granularity: granularity of the reported transfer residue 408 * @descriptor_reuse: if a descriptor can be reused by client and 409 * resubmitted multiple times 410 */ 411 struct dma_slave_caps { 412 u32 src_addr_widths; 413 u32 dst_addr_widths; 414 u32 directions; 415 u32 max_burst; 416 bool cmd_pause; 417 bool cmd_terminate; 418 enum dma_residue_granularity residue_granularity; 419 bool descriptor_reuse; 420 }; 421 422 static inline const char *dma_chan_name(struct dma_chan *chan) 423 { 424 return dev_name(&chan->dev->device); 425 } 426 427 void dma_chan_cleanup(struct kref *kref); 428 429 /** 430 * typedef dma_filter_fn - callback filter for dma_request_channel 431 * @chan: channel to be reviewed 432 * @filter_param: opaque parameter passed through dma_request_channel 433 * 434 * When this optional parameter is specified in a call to dma_request_channel a 435 * suitable channel is passed to this routine for further dispositioning before 436 * being returned. Where 'suitable' indicates a non-busy channel that 437 * satisfies the given capability mask. It returns 'true' to indicate that the 438 * channel is suitable. 439 */ 440 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); 441 442 typedef void (*dma_async_tx_callback)(void *dma_async_param); 443 444 enum dmaengine_tx_result { 445 DMA_TRANS_NOERROR = 0, /* SUCCESS */ 446 DMA_TRANS_READ_FAILED, /* Source DMA read failed */ 447 DMA_TRANS_WRITE_FAILED, /* Destination DMA write failed */ 448 DMA_TRANS_ABORTED, /* Op never submitted / aborted */ 449 }; 450 451 struct dmaengine_result { 452 enum dmaengine_tx_result result; 453 u32 residue; 454 }; 455 456 typedef void (*dma_async_tx_callback_result)(void *dma_async_param, 457 const struct dmaengine_result *result); 458 459 struct dmaengine_unmap_data { 460 u8 map_cnt; 461 u8 to_cnt; 462 u8 from_cnt; 463 u8 bidi_cnt; 464 struct device *dev; 465 struct kref kref; 466 size_t len; 467 dma_addr_t addr[0]; 468 }; 469 470 /** 471 * struct dma_async_tx_descriptor - async transaction descriptor 472 * ---dma generic offload fields--- 473 * @cookie: tracking cookie for this transaction, set to -EBUSY if 474 * this tx is sitting on a dependency list 475 * @flags: flags to augment operation preparation, control completion, and 476 * communicate status 477 * @phys: physical address of the descriptor 478 * @chan: target channel for this operation 479 * @tx_submit: accept the descriptor, assign ordered cookie and mark the 480 * descriptor pending. To be pushed on .issue_pending() call 481 * @callback: routine to call after this operation is complete 482 * @callback_param: general parameter to pass to the callback routine 483 * ---async_tx api specific fields--- 484 * @next: at completion submit this descriptor 485 * @parent: pointer to the next level up in the dependency chain 486 * @lock: protect the parent and next pointers 487 */ 488 struct dma_async_tx_descriptor { 489 dma_cookie_t cookie; 490 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ 491 dma_addr_t phys; 492 struct dma_chan *chan; 493 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); 494 int (*desc_free)(struct dma_async_tx_descriptor *tx); 495 dma_async_tx_callback callback; 496 dma_async_tx_callback_result callback_result; 497 void *callback_param; 498 struct dmaengine_unmap_data *unmap; 499 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH 500 struct dma_async_tx_descriptor *next; 501 struct dma_async_tx_descriptor *parent; 502 spinlock_t lock; 503 #endif 504 }; 505 506 #ifdef CONFIG_DMA_ENGINE 507 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, 508 struct dmaengine_unmap_data *unmap) 509 { 510 kref_get(&unmap->kref); 511 tx->unmap = unmap; 512 } 513 514 struct dmaengine_unmap_data * 515 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags); 516 void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap); 517 #else 518 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, 519 struct dmaengine_unmap_data *unmap) 520 { 521 } 522 static inline struct dmaengine_unmap_data * 523 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags) 524 { 525 return NULL; 526 } 527 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap) 528 { 529 } 530 #endif 531 532 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx) 533 { 534 if (tx->unmap) { 535 dmaengine_unmap_put(tx->unmap); 536 tx->unmap = NULL; 537 } 538 } 539 540 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH 541 static inline void txd_lock(struct dma_async_tx_descriptor *txd) 542 { 543 } 544 static inline void txd_unlock(struct dma_async_tx_descriptor *txd) 545 { 546 } 547 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) 548 { 549 BUG(); 550 } 551 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) 552 { 553 } 554 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) 555 { 556 } 557 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) 558 { 559 return NULL; 560 } 561 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) 562 { 563 return NULL; 564 } 565 566 #else 567 static inline void txd_lock(struct dma_async_tx_descriptor *txd) 568 { 569 spin_lock_bh(&txd->lock); 570 } 571 static inline void txd_unlock(struct dma_async_tx_descriptor *txd) 572 { 573 spin_unlock_bh(&txd->lock); 574 } 575 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) 576 { 577 txd->next = next; 578 next->parent = txd; 579 } 580 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) 581 { 582 txd->parent = NULL; 583 } 584 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) 585 { 586 txd->next = NULL; 587 } 588 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) 589 { 590 return txd->parent; 591 } 592 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) 593 { 594 return txd->next; 595 } 596 #endif 597 598 /** 599 * struct dma_tx_state - filled in to report the status of 600 * a transfer. 601 * @last: last completed DMA cookie 602 * @used: last issued DMA cookie (i.e. the one in progress) 603 * @residue: the remaining number of bytes left to transmit 604 * on the selected transfer for states DMA_IN_PROGRESS and 605 * DMA_PAUSED if this is implemented in the driver, else 0 606 */ 607 struct dma_tx_state { 608 dma_cookie_t last; 609 dma_cookie_t used; 610 u32 residue; 611 }; 612 613 /** 614 * enum dmaengine_alignment - defines alignment of the DMA async tx 615 * buffers 616 */ 617 enum dmaengine_alignment { 618 DMAENGINE_ALIGN_1_BYTE = 0, 619 DMAENGINE_ALIGN_2_BYTES = 1, 620 DMAENGINE_ALIGN_4_BYTES = 2, 621 DMAENGINE_ALIGN_8_BYTES = 3, 622 DMAENGINE_ALIGN_16_BYTES = 4, 623 DMAENGINE_ALIGN_32_BYTES = 5, 624 DMAENGINE_ALIGN_64_BYTES = 6, 625 }; 626 627 /** 628 * struct dma_slave_map - associates slave device and it's slave channel with 629 * parameter to be used by a filter function 630 * @devname: name of the device 631 * @slave: slave channel name 632 * @param: opaque parameter to pass to struct dma_filter.fn 633 */ 634 struct dma_slave_map { 635 const char *devname; 636 const char *slave; 637 void *param; 638 }; 639 640 /** 641 * struct dma_filter - information for slave device/channel to filter_fn/param 642 * mapping 643 * @fn: filter function callback 644 * @mapcnt: number of slave device/channel in the map 645 * @map: array of channel to filter mapping data 646 */ 647 struct dma_filter { 648 dma_filter_fn fn; 649 int mapcnt; 650 const struct dma_slave_map *map; 651 }; 652 653 /** 654 * struct dma_device - info on the entity supplying DMA services 655 * @chancnt: how many DMA channels are supported 656 * @privatecnt: how many DMA channels are requested by dma_request_channel 657 * @channels: the list of struct dma_chan 658 * @global_node: list_head for global dma_device_list 659 * @filter: information for device/slave to filter function/param mapping 660 * @cap_mask: one or more dma_capability flags 661 * @max_xor: maximum number of xor sources, 0 if no capability 662 * @max_pq: maximum number of PQ sources and PQ-continue capability 663 * @copy_align: alignment shift for memcpy operations 664 * @xor_align: alignment shift for xor operations 665 * @pq_align: alignment shift for pq operations 666 * @fill_align: alignment shift for memset operations 667 * @dev_id: unique device ID 668 * @dev: struct device reference for dma mapping api 669 * @src_addr_widths: bit mask of src addr widths the device supports 670 * @dst_addr_widths: bit mask of dst addr widths the device supports 671 * @directions: bit mask of slave direction the device supports since 672 * the enum dma_transfer_direction is not defined as bits for 673 * each type of direction, the dma controller should fill (1 << 674 * <TYPE>) and same should be checked by controller as well 675 * @max_burst: max burst capability per-transfer 676 * @residue_granularity: granularity of the transfer residue reported 677 * by tx_status 678 * @device_alloc_chan_resources: allocate resources and return the 679 * number of allocated descriptors 680 * @device_free_chan_resources: release DMA channel's resources 681 * @device_prep_dma_memcpy: prepares a memcpy operation 682 * @device_prep_dma_xor: prepares a xor operation 683 * @device_prep_dma_xor_val: prepares a xor validation operation 684 * @device_prep_dma_pq: prepares a pq operation 685 * @device_prep_dma_pq_val: prepares a pqzero_sum operation 686 * @device_prep_dma_memset: prepares a memset operation 687 * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list 688 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation 689 * @device_prep_slave_sg: prepares a slave dma operation 690 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio. 691 * The function takes a buffer of size buf_len. The callback function will 692 * be called after period_len bytes have been transferred. 693 * @device_prep_interleaved_dma: Transfer expression in a generic way. 694 * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address 695 * @device_config: Pushes a new configuration to a channel, return 0 or an error 696 * code 697 * @device_pause: Pauses any transfer happening on a channel. Returns 698 * 0 or an error code 699 * @device_resume: Resumes any transfer on a channel previously 700 * paused. Returns 0 or an error code 701 * @device_terminate_all: Aborts all transfers on a channel. Returns 0 702 * or an error code 703 * @device_synchronize: Synchronizes the termination of a transfers to the 704 * current context. 705 * @device_tx_status: poll for transaction completion, the optional 706 * txstate parameter can be supplied with a pointer to get a 707 * struct with auxiliary transfer status information, otherwise the call 708 * will just return a simple status code 709 * @device_issue_pending: push pending transactions to hardware 710 * @descriptor_reuse: a submitted transfer can be resubmitted after completion 711 */ 712 struct dma_device { 713 714 unsigned int chancnt; 715 unsigned int privatecnt; 716 struct list_head channels; 717 struct list_head global_node; 718 struct dma_filter filter; 719 dma_cap_mask_t cap_mask; 720 unsigned short max_xor; 721 unsigned short max_pq; 722 enum dmaengine_alignment copy_align; 723 enum dmaengine_alignment xor_align; 724 enum dmaengine_alignment pq_align; 725 enum dmaengine_alignment fill_align; 726 #define DMA_HAS_PQ_CONTINUE (1 << 15) 727 728 int dev_id; 729 struct device *dev; 730 731 u32 src_addr_widths; 732 u32 dst_addr_widths; 733 u32 directions; 734 u32 max_burst; 735 bool descriptor_reuse; 736 enum dma_residue_granularity residue_granularity; 737 738 int (*device_alloc_chan_resources)(struct dma_chan *chan); 739 void (*device_free_chan_resources)(struct dma_chan *chan); 740 741 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( 742 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, 743 size_t len, unsigned long flags); 744 struct dma_async_tx_descriptor *(*device_prep_dma_xor)( 745 struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, 746 unsigned int src_cnt, size_t len, unsigned long flags); 747 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( 748 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, 749 size_t len, enum sum_check_flags *result, unsigned long flags); 750 struct dma_async_tx_descriptor *(*device_prep_dma_pq)( 751 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, 752 unsigned int src_cnt, const unsigned char *scf, 753 size_t len, unsigned long flags); 754 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)( 755 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, 756 unsigned int src_cnt, const unsigned char *scf, size_t len, 757 enum sum_check_flags *pqres, unsigned long flags); 758 struct dma_async_tx_descriptor *(*device_prep_dma_memset)( 759 struct dma_chan *chan, dma_addr_t dest, int value, size_t len, 760 unsigned long flags); 761 struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)( 762 struct dma_chan *chan, struct scatterlist *sg, 763 unsigned int nents, int value, unsigned long flags); 764 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( 765 struct dma_chan *chan, unsigned long flags); 766 struct dma_async_tx_descriptor *(*device_prep_dma_sg)( 767 struct dma_chan *chan, 768 struct scatterlist *dst_sg, unsigned int dst_nents, 769 struct scatterlist *src_sg, unsigned int src_nents, 770 unsigned long flags); 771 772 struct dma_async_tx_descriptor *(*device_prep_slave_sg)( 773 struct dma_chan *chan, struct scatterlist *sgl, 774 unsigned int sg_len, enum dma_transfer_direction direction, 775 unsigned long flags, void *context); 776 struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)( 777 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 778 size_t period_len, enum dma_transfer_direction direction, 779 unsigned long flags); 780 struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( 781 struct dma_chan *chan, struct dma_interleaved_template *xt, 782 unsigned long flags); 783 struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)( 784 struct dma_chan *chan, dma_addr_t dst, u64 data, 785 unsigned long flags); 786 787 int (*device_config)(struct dma_chan *chan, 788 struct dma_slave_config *config); 789 int (*device_pause)(struct dma_chan *chan); 790 int (*device_resume)(struct dma_chan *chan); 791 int (*device_terminate_all)(struct dma_chan *chan); 792 void (*device_synchronize)(struct dma_chan *chan); 793 794 enum dma_status (*device_tx_status)(struct dma_chan *chan, 795 dma_cookie_t cookie, 796 struct dma_tx_state *txstate); 797 void (*device_issue_pending)(struct dma_chan *chan); 798 }; 799 800 static inline int dmaengine_slave_config(struct dma_chan *chan, 801 struct dma_slave_config *config) 802 { 803 if (chan->device->device_config) 804 return chan->device->device_config(chan, config); 805 806 return -ENOSYS; 807 } 808 809 static inline bool is_slave_direction(enum dma_transfer_direction direction) 810 { 811 return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM); 812 } 813 814 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single( 815 struct dma_chan *chan, dma_addr_t buf, size_t len, 816 enum dma_transfer_direction dir, unsigned long flags) 817 { 818 struct scatterlist sg; 819 sg_init_table(&sg, 1); 820 sg_dma_address(&sg) = buf; 821 sg_dma_len(&sg) = len; 822 823 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) 824 return NULL; 825 826 return chan->device->device_prep_slave_sg(chan, &sg, 1, 827 dir, flags, NULL); 828 } 829 830 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg( 831 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, 832 enum dma_transfer_direction dir, unsigned long flags) 833 { 834 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) 835 return NULL; 836 837 return chan->device->device_prep_slave_sg(chan, sgl, sg_len, 838 dir, flags, NULL); 839 } 840 841 #ifdef CONFIG_RAPIDIO_DMA_ENGINE 842 struct rio_dma_ext; 843 static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg( 844 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, 845 enum dma_transfer_direction dir, unsigned long flags, 846 struct rio_dma_ext *rio_ext) 847 { 848 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) 849 return NULL; 850 851 return chan->device->device_prep_slave_sg(chan, sgl, sg_len, 852 dir, flags, rio_ext); 853 } 854 #endif 855 856 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic( 857 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 858 size_t period_len, enum dma_transfer_direction dir, 859 unsigned long flags) 860 { 861 if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic) 862 return NULL; 863 864 return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len, 865 period_len, dir, flags); 866 } 867 868 static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma( 869 struct dma_chan *chan, struct dma_interleaved_template *xt, 870 unsigned long flags) 871 { 872 if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma) 873 return NULL; 874 875 return chan->device->device_prep_interleaved_dma(chan, xt, flags); 876 } 877 878 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset( 879 struct dma_chan *chan, dma_addr_t dest, int value, size_t len, 880 unsigned long flags) 881 { 882 if (!chan || !chan->device || !chan->device->device_prep_dma_memset) 883 return NULL; 884 885 return chan->device->device_prep_dma_memset(chan, dest, value, 886 len, flags); 887 } 888 889 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg( 890 struct dma_chan *chan, 891 struct scatterlist *dst_sg, unsigned int dst_nents, 892 struct scatterlist *src_sg, unsigned int src_nents, 893 unsigned long flags) 894 { 895 if (!chan || !chan->device || !chan->device->device_prep_dma_sg) 896 return NULL; 897 898 return chan->device->device_prep_dma_sg(chan, dst_sg, dst_nents, 899 src_sg, src_nents, flags); 900 } 901 902 /** 903 * dmaengine_terminate_all() - Terminate all active DMA transfers 904 * @chan: The channel for which to terminate the transfers 905 * 906 * This function is DEPRECATED use either dmaengine_terminate_sync() or 907 * dmaengine_terminate_async() instead. 908 */ 909 static inline int dmaengine_terminate_all(struct dma_chan *chan) 910 { 911 if (chan->device->device_terminate_all) 912 return chan->device->device_terminate_all(chan); 913 914 return -ENOSYS; 915 } 916 917 /** 918 * dmaengine_terminate_async() - Terminate all active DMA transfers 919 * @chan: The channel for which to terminate the transfers 920 * 921 * Calling this function will terminate all active and pending descriptors 922 * that have previously been submitted to the channel. It is not guaranteed 923 * though that the transfer for the active descriptor has stopped when the 924 * function returns. Furthermore it is possible the complete callback of a 925 * submitted transfer is still running when this function returns. 926 * 927 * dmaengine_synchronize() needs to be called before it is safe to free 928 * any memory that is accessed by previously submitted descriptors or before 929 * freeing any resources accessed from within the completion callback of any 930 * perviously submitted descriptors. 931 * 932 * This function can be called from atomic context as well as from within a 933 * complete callback of a descriptor submitted on the same channel. 934 * 935 * If none of the two conditions above apply consider using 936 * dmaengine_terminate_sync() instead. 937 */ 938 static inline int dmaengine_terminate_async(struct dma_chan *chan) 939 { 940 if (chan->device->device_terminate_all) 941 return chan->device->device_terminate_all(chan); 942 943 return -EINVAL; 944 } 945 946 /** 947 * dmaengine_synchronize() - Synchronize DMA channel termination 948 * @chan: The channel to synchronize 949 * 950 * Synchronizes to the DMA channel termination to the current context. When this 951 * function returns it is guaranteed that all transfers for previously issued 952 * descriptors have stopped and and it is safe to free the memory assoicated 953 * with them. Furthermore it is guaranteed that all complete callback functions 954 * for a previously submitted descriptor have finished running and it is safe to 955 * free resources accessed from within the complete callbacks. 956 * 957 * The behavior of this function is undefined if dma_async_issue_pending() has 958 * been called between dmaengine_terminate_async() and this function. 959 * 960 * This function must only be called from non-atomic context and must not be 961 * called from within a complete callback of a descriptor submitted on the same 962 * channel. 963 */ 964 static inline void dmaengine_synchronize(struct dma_chan *chan) 965 { 966 might_sleep(); 967 968 if (chan->device->device_synchronize) 969 chan->device->device_synchronize(chan); 970 } 971 972 /** 973 * dmaengine_terminate_sync() - Terminate all active DMA transfers 974 * @chan: The channel for which to terminate the transfers 975 * 976 * Calling this function will terminate all active and pending transfers 977 * that have previously been submitted to the channel. It is similar to 978 * dmaengine_terminate_async() but guarantees that the DMA transfer has actually 979 * stopped and that all complete callbacks have finished running when the 980 * function returns. 981 * 982 * This function must only be called from non-atomic context and must not be 983 * called from within a complete callback of a descriptor submitted on the same 984 * channel. 985 */ 986 static inline int dmaengine_terminate_sync(struct dma_chan *chan) 987 { 988 int ret; 989 990 ret = dmaengine_terminate_async(chan); 991 if (ret) 992 return ret; 993 994 dmaengine_synchronize(chan); 995 996 return 0; 997 } 998 999 static inline int dmaengine_pause(struct dma_chan *chan) 1000 { 1001 if (chan->device->device_pause) 1002 return chan->device->device_pause(chan); 1003 1004 return -ENOSYS; 1005 } 1006 1007 static inline int dmaengine_resume(struct dma_chan *chan) 1008 { 1009 if (chan->device->device_resume) 1010 return chan->device->device_resume(chan); 1011 1012 return -ENOSYS; 1013 } 1014 1015 static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan, 1016 dma_cookie_t cookie, struct dma_tx_state *state) 1017 { 1018 return chan->device->device_tx_status(chan, cookie, state); 1019 } 1020 1021 static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc) 1022 { 1023 return desc->tx_submit(desc); 1024 } 1025 1026 static inline bool dmaengine_check_align(enum dmaengine_alignment align, 1027 size_t off1, size_t off2, size_t len) 1028 { 1029 size_t mask; 1030 1031 if (!align) 1032 return true; 1033 mask = (1 << align) - 1; 1034 if (mask & (off1 | off2 | len)) 1035 return false; 1036 return true; 1037 } 1038 1039 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1, 1040 size_t off2, size_t len) 1041 { 1042 return dmaengine_check_align(dev->copy_align, off1, off2, len); 1043 } 1044 1045 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1, 1046 size_t off2, size_t len) 1047 { 1048 return dmaengine_check_align(dev->xor_align, off1, off2, len); 1049 } 1050 1051 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1, 1052 size_t off2, size_t len) 1053 { 1054 return dmaengine_check_align(dev->pq_align, off1, off2, len); 1055 } 1056 1057 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, 1058 size_t off2, size_t len) 1059 { 1060 return dmaengine_check_align(dev->fill_align, off1, off2, len); 1061 } 1062 1063 static inline void 1064 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) 1065 { 1066 dma->max_pq = maxpq; 1067 if (has_pq_continue) 1068 dma->max_pq |= DMA_HAS_PQ_CONTINUE; 1069 } 1070 1071 static inline bool dmaf_continue(enum dma_ctrl_flags flags) 1072 { 1073 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; 1074 } 1075 1076 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) 1077 { 1078 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; 1079 1080 return (flags & mask) == mask; 1081 } 1082 1083 static inline bool dma_dev_has_pq_continue(struct dma_device *dma) 1084 { 1085 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; 1086 } 1087 1088 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma) 1089 { 1090 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; 1091 } 1092 1093 /* dma_maxpq - reduce maxpq in the face of continued operations 1094 * @dma - dma device with PQ capability 1095 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set 1096 * 1097 * When an engine does not support native continuation we need 3 extra 1098 * source slots to reuse P and Q with the following coefficients: 1099 * 1/ {00} * P : remove P from Q', but use it as a source for P' 1100 * 2/ {01} * Q : use Q to continue Q' calculation 1101 * 3/ {00} * Q : subtract Q from P' to cancel (2) 1102 * 1103 * In the case where P is disabled we only need 1 extra source: 1104 * 1/ {01} * Q : use Q to continue Q' calculation 1105 */ 1106 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) 1107 { 1108 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) 1109 return dma_dev_to_maxpq(dma); 1110 else if (dmaf_p_disabled_continue(flags)) 1111 return dma_dev_to_maxpq(dma) - 1; 1112 else if (dmaf_continue(flags)) 1113 return dma_dev_to_maxpq(dma) - 3; 1114 BUG(); 1115 } 1116 1117 static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg, 1118 size_t dir_icg) 1119 { 1120 if (inc) { 1121 if (dir_icg) 1122 return dir_icg; 1123 else if (sgl) 1124 return icg; 1125 } 1126 1127 return 0; 1128 } 1129 1130 static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt, 1131 struct data_chunk *chunk) 1132 { 1133 return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl, 1134 chunk->icg, chunk->dst_icg); 1135 } 1136 1137 static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt, 1138 struct data_chunk *chunk) 1139 { 1140 return dmaengine_get_icg(xt->src_inc, xt->src_sgl, 1141 chunk->icg, chunk->src_icg); 1142 } 1143 1144 /* --- public DMA engine API --- */ 1145 1146 #ifdef CONFIG_DMA_ENGINE 1147 void dmaengine_get(void); 1148 void dmaengine_put(void); 1149 #else 1150 static inline void dmaengine_get(void) 1151 { 1152 } 1153 static inline void dmaengine_put(void) 1154 { 1155 } 1156 #endif 1157 1158 #ifdef CONFIG_ASYNC_TX_DMA 1159 #define async_dmaengine_get() dmaengine_get() 1160 #define async_dmaengine_put() dmaengine_put() 1161 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH 1162 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) 1163 #else 1164 #define async_dma_find_channel(type) dma_find_channel(type) 1165 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */ 1166 #else 1167 static inline void async_dmaengine_get(void) 1168 { 1169 } 1170 static inline void async_dmaengine_put(void) 1171 { 1172 } 1173 static inline struct dma_chan * 1174 async_dma_find_channel(enum dma_transaction_type type) 1175 { 1176 return NULL; 1177 } 1178 #endif /* CONFIG_ASYNC_TX_DMA */ 1179 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, 1180 struct dma_chan *chan); 1181 1182 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) 1183 { 1184 tx->flags |= DMA_CTRL_ACK; 1185 } 1186 1187 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) 1188 { 1189 tx->flags &= ~DMA_CTRL_ACK; 1190 } 1191 1192 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) 1193 { 1194 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; 1195 } 1196 1197 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) 1198 static inline void 1199 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) 1200 { 1201 set_bit(tx_type, dstp->bits); 1202 } 1203 1204 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) 1205 static inline void 1206 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) 1207 { 1208 clear_bit(tx_type, dstp->bits); 1209 } 1210 1211 #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) 1212 static inline void __dma_cap_zero(dma_cap_mask_t *dstp) 1213 { 1214 bitmap_zero(dstp->bits, DMA_TX_TYPE_END); 1215 } 1216 1217 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) 1218 static inline int 1219 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) 1220 { 1221 return test_bit(tx_type, srcp->bits); 1222 } 1223 1224 #define for_each_dma_cap_mask(cap, mask) \ 1225 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END) 1226 1227 /** 1228 * dma_async_issue_pending - flush pending transactions to HW 1229 * @chan: target DMA channel 1230 * 1231 * This allows drivers to push copies to HW in batches, 1232 * reducing MMIO writes where possible. 1233 */ 1234 static inline void dma_async_issue_pending(struct dma_chan *chan) 1235 { 1236 chan->device->device_issue_pending(chan); 1237 } 1238 1239 /** 1240 * dma_async_is_tx_complete - poll for transaction completion 1241 * @chan: DMA channel 1242 * @cookie: transaction identifier to check status of 1243 * @last: returns last completed cookie, can be NULL 1244 * @used: returns last issued cookie, can be NULL 1245 * 1246 * If @last and @used are passed in, upon return they reflect the driver 1247 * internal state and can be used with dma_async_is_complete() to check 1248 * the status of multiple cookies without re-checking hardware state. 1249 */ 1250 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, 1251 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) 1252 { 1253 struct dma_tx_state state; 1254 enum dma_status status; 1255 1256 status = chan->device->device_tx_status(chan, cookie, &state); 1257 if (last) 1258 *last = state.last; 1259 if (used) 1260 *used = state.used; 1261 return status; 1262 } 1263 1264 /** 1265 * dma_async_is_complete - test a cookie against chan state 1266 * @cookie: transaction identifier to test status of 1267 * @last_complete: last know completed transaction 1268 * @last_used: last cookie value handed out 1269 * 1270 * dma_async_is_complete() is used in dma_async_is_tx_complete() 1271 * the test logic is separated for lightweight testing of multiple cookies 1272 */ 1273 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, 1274 dma_cookie_t last_complete, dma_cookie_t last_used) 1275 { 1276 if (last_complete <= last_used) { 1277 if ((cookie <= last_complete) || (cookie > last_used)) 1278 return DMA_COMPLETE; 1279 } else { 1280 if ((cookie <= last_complete) && (cookie > last_used)) 1281 return DMA_COMPLETE; 1282 } 1283 return DMA_IN_PROGRESS; 1284 } 1285 1286 static inline void 1287 dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue) 1288 { 1289 if (st) { 1290 st->last = last; 1291 st->used = used; 1292 st->residue = residue; 1293 } 1294 } 1295 1296 #ifdef CONFIG_DMA_ENGINE 1297 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); 1298 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); 1299 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); 1300 void dma_issue_pending_all(void); 1301 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, 1302 dma_filter_fn fn, void *fn_param); 1303 struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name); 1304 1305 struct dma_chan *dma_request_chan(struct device *dev, const char *name); 1306 struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask); 1307 1308 void dma_release_channel(struct dma_chan *chan); 1309 int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps); 1310 #else 1311 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) 1312 { 1313 return NULL; 1314 } 1315 static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) 1316 { 1317 return DMA_COMPLETE; 1318 } 1319 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) 1320 { 1321 return DMA_COMPLETE; 1322 } 1323 static inline void dma_issue_pending_all(void) 1324 { 1325 } 1326 static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, 1327 dma_filter_fn fn, void *fn_param) 1328 { 1329 return NULL; 1330 } 1331 static inline struct dma_chan *dma_request_slave_channel(struct device *dev, 1332 const char *name) 1333 { 1334 return NULL; 1335 } 1336 static inline struct dma_chan *dma_request_chan(struct device *dev, 1337 const char *name) 1338 { 1339 return ERR_PTR(-ENODEV); 1340 } 1341 static inline struct dma_chan *dma_request_chan_by_mask( 1342 const dma_cap_mask_t *mask) 1343 { 1344 return ERR_PTR(-ENODEV); 1345 } 1346 static inline void dma_release_channel(struct dma_chan *chan) 1347 { 1348 } 1349 static inline int dma_get_slave_caps(struct dma_chan *chan, 1350 struct dma_slave_caps *caps) 1351 { 1352 return -ENXIO; 1353 } 1354 #endif 1355 1356 #define dma_request_slave_channel_reason(dev, name) dma_request_chan(dev, name) 1357 1358 static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx) 1359 { 1360 struct dma_slave_caps caps; 1361 1362 dma_get_slave_caps(tx->chan, &caps); 1363 1364 if (caps.descriptor_reuse) { 1365 tx->flags |= DMA_CTRL_REUSE; 1366 return 0; 1367 } else { 1368 return -EPERM; 1369 } 1370 } 1371 1372 static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx) 1373 { 1374 tx->flags &= ~DMA_CTRL_REUSE; 1375 } 1376 1377 static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx) 1378 { 1379 return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE; 1380 } 1381 1382 static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc) 1383 { 1384 /* this is supported for reusable desc, so check that */ 1385 if (dmaengine_desc_test_reuse(desc)) 1386 return desc->desc_free(desc); 1387 else 1388 return -EPERM; 1389 } 1390 1391 /* --- DMA device --- */ 1392 1393 int dma_async_device_register(struct dma_device *device); 1394 void dma_async_device_unregister(struct dma_device *device); 1395 void dma_run_dependencies(struct dma_async_tx_descriptor *tx); 1396 struct dma_chan *dma_get_slave_channel(struct dma_chan *chan); 1397 struct dma_chan *dma_get_any_slave_channel(struct dma_device *device); 1398 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) 1399 #define dma_request_slave_channel_compat(mask, x, y, dev, name) \ 1400 __dma_request_slave_channel_compat(&(mask), x, y, dev, name) 1401 1402 static inline struct dma_chan 1403 *__dma_request_slave_channel_compat(const dma_cap_mask_t *mask, 1404 dma_filter_fn fn, void *fn_param, 1405 struct device *dev, const char *name) 1406 { 1407 struct dma_chan *chan; 1408 1409 chan = dma_request_slave_channel(dev, name); 1410 if (chan) 1411 return chan; 1412 1413 if (!fn || !fn_param) 1414 return NULL; 1415 1416 return __dma_request_channel(mask, fn, fn_param); 1417 } 1418 #endif /* DMAENGINE_H */ 1419