1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. 4 */ 5 #ifndef LINUX_DMAENGINE_H 6 #define LINUX_DMAENGINE_H 7 8 #include <linux/device.h> 9 #include <linux/err.h> 10 #include <linux/uio.h> 11 #include <linux/bug.h> 12 #include <linux/scatterlist.h> 13 #include <linux/bitmap.h> 14 #include <linux/types.h> 15 #include <asm/page.h> 16 17 /** 18 * typedef dma_cookie_t - an opaque DMA cookie 19 * 20 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code 21 */ 22 typedef s32 dma_cookie_t; 23 #define DMA_MIN_COOKIE 1 24 25 static inline int dma_submit_error(dma_cookie_t cookie) 26 { 27 return cookie < 0 ? cookie : 0; 28 } 29 30 /** 31 * enum dma_status - DMA transaction status 32 * @DMA_COMPLETE: transaction completed 33 * @DMA_IN_PROGRESS: transaction not yet processed 34 * @DMA_PAUSED: transaction is paused 35 * @DMA_ERROR: transaction failed 36 */ 37 enum dma_status { 38 DMA_COMPLETE, 39 DMA_IN_PROGRESS, 40 DMA_PAUSED, 41 DMA_ERROR, 42 DMA_OUT_OF_ORDER, 43 }; 44 45 /** 46 * enum dma_transaction_type - DMA transaction types/indexes 47 * 48 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is 49 * automatically set as dma devices are registered. 50 */ 51 enum dma_transaction_type { 52 DMA_MEMCPY, 53 DMA_XOR, 54 DMA_PQ, 55 DMA_XOR_VAL, 56 DMA_PQ_VAL, 57 DMA_MEMSET, 58 DMA_MEMSET_SG, 59 DMA_INTERRUPT, 60 DMA_PRIVATE, 61 DMA_ASYNC_TX, 62 DMA_SLAVE, 63 DMA_CYCLIC, 64 DMA_INTERLEAVE, 65 DMA_COMPLETION_NO_ORDER, 66 /* last transaction type for creation of the capabilities mask */ 67 DMA_TX_TYPE_END, 68 }; 69 70 /** 71 * enum dma_transfer_direction - dma transfer mode and direction indicator 72 * @DMA_MEM_TO_MEM: Async/Memcpy mode 73 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device 74 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory 75 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device 76 */ 77 enum dma_transfer_direction { 78 DMA_MEM_TO_MEM, 79 DMA_MEM_TO_DEV, 80 DMA_DEV_TO_MEM, 81 DMA_DEV_TO_DEV, 82 DMA_TRANS_NONE, 83 }; 84 85 /** 86 * Interleaved Transfer Request 87 * ---------------------------- 88 * A chunk is collection of contiguous bytes to be transferred. 89 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG). 90 * ICGs may or may not change between chunks. 91 * A FRAME is the smallest series of contiguous {chunk,icg} pairs, 92 * that when repeated an integral number of times, specifies the transfer. 93 * A transfer template is specification of a Frame, the number of times 94 * it is to be repeated and other per-transfer attributes. 95 * 96 * Practically, a client driver would have ready a template for each 97 * type of transfer it is going to need during its lifetime and 98 * set only 'src_start' and 'dst_start' before submitting the requests. 99 * 100 * 101 * | Frame-1 | Frame-2 | ~ | Frame-'numf' | 102 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...| 103 * 104 * == Chunk size 105 * ... ICG 106 */ 107 108 /** 109 * struct data_chunk - Element of scatter-gather list that makes a frame. 110 * @size: Number of bytes to read from source. 111 * size_dst := fn(op, size_src), so doesn't mean much for destination. 112 * @icg: Number of bytes to jump after last src/dst address of this 113 * chunk and before first src/dst address for next chunk. 114 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false. 115 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false. 116 * @dst_icg: Number of bytes to jump after last dst address of this 117 * chunk and before the first dst address for next chunk. 118 * Ignored if dst_inc is true and dst_sgl is false. 119 * @src_icg: Number of bytes to jump after last src address of this 120 * chunk and before the first src address for next chunk. 121 * Ignored if src_inc is true and src_sgl is false. 122 */ 123 struct data_chunk { 124 size_t size; 125 size_t icg; 126 size_t dst_icg; 127 size_t src_icg; 128 }; 129 130 /** 131 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern 132 * and attributes. 133 * @src_start: Bus address of source for the first chunk. 134 * @dst_start: Bus address of destination for the first chunk. 135 * @dir: Specifies the type of Source and Destination. 136 * @src_inc: If the source address increments after reading from it. 137 * @dst_inc: If the destination address increments after writing to it. 138 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read). 139 * Otherwise, source is read contiguously (icg ignored). 140 * Ignored if src_inc is false. 141 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write). 142 * Otherwise, destination is filled contiguously (icg ignored). 143 * Ignored if dst_inc is false. 144 * @numf: Number of frames in this template. 145 * @frame_size: Number of chunks in a frame i.e, size of sgl[]. 146 * @sgl: Array of {chunk,icg} pairs that make up a frame. 147 */ 148 struct dma_interleaved_template { 149 dma_addr_t src_start; 150 dma_addr_t dst_start; 151 enum dma_transfer_direction dir; 152 bool src_inc; 153 bool dst_inc; 154 bool src_sgl; 155 bool dst_sgl; 156 size_t numf; 157 size_t frame_size; 158 struct data_chunk sgl[0]; 159 }; 160 161 /** 162 * enum dma_ctrl_flags - DMA flags to augment operation preparation, 163 * control completion, and communicate status. 164 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of 165 * this transaction 166 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client 167 * acknowledges receipt, i.e. has a chance to establish any dependency 168 * chains 169 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q 170 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P 171 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as 172 * sources that were the result of a previous operation, in the case of a PQ 173 * operation it continues the calculation with new sources 174 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend 175 * on the result of this operation 176 * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till 177 * cleared or freed 178 * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command 179 * data and the descriptor should be in different format from normal 180 * data descriptors. 181 */ 182 enum dma_ctrl_flags { 183 DMA_PREP_INTERRUPT = (1 << 0), 184 DMA_CTRL_ACK = (1 << 1), 185 DMA_PREP_PQ_DISABLE_P = (1 << 2), 186 DMA_PREP_PQ_DISABLE_Q = (1 << 3), 187 DMA_PREP_CONTINUE = (1 << 4), 188 DMA_PREP_FENCE = (1 << 5), 189 DMA_CTRL_REUSE = (1 << 6), 190 DMA_PREP_CMD = (1 << 7), 191 }; 192 193 /** 194 * enum sum_check_bits - bit position of pq_check_flags 195 */ 196 enum sum_check_bits { 197 SUM_CHECK_P = 0, 198 SUM_CHECK_Q = 1, 199 }; 200 201 /** 202 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations 203 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise 204 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise 205 */ 206 enum sum_check_flags { 207 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P), 208 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q), 209 }; 210 211 212 /** 213 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. 214 * See linux/cpumask.h 215 */ 216 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; 217 218 /** 219 * struct dma_chan_percpu - the per-CPU part of struct dma_chan 220 * @memcpy_count: transaction counter 221 * @bytes_transferred: byte counter 222 */ 223 224 /** 225 * enum dma_desc_metadata_mode - per descriptor metadata mode types supported 226 * @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the 227 * client driver and it is attached (via the dmaengine_desc_attach_metadata() 228 * helper) to the descriptor. 229 * 230 * Client drivers interested to use this mode can follow: 231 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM: 232 * 1. prepare the descriptor (dmaengine_prep_*) 233 * construct the metadata in the client's buffer 234 * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the 235 * descriptor 236 * 3. submit the transfer 237 * - DMA_DEV_TO_MEM: 238 * 1. prepare the descriptor (dmaengine_prep_*) 239 * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the 240 * descriptor 241 * 3. submit the transfer 242 * 4. when the transfer is completed, the metadata should be available in the 243 * attached buffer 244 * 245 * @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA 246 * driver. The client driver can ask for the pointer, maximum size and the 247 * currently used size of the metadata and can directly update or read it. 248 * dmaengine_desc_get_metadata_ptr() and dmaengine_desc_set_metadata_len() is 249 * provided as helper functions. 250 * 251 * Note: the metadata area for the descriptor is no longer valid after the 252 * transfer has been completed (valid up to the point when the completion 253 * callback returns if used). 254 * 255 * Client drivers interested to use this mode can follow: 256 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM: 257 * 1. prepare the descriptor (dmaengine_prep_*) 258 * 2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the engine's 259 * metadata area 260 * 3. update the metadata at the pointer 261 * 4. use dmaengine_desc_set_metadata_len() to tell the DMA engine the amount 262 * of data the client has placed into the metadata buffer 263 * 5. submit the transfer 264 * - DMA_DEV_TO_MEM: 265 * 1. prepare the descriptor (dmaengine_prep_*) 266 * 2. submit the transfer 267 * 3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get the 268 * pointer to the engine's metadata area 269 * 4. Read out the metadata from the pointer 270 * 271 * Note: the two mode is not compatible and clients must use one mode for a 272 * descriptor. 273 */ 274 enum dma_desc_metadata_mode { 275 DESC_METADATA_NONE = 0, 276 DESC_METADATA_CLIENT = BIT(0), 277 DESC_METADATA_ENGINE = BIT(1), 278 }; 279 280 struct dma_chan_percpu { 281 /* stats */ 282 unsigned long memcpy_count; 283 unsigned long bytes_transferred; 284 }; 285 286 /** 287 * struct dma_router - DMA router structure 288 * @dev: pointer to the DMA router device 289 * @route_free: function to be called when the route can be disconnected 290 */ 291 struct dma_router { 292 struct device *dev; 293 void (*route_free)(struct device *dev, void *route_data); 294 }; 295 296 /** 297 * struct dma_chan - devices supply DMA channels, clients use them 298 * @device: ptr to the dma device who supplies this channel, always !%NULL 299 * @slave: ptr to the device using this channel 300 * @cookie: last cookie value returned to client 301 * @completed_cookie: last completed cookie for this channel 302 * @chan_id: channel ID for sysfs 303 * @dev: class device for sysfs 304 * @name: backlink name for sysfs 305 * @dbg_client_name: slave name for debugfs in format: 306 * dev_name(requester's dev):channel name, for example: "2b00000.mcasp:tx" 307 * @device_node: used to add this to the device chan list 308 * @local: per-cpu pointer to a struct dma_chan_percpu 309 * @client_count: how many clients are using this channel 310 * @table_count: number of appearances in the mem-to-mem allocation table 311 * @router: pointer to the DMA router structure 312 * @route_data: channel specific data for the router 313 * @private: private data for certain client-channel associations 314 */ 315 struct dma_chan { 316 struct dma_device *device; 317 struct device *slave; 318 dma_cookie_t cookie; 319 dma_cookie_t completed_cookie; 320 321 /* sysfs */ 322 int chan_id; 323 struct dma_chan_dev *dev; 324 const char *name; 325 #ifdef CONFIG_DEBUG_FS 326 char *dbg_client_name; 327 #endif 328 329 struct list_head device_node; 330 struct dma_chan_percpu __percpu *local; 331 int client_count; 332 int table_count; 333 334 /* DMA router */ 335 struct dma_router *router; 336 void *route_data; 337 338 void *private; 339 }; 340 341 /** 342 * struct dma_chan_dev - relate sysfs device node to backing channel device 343 * @chan: driver channel device 344 * @device: sysfs device 345 * @dev_id: parent dma_device dev_id 346 */ 347 struct dma_chan_dev { 348 struct dma_chan *chan; 349 struct device device; 350 int dev_id; 351 }; 352 353 /** 354 * enum dma_slave_buswidth - defines bus width of the DMA slave 355 * device, source or target buses 356 */ 357 enum dma_slave_buswidth { 358 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, 359 DMA_SLAVE_BUSWIDTH_1_BYTE = 1, 360 DMA_SLAVE_BUSWIDTH_2_BYTES = 2, 361 DMA_SLAVE_BUSWIDTH_3_BYTES = 3, 362 DMA_SLAVE_BUSWIDTH_4_BYTES = 4, 363 DMA_SLAVE_BUSWIDTH_8_BYTES = 8, 364 DMA_SLAVE_BUSWIDTH_16_BYTES = 16, 365 DMA_SLAVE_BUSWIDTH_32_BYTES = 32, 366 DMA_SLAVE_BUSWIDTH_64_BYTES = 64, 367 }; 368 369 /** 370 * struct dma_slave_config - dma slave channel runtime config 371 * @direction: whether the data shall go in or out on this slave 372 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are 373 * legal values. DEPRECATED, drivers should use the direction argument 374 * to the device_prep_slave_sg and device_prep_dma_cyclic functions or 375 * the dir field in the dma_interleaved_template structure. 376 * @src_addr: this is the physical address where DMA slave data 377 * should be read (RX), if the source is memory this argument is 378 * ignored. 379 * @dst_addr: this is the physical address where DMA slave data 380 * should be written (TX), if the source is memory this argument 381 * is ignored. 382 * @src_addr_width: this is the width in bytes of the source (RX) 383 * register where DMA data shall be read. If the source 384 * is memory this may be ignored depending on architecture. 385 * Legal values: 1, 2, 3, 4, 8, 16, 32, 64. 386 * @dst_addr_width: same as src_addr_width but for destination 387 * target (TX) mutatis mutandis. 388 * @src_maxburst: the maximum number of words (note: words, as in 389 * units of the src_addr_width member, not bytes) that can be sent 390 * in one burst to the device. Typically something like half the 391 * FIFO depth on I/O peripherals so you don't overflow it. This 392 * may or may not be applicable on memory sources. 393 * @dst_maxburst: same as src_maxburst but for destination target 394 * mutatis mutandis. 395 * @src_port_window_size: The length of the register area in words the data need 396 * to be accessed on the device side. It is only used for devices which is using 397 * an area instead of a single register to receive the data. Typically the DMA 398 * loops in this area in order to transfer the data. 399 * @dst_port_window_size: same as src_port_window_size but for the destination 400 * port. 401 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill 402 * with 'true' if peripheral should be flow controller. Direction will be 403 * selected at Runtime. 404 * @slave_id: Slave requester id. Only valid for slave channels. The dma 405 * slave peripheral will have unique id as dma requester which need to be 406 * pass as slave config. 407 * 408 * This struct is passed in as configuration data to a DMA engine 409 * in order to set up a certain channel for DMA transport at runtime. 410 * The DMA device/engine has to provide support for an additional 411 * callback in the dma_device structure, device_config and this struct 412 * will then be passed in as an argument to the function. 413 * 414 * The rationale for adding configuration information to this struct is as 415 * follows: if it is likely that more than one DMA slave controllers in 416 * the world will support the configuration option, then make it generic. 417 * If not: if it is fixed so that it be sent in static from the platform 418 * data, then prefer to do that. 419 */ 420 struct dma_slave_config { 421 enum dma_transfer_direction direction; 422 phys_addr_t src_addr; 423 phys_addr_t dst_addr; 424 enum dma_slave_buswidth src_addr_width; 425 enum dma_slave_buswidth dst_addr_width; 426 u32 src_maxburst; 427 u32 dst_maxburst; 428 u32 src_port_window_size; 429 u32 dst_port_window_size; 430 bool device_fc; 431 unsigned int slave_id; 432 }; 433 434 /** 435 * enum dma_residue_granularity - Granularity of the reported transfer residue 436 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The 437 * DMA channel is only able to tell whether a descriptor has been completed or 438 * not, which means residue reporting is not supported by this channel. The 439 * residue field of the dma_tx_state field will always be 0. 440 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully 441 * completed segment of the transfer (For cyclic transfers this is after each 442 * period). This is typically implemented by having the hardware generate an 443 * interrupt after each transferred segment and then the drivers updates the 444 * outstanding residue by the size of the segment. Another possibility is if 445 * the hardware supports scatter-gather and the segment descriptor has a field 446 * which gets set after the segment has been completed. The driver then counts 447 * the number of segments without the flag set to compute the residue. 448 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred 449 * burst. This is typically only supported if the hardware has a progress 450 * register of some sort (E.g. a register with the current read/write address 451 * or a register with the amount of bursts/beats/bytes that have been 452 * transferred or still need to be transferred). 453 */ 454 enum dma_residue_granularity { 455 DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0, 456 DMA_RESIDUE_GRANULARITY_SEGMENT = 1, 457 DMA_RESIDUE_GRANULARITY_BURST = 2, 458 }; 459 460 /** 461 * struct dma_slave_caps - expose capabilities of a slave channel only 462 * @src_addr_widths: bit mask of src addr widths the channel supports. 463 * Width is specified in bytes, e.g. for a channel supporting 464 * a width of 4 the mask should have BIT(4) set. 465 * @dst_addr_widths: bit mask of dst addr widths the channel supports 466 * @directions: bit mask of slave directions the channel supports. 467 * Since the enum dma_transfer_direction is not defined as bit flag for 468 * each type, the dma controller should set BIT(<TYPE>) and same 469 * should be checked by controller as well 470 * @min_burst: min burst capability per-transfer 471 * @max_burst: max burst capability per-transfer 472 * @max_sg_burst: max number of SG list entries executed in a single burst 473 * DMA tansaction with no software intervention for reinitialization. 474 * Zero value means unlimited number of entries. 475 * @cmd_pause: true, if pause is supported (i.e. for reading residue or 476 * for resume later) 477 * @cmd_resume: true, if resume is supported 478 * @cmd_terminate: true, if terminate cmd is supported 479 * @residue_granularity: granularity of the reported transfer residue 480 * @descriptor_reuse: if a descriptor can be reused by client and 481 * resubmitted multiple times 482 */ 483 struct dma_slave_caps { 484 u32 src_addr_widths; 485 u32 dst_addr_widths; 486 u32 directions; 487 u32 min_burst; 488 u32 max_burst; 489 u32 max_sg_burst; 490 bool cmd_pause; 491 bool cmd_resume; 492 bool cmd_terminate; 493 enum dma_residue_granularity residue_granularity; 494 bool descriptor_reuse; 495 }; 496 497 static inline const char *dma_chan_name(struct dma_chan *chan) 498 { 499 return dev_name(&chan->dev->device); 500 } 501 502 void dma_chan_cleanup(struct kref *kref); 503 504 /** 505 * typedef dma_filter_fn - callback filter for dma_request_channel 506 * @chan: channel to be reviewed 507 * @filter_param: opaque parameter passed through dma_request_channel 508 * 509 * When this optional parameter is specified in a call to dma_request_channel a 510 * suitable channel is passed to this routine for further dispositioning before 511 * being returned. Where 'suitable' indicates a non-busy channel that 512 * satisfies the given capability mask. It returns 'true' to indicate that the 513 * channel is suitable. 514 */ 515 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); 516 517 typedef void (*dma_async_tx_callback)(void *dma_async_param); 518 519 enum dmaengine_tx_result { 520 DMA_TRANS_NOERROR = 0, /* SUCCESS */ 521 DMA_TRANS_READ_FAILED, /* Source DMA read failed */ 522 DMA_TRANS_WRITE_FAILED, /* Destination DMA write failed */ 523 DMA_TRANS_ABORTED, /* Op never submitted / aborted */ 524 }; 525 526 struct dmaengine_result { 527 enum dmaengine_tx_result result; 528 u32 residue; 529 }; 530 531 typedef void (*dma_async_tx_callback_result)(void *dma_async_param, 532 const struct dmaengine_result *result); 533 534 struct dmaengine_unmap_data { 535 #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID) 536 u16 map_cnt; 537 #else 538 u8 map_cnt; 539 #endif 540 u8 to_cnt; 541 u8 from_cnt; 542 u8 bidi_cnt; 543 struct device *dev; 544 struct kref kref; 545 size_t len; 546 dma_addr_t addr[0]; 547 }; 548 549 struct dma_async_tx_descriptor; 550 551 struct dma_descriptor_metadata_ops { 552 int (*attach)(struct dma_async_tx_descriptor *desc, void *data, 553 size_t len); 554 555 void *(*get_ptr)(struct dma_async_tx_descriptor *desc, 556 size_t *payload_len, size_t *max_len); 557 int (*set_len)(struct dma_async_tx_descriptor *desc, 558 size_t payload_len); 559 }; 560 561 /** 562 * struct dma_async_tx_descriptor - async transaction descriptor 563 * ---dma generic offload fields--- 564 * @cookie: tracking cookie for this transaction, set to -EBUSY if 565 * this tx is sitting on a dependency list 566 * @flags: flags to augment operation preparation, control completion, and 567 * communicate status 568 * @phys: physical address of the descriptor 569 * @chan: target channel for this operation 570 * @tx_submit: accept the descriptor, assign ordered cookie and mark the 571 * descriptor pending. To be pushed on .issue_pending() call 572 * @callback: routine to call after this operation is complete 573 * @callback_param: general parameter to pass to the callback routine 574 * @desc_metadata_mode: core managed metadata mode to protect mixed use of 575 * DESC_METADATA_CLIENT or DESC_METADATA_ENGINE. Otherwise 576 * DESC_METADATA_NONE 577 * @metadata_ops: DMA driver provided metadata mode ops, need to be set by the 578 * DMA driver if metadata mode is supported with the descriptor 579 * ---async_tx api specific fields--- 580 * @next: at completion submit this descriptor 581 * @parent: pointer to the next level up in the dependency chain 582 * @lock: protect the parent and next pointers 583 */ 584 struct dma_async_tx_descriptor { 585 dma_cookie_t cookie; 586 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ 587 dma_addr_t phys; 588 struct dma_chan *chan; 589 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); 590 int (*desc_free)(struct dma_async_tx_descriptor *tx); 591 dma_async_tx_callback callback; 592 dma_async_tx_callback_result callback_result; 593 void *callback_param; 594 struct dmaengine_unmap_data *unmap; 595 enum dma_desc_metadata_mode desc_metadata_mode; 596 struct dma_descriptor_metadata_ops *metadata_ops; 597 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH 598 struct dma_async_tx_descriptor *next; 599 struct dma_async_tx_descriptor *parent; 600 spinlock_t lock; 601 #endif 602 }; 603 604 #ifdef CONFIG_DMA_ENGINE 605 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, 606 struct dmaengine_unmap_data *unmap) 607 { 608 kref_get(&unmap->kref); 609 tx->unmap = unmap; 610 } 611 612 struct dmaengine_unmap_data * 613 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags); 614 void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap); 615 #else 616 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, 617 struct dmaengine_unmap_data *unmap) 618 { 619 } 620 static inline struct dmaengine_unmap_data * 621 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags) 622 { 623 return NULL; 624 } 625 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap) 626 { 627 } 628 #endif 629 630 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx) 631 { 632 if (!tx->unmap) 633 return; 634 635 dmaengine_unmap_put(tx->unmap); 636 tx->unmap = NULL; 637 } 638 639 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH 640 static inline void txd_lock(struct dma_async_tx_descriptor *txd) 641 { 642 } 643 static inline void txd_unlock(struct dma_async_tx_descriptor *txd) 644 { 645 } 646 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) 647 { 648 BUG(); 649 } 650 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) 651 { 652 } 653 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) 654 { 655 } 656 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) 657 { 658 return NULL; 659 } 660 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) 661 { 662 return NULL; 663 } 664 665 #else 666 static inline void txd_lock(struct dma_async_tx_descriptor *txd) 667 { 668 spin_lock_bh(&txd->lock); 669 } 670 static inline void txd_unlock(struct dma_async_tx_descriptor *txd) 671 { 672 spin_unlock_bh(&txd->lock); 673 } 674 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) 675 { 676 txd->next = next; 677 next->parent = txd; 678 } 679 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) 680 { 681 txd->parent = NULL; 682 } 683 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) 684 { 685 txd->next = NULL; 686 } 687 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) 688 { 689 return txd->parent; 690 } 691 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) 692 { 693 return txd->next; 694 } 695 #endif 696 697 /** 698 * struct dma_tx_state - filled in to report the status of 699 * a transfer. 700 * @last: last completed DMA cookie 701 * @used: last issued DMA cookie (i.e. the one in progress) 702 * @residue: the remaining number of bytes left to transmit 703 * on the selected transfer for states DMA_IN_PROGRESS and 704 * DMA_PAUSED if this is implemented in the driver, else 0 705 * @in_flight_bytes: amount of data in bytes cached by the DMA. 706 */ 707 struct dma_tx_state { 708 dma_cookie_t last; 709 dma_cookie_t used; 710 u32 residue; 711 u32 in_flight_bytes; 712 }; 713 714 /** 715 * enum dmaengine_alignment - defines alignment of the DMA async tx 716 * buffers 717 */ 718 enum dmaengine_alignment { 719 DMAENGINE_ALIGN_1_BYTE = 0, 720 DMAENGINE_ALIGN_2_BYTES = 1, 721 DMAENGINE_ALIGN_4_BYTES = 2, 722 DMAENGINE_ALIGN_8_BYTES = 3, 723 DMAENGINE_ALIGN_16_BYTES = 4, 724 DMAENGINE_ALIGN_32_BYTES = 5, 725 DMAENGINE_ALIGN_64_BYTES = 6, 726 }; 727 728 /** 729 * struct dma_slave_map - associates slave device and it's slave channel with 730 * parameter to be used by a filter function 731 * @devname: name of the device 732 * @slave: slave channel name 733 * @param: opaque parameter to pass to struct dma_filter.fn 734 */ 735 struct dma_slave_map { 736 const char *devname; 737 const char *slave; 738 void *param; 739 }; 740 741 /** 742 * struct dma_filter - information for slave device/channel to filter_fn/param 743 * mapping 744 * @fn: filter function callback 745 * @mapcnt: number of slave device/channel in the map 746 * @map: array of channel to filter mapping data 747 */ 748 struct dma_filter { 749 dma_filter_fn fn; 750 int mapcnt; 751 const struct dma_slave_map *map; 752 }; 753 754 /** 755 * struct dma_device - info on the entity supplying DMA services 756 * @chancnt: how many DMA channels are supported 757 * @privatecnt: how many DMA channels are requested by dma_request_channel 758 * @channels: the list of struct dma_chan 759 * @global_node: list_head for global dma_device_list 760 * @filter: information for device/slave to filter function/param mapping 761 * @cap_mask: one or more dma_capability flags 762 * @desc_metadata_modes: supported metadata modes by the DMA device 763 * @max_xor: maximum number of xor sources, 0 if no capability 764 * @max_pq: maximum number of PQ sources and PQ-continue capability 765 * @copy_align: alignment shift for memcpy operations 766 * @xor_align: alignment shift for xor operations 767 * @pq_align: alignment shift for pq operations 768 * @fill_align: alignment shift for memset operations 769 * @dev_id: unique device ID 770 * @dev: struct device reference for dma mapping api 771 * @owner: owner module (automatically set based on the provided dev) 772 * @src_addr_widths: bit mask of src addr widths the device supports 773 * Width is specified in bytes, e.g. for a device supporting 774 * a width of 4 the mask should have BIT(4) set. 775 * @dst_addr_widths: bit mask of dst addr widths the device supports 776 * @directions: bit mask of slave directions the device supports. 777 * Since the enum dma_transfer_direction is not defined as bit flag for 778 * each type, the dma controller should set BIT(<TYPE>) and same 779 * should be checked by controller as well 780 * @min_burst: min burst capability per-transfer 781 * @max_burst: max burst capability per-transfer 782 * @max_sg_burst: max number of SG list entries executed in a single burst 783 * DMA tansaction with no software intervention for reinitialization. 784 * Zero value means unlimited number of entries. 785 * @residue_granularity: granularity of the transfer residue reported 786 * by tx_status 787 * @device_alloc_chan_resources: allocate resources and return the 788 * number of allocated descriptors 789 * @device_free_chan_resources: release DMA channel's resources 790 * @device_prep_dma_memcpy: prepares a memcpy operation 791 * @device_prep_dma_xor: prepares a xor operation 792 * @device_prep_dma_xor_val: prepares a xor validation operation 793 * @device_prep_dma_pq: prepares a pq operation 794 * @device_prep_dma_pq_val: prepares a pqzero_sum operation 795 * @device_prep_dma_memset: prepares a memset operation 796 * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list 797 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation 798 * @device_prep_slave_sg: prepares a slave dma operation 799 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio. 800 * The function takes a buffer of size buf_len. The callback function will 801 * be called after period_len bytes have been transferred. 802 * @device_prep_interleaved_dma: Transfer expression in a generic way. 803 * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address 804 * @device_caps: May be used to override the generic DMA slave capabilities 805 * with per-channel specific ones 806 * @device_config: Pushes a new configuration to a channel, return 0 or an error 807 * code 808 * @device_pause: Pauses any transfer happening on a channel. Returns 809 * 0 or an error code 810 * @device_resume: Resumes any transfer on a channel previously 811 * paused. Returns 0 or an error code 812 * @device_terminate_all: Aborts all transfers on a channel. Returns 0 813 * or an error code 814 * @device_synchronize: Synchronizes the termination of a transfers to the 815 * current context. 816 * @device_tx_status: poll for transaction completion, the optional 817 * txstate parameter can be supplied with a pointer to get a 818 * struct with auxiliary transfer status information, otherwise the call 819 * will just return a simple status code 820 * @device_issue_pending: push pending transactions to hardware 821 * @descriptor_reuse: a submitted transfer can be resubmitted after completion 822 * @device_release: called sometime atfer dma_async_device_unregister() is 823 * called and there are no further references to this structure. This 824 * must be implemented to free resources however many existing drivers 825 * do not and are therefore not safe to unbind while in use. 826 * @dbg_summary_show: optional routine to show contents in debugfs; default code 827 * will be used when this is omitted, but custom code can show extra, 828 * controller specific information. 829 */ 830 struct dma_device { 831 struct kref ref; 832 unsigned int chancnt; 833 unsigned int privatecnt; 834 struct list_head channels; 835 struct list_head global_node; 836 struct dma_filter filter; 837 dma_cap_mask_t cap_mask; 838 enum dma_desc_metadata_mode desc_metadata_modes; 839 unsigned short max_xor; 840 unsigned short max_pq; 841 enum dmaengine_alignment copy_align; 842 enum dmaengine_alignment xor_align; 843 enum dmaengine_alignment pq_align; 844 enum dmaengine_alignment fill_align; 845 #define DMA_HAS_PQ_CONTINUE (1 << 15) 846 847 int dev_id; 848 struct device *dev; 849 struct module *owner; 850 struct ida chan_ida; 851 struct mutex chan_mutex; /* to protect chan_ida */ 852 853 u32 src_addr_widths; 854 u32 dst_addr_widths; 855 u32 directions; 856 u32 min_burst; 857 u32 max_burst; 858 u32 max_sg_burst; 859 bool descriptor_reuse; 860 enum dma_residue_granularity residue_granularity; 861 862 int (*device_alloc_chan_resources)(struct dma_chan *chan); 863 void (*device_free_chan_resources)(struct dma_chan *chan); 864 865 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( 866 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, 867 size_t len, unsigned long flags); 868 struct dma_async_tx_descriptor *(*device_prep_dma_xor)( 869 struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, 870 unsigned int src_cnt, size_t len, unsigned long flags); 871 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( 872 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, 873 size_t len, enum sum_check_flags *result, unsigned long flags); 874 struct dma_async_tx_descriptor *(*device_prep_dma_pq)( 875 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, 876 unsigned int src_cnt, const unsigned char *scf, 877 size_t len, unsigned long flags); 878 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)( 879 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, 880 unsigned int src_cnt, const unsigned char *scf, size_t len, 881 enum sum_check_flags *pqres, unsigned long flags); 882 struct dma_async_tx_descriptor *(*device_prep_dma_memset)( 883 struct dma_chan *chan, dma_addr_t dest, int value, size_t len, 884 unsigned long flags); 885 struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)( 886 struct dma_chan *chan, struct scatterlist *sg, 887 unsigned int nents, int value, unsigned long flags); 888 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( 889 struct dma_chan *chan, unsigned long flags); 890 891 struct dma_async_tx_descriptor *(*device_prep_slave_sg)( 892 struct dma_chan *chan, struct scatterlist *sgl, 893 unsigned int sg_len, enum dma_transfer_direction direction, 894 unsigned long flags, void *context); 895 struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)( 896 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 897 size_t period_len, enum dma_transfer_direction direction, 898 unsigned long flags); 899 struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( 900 struct dma_chan *chan, struct dma_interleaved_template *xt, 901 unsigned long flags); 902 struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)( 903 struct dma_chan *chan, dma_addr_t dst, u64 data, 904 unsigned long flags); 905 906 void (*device_caps)(struct dma_chan *chan, 907 struct dma_slave_caps *caps); 908 int (*device_config)(struct dma_chan *chan, 909 struct dma_slave_config *config); 910 int (*device_pause)(struct dma_chan *chan); 911 int (*device_resume)(struct dma_chan *chan); 912 int (*device_terminate_all)(struct dma_chan *chan); 913 void (*device_synchronize)(struct dma_chan *chan); 914 915 enum dma_status (*device_tx_status)(struct dma_chan *chan, 916 dma_cookie_t cookie, 917 struct dma_tx_state *txstate); 918 void (*device_issue_pending)(struct dma_chan *chan); 919 void (*device_release)(struct dma_device *dev); 920 /* debugfs support */ 921 #ifdef CONFIG_DEBUG_FS 922 void (*dbg_summary_show)(struct seq_file *s, struct dma_device *dev); 923 struct dentry *dbg_dev_root; 924 #endif 925 }; 926 927 static inline int dmaengine_slave_config(struct dma_chan *chan, 928 struct dma_slave_config *config) 929 { 930 if (chan->device->device_config) 931 return chan->device->device_config(chan, config); 932 933 return -ENOSYS; 934 } 935 936 static inline bool is_slave_direction(enum dma_transfer_direction direction) 937 { 938 return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM); 939 } 940 941 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single( 942 struct dma_chan *chan, dma_addr_t buf, size_t len, 943 enum dma_transfer_direction dir, unsigned long flags) 944 { 945 struct scatterlist sg; 946 sg_init_table(&sg, 1); 947 sg_dma_address(&sg) = buf; 948 sg_dma_len(&sg) = len; 949 950 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) 951 return NULL; 952 953 return chan->device->device_prep_slave_sg(chan, &sg, 1, 954 dir, flags, NULL); 955 } 956 957 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg( 958 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, 959 enum dma_transfer_direction dir, unsigned long flags) 960 { 961 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) 962 return NULL; 963 964 return chan->device->device_prep_slave_sg(chan, sgl, sg_len, 965 dir, flags, NULL); 966 } 967 968 #ifdef CONFIG_RAPIDIO_DMA_ENGINE 969 struct rio_dma_ext; 970 static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg( 971 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, 972 enum dma_transfer_direction dir, unsigned long flags, 973 struct rio_dma_ext *rio_ext) 974 { 975 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) 976 return NULL; 977 978 return chan->device->device_prep_slave_sg(chan, sgl, sg_len, 979 dir, flags, rio_ext); 980 } 981 #endif 982 983 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic( 984 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 985 size_t period_len, enum dma_transfer_direction dir, 986 unsigned long flags) 987 { 988 if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic) 989 return NULL; 990 991 return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len, 992 period_len, dir, flags); 993 } 994 995 static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma( 996 struct dma_chan *chan, struct dma_interleaved_template *xt, 997 unsigned long flags) 998 { 999 if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma) 1000 return NULL; 1001 1002 return chan->device->device_prep_interleaved_dma(chan, xt, flags); 1003 } 1004 1005 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset( 1006 struct dma_chan *chan, dma_addr_t dest, int value, size_t len, 1007 unsigned long flags) 1008 { 1009 if (!chan || !chan->device || !chan->device->device_prep_dma_memset) 1010 return NULL; 1011 1012 return chan->device->device_prep_dma_memset(chan, dest, value, 1013 len, flags); 1014 } 1015 1016 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy( 1017 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 1018 size_t len, unsigned long flags) 1019 { 1020 if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy) 1021 return NULL; 1022 1023 return chan->device->device_prep_dma_memcpy(chan, dest, src, 1024 len, flags); 1025 } 1026 1027 static inline bool dmaengine_is_metadata_mode_supported(struct dma_chan *chan, 1028 enum dma_desc_metadata_mode mode) 1029 { 1030 if (!chan) 1031 return false; 1032 1033 return !!(chan->device->desc_metadata_modes & mode); 1034 } 1035 1036 #ifdef CONFIG_DMA_ENGINE 1037 int dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc, 1038 void *data, size_t len); 1039 void *dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc, 1040 size_t *payload_len, size_t *max_len); 1041 int dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc, 1042 size_t payload_len); 1043 #else /* CONFIG_DMA_ENGINE */ 1044 static inline int dmaengine_desc_attach_metadata( 1045 struct dma_async_tx_descriptor *desc, void *data, size_t len) 1046 { 1047 return -EINVAL; 1048 } 1049 static inline void *dmaengine_desc_get_metadata_ptr( 1050 struct dma_async_tx_descriptor *desc, size_t *payload_len, 1051 size_t *max_len) 1052 { 1053 return NULL; 1054 } 1055 static inline int dmaengine_desc_set_metadata_len( 1056 struct dma_async_tx_descriptor *desc, size_t payload_len) 1057 { 1058 return -EINVAL; 1059 } 1060 #endif /* CONFIG_DMA_ENGINE */ 1061 1062 /** 1063 * dmaengine_terminate_all() - Terminate all active DMA transfers 1064 * @chan: The channel for which to terminate the transfers 1065 * 1066 * This function is DEPRECATED use either dmaengine_terminate_sync() or 1067 * dmaengine_terminate_async() instead. 1068 */ 1069 static inline int dmaengine_terminate_all(struct dma_chan *chan) 1070 { 1071 if (chan->device->device_terminate_all) 1072 return chan->device->device_terminate_all(chan); 1073 1074 return -ENOSYS; 1075 } 1076 1077 /** 1078 * dmaengine_terminate_async() - Terminate all active DMA transfers 1079 * @chan: The channel for which to terminate the transfers 1080 * 1081 * Calling this function will terminate all active and pending descriptors 1082 * that have previously been submitted to the channel. It is not guaranteed 1083 * though that the transfer for the active descriptor has stopped when the 1084 * function returns. Furthermore it is possible the complete callback of a 1085 * submitted transfer is still running when this function returns. 1086 * 1087 * dmaengine_synchronize() needs to be called before it is safe to free 1088 * any memory that is accessed by previously submitted descriptors or before 1089 * freeing any resources accessed from within the completion callback of any 1090 * previously submitted descriptors. 1091 * 1092 * This function can be called from atomic context as well as from within a 1093 * complete callback of a descriptor submitted on the same channel. 1094 * 1095 * If none of the two conditions above apply consider using 1096 * dmaengine_terminate_sync() instead. 1097 */ 1098 static inline int dmaengine_terminate_async(struct dma_chan *chan) 1099 { 1100 if (chan->device->device_terminate_all) 1101 return chan->device->device_terminate_all(chan); 1102 1103 return -EINVAL; 1104 } 1105 1106 /** 1107 * dmaengine_synchronize() - Synchronize DMA channel termination 1108 * @chan: The channel to synchronize 1109 * 1110 * Synchronizes to the DMA channel termination to the current context. When this 1111 * function returns it is guaranteed that all transfers for previously issued 1112 * descriptors have stopped and it is safe to free the memory associated 1113 * with them. Furthermore it is guaranteed that all complete callback functions 1114 * for a previously submitted descriptor have finished running and it is safe to 1115 * free resources accessed from within the complete callbacks. 1116 * 1117 * The behavior of this function is undefined if dma_async_issue_pending() has 1118 * been called between dmaengine_terminate_async() and this function. 1119 * 1120 * This function must only be called from non-atomic context and must not be 1121 * called from within a complete callback of a descriptor submitted on the same 1122 * channel. 1123 */ 1124 static inline void dmaengine_synchronize(struct dma_chan *chan) 1125 { 1126 might_sleep(); 1127 1128 if (chan->device->device_synchronize) 1129 chan->device->device_synchronize(chan); 1130 } 1131 1132 /** 1133 * dmaengine_terminate_sync() - Terminate all active DMA transfers 1134 * @chan: The channel for which to terminate the transfers 1135 * 1136 * Calling this function will terminate all active and pending transfers 1137 * that have previously been submitted to the channel. It is similar to 1138 * dmaengine_terminate_async() but guarantees that the DMA transfer has actually 1139 * stopped and that all complete callbacks have finished running when the 1140 * function returns. 1141 * 1142 * This function must only be called from non-atomic context and must not be 1143 * called from within a complete callback of a descriptor submitted on the same 1144 * channel. 1145 */ 1146 static inline int dmaengine_terminate_sync(struct dma_chan *chan) 1147 { 1148 int ret; 1149 1150 ret = dmaengine_terminate_async(chan); 1151 if (ret) 1152 return ret; 1153 1154 dmaengine_synchronize(chan); 1155 1156 return 0; 1157 } 1158 1159 static inline int dmaengine_pause(struct dma_chan *chan) 1160 { 1161 if (chan->device->device_pause) 1162 return chan->device->device_pause(chan); 1163 1164 return -ENOSYS; 1165 } 1166 1167 static inline int dmaengine_resume(struct dma_chan *chan) 1168 { 1169 if (chan->device->device_resume) 1170 return chan->device->device_resume(chan); 1171 1172 return -ENOSYS; 1173 } 1174 1175 static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan, 1176 dma_cookie_t cookie, struct dma_tx_state *state) 1177 { 1178 return chan->device->device_tx_status(chan, cookie, state); 1179 } 1180 1181 static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc) 1182 { 1183 return desc->tx_submit(desc); 1184 } 1185 1186 static inline bool dmaengine_check_align(enum dmaengine_alignment align, 1187 size_t off1, size_t off2, size_t len) 1188 { 1189 return !(((1 << align) - 1) & (off1 | off2 | len)); 1190 } 1191 1192 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1, 1193 size_t off2, size_t len) 1194 { 1195 return dmaengine_check_align(dev->copy_align, off1, off2, len); 1196 } 1197 1198 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1, 1199 size_t off2, size_t len) 1200 { 1201 return dmaengine_check_align(dev->xor_align, off1, off2, len); 1202 } 1203 1204 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1, 1205 size_t off2, size_t len) 1206 { 1207 return dmaengine_check_align(dev->pq_align, off1, off2, len); 1208 } 1209 1210 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, 1211 size_t off2, size_t len) 1212 { 1213 return dmaengine_check_align(dev->fill_align, off1, off2, len); 1214 } 1215 1216 static inline void 1217 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) 1218 { 1219 dma->max_pq = maxpq; 1220 if (has_pq_continue) 1221 dma->max_pq |= DMA_HAS_PQ_CONTINUE; 1222 } 1223 1224 static inline bool dmaf_continue(enum dma_ctrl_flags flags) 1225 { 1226 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; 1227 } 1228 1229 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) 1230 { 1231 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; 1232 1233 return (flags & mask) == mask; 1234 } 1235 1236 static inline bool dma_dev_has_pq_continue(struct dma_device *dma) 1237 { 1238 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; 1239 } 1240 1241 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma) 1242 { 1243 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; 1244 } 1245 1246 /* dma_maxpq - reduce maxpq in the face of continued operations 1247 * @dma - dma device with PQ capability 1248 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set 1249 * 1250 * When an engine does not support native continuation we need 3 extra 1251 * source slots to reuse P and Q with the following coefficients: 1252 * 1/ {00} * P : remove P from Q', but use it as a source for P' 1253 * 2/ {01} * Q : use Q to continue Q' calculation 1254 * 3/ {00} * Q : subtract Q from P' to cancel (2) 1255 * 1256 * In the case where P is disabled we only need 1 extra source: 1257 * 1/ {01} * Q : use Q to continue Q' calculation 1258 */ 1259 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) 1260 { 1261 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) 1262 return dma_dev_to_maxpq(dma); 1263 if (dmaf_p_disabled_continue(flags)) 1264 return dma_dev_to_maxpq(dma) - 1; 1265 if (dmaf_continue(flags)) 1266 return dma_dev_to_maxpq(dma) - 3; 1267 BUG(); 1268 } 1269 1270 static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg, 1271 size_t dir_icg) 1272 { 1273 if (inc) { 1274 if (dir_icg) 1275 return dir_icg; 1276 if (sgl) 1277 return icg; 1278 } 1279 1280 return 0; 1281 } 1282 1283 static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt, 1284 struct data_chunk *chunk) 1285 { 1286 return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl, 1287 chunk->icg, chunk->dst_icg); 1288 } 1289 1290 static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt, 1291 struct data_chunk *chunk) 1292 { 1293 return dmaengine_get_icg(xt->src_inc, xt->src_sgl, 1294 chunk->icg, chunk->src_icg); 1295 } 1296 1297 /* --- public DMA engine API --- */ 1298 1299 #ifdef CONFIG_DMA_ENGINE 1300 void dmaengine_get(void); 1301 void dmaengine_put(void); 1302 #else 1303 static inline void dmaengine_get(void) 1304 { 1305 } 1306 static inline void dmaengine_put(void) 1307 { 1308 } 1309 #endif 1310 1311 #ifdef CONFIG_ASYNC_TX_DMA 1312 #define async_dmaengine_get() dmaengine_get() 1313 #define async_dmaengine_put() dmaengine_put() 1314 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH 1315 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) 1316 #else 1317 #define async_dma_find_channel(type) dma_find_channel(type) 1318 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */ 1319 #else 1320 static inline void async_dmaengine_get(void) 1321 { 1322 } 1323 static inline void async_dmaengine_put(void) 1324 { 1325 } 1326 static inline struct dma_chan * 1327 async_dma_find_channel(enum dma_transaction_type type) 1328 { 1329 return NULL; 1330 } 1331 #endif /* CONFIG_ASYNC_TX_DMA */ 1332 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, 1333 struct dma_chan *chan); 1334 1335 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) 1336 { 1337 tx->flags |= DMA_CTRL_ACK; 1338 } 1339 1340 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) 1341 { 1342 tx->flags &= ~DMA_CTRL_ACK; 1343 } 1344 1345 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) 1346 { 1347 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; 1348 } 1349 1350 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) 1351 static inline void 1352 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) 1353 { 1354 set_bit(tx_type, dstp->bits); 1355 } 1356 1357 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) 1358 static inline void 1359 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) 1360 { 1361 clear_bit(tx_type, dstp->bits); 1362 } 1363 1364 #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) 1365 static inline void __dma_cap_zero(dma_cap_mask_t *dstp) 1366 { 1367 bitmap_zero(dstp->bits, DMA_TX_TYPE_END); 1368 } 1369 1370 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) 1371 static inline int 1372 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) 1373 { 1374 return test_bit(tx_type, srcp->bits); 1375 } 1376 1377 #define for_each_dma_cap_mask(cap, mask) \ 1378 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END) 1379 1380 /** 1381 * dma_async_issue_pending - flush pending transactions to HW 1382 * @chan: target DMA channel 1383 * 1384 * This allows drivers to push copies to HW in batches, 1385 * reducing MMIO writes where possible. 1386 */ 1387 static inline void dma_async_issue_pending(struct dma_chan *chan) 1388 { 1389 chan->device->device_issue_pending(chan); 1390 } 1391 1392 /** 1393 * dma_async_is_tx_complete - poll for transaction completion 1394 * @chan: DMA channel 1395 * @cookie: transaction identifier to check status of 1396 * @last: returns last completed cookie, can be NULL 1397 * @used: returns last issued cookie, can be NULL 1398 * 1399 * If @last and @used are passed in, upon return they reflect the driver 1400 * internal state and can be used with dma_async_is_complete() to check 1401 * the status of multiple cookies without re-checking hardware state. 1402 */ 1403 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, 1404 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) 1405 { 1406 struct dma_tx_state state; 1407 enum dma_status status; 1408 1409 status = chan->device->device_tx_status(chan, cookie, &state); 1410 if (last) 1411 *last = state.last; 1412 if (used) 1413 *used = state.used; 1414 return status; 1415 } 1416 1417 /** 1418 * dma_async_is_complete - test a cookie against chan state 1419 * @cookie: transaction identifier to test status of 1420 * @last_complete: last know completed transaction 1421 * @last_used: last cookie value handed out 1422 * 1423 * dma_async_is_complete() is used in dma_async_is_tx_complete() 1424 * the test logic is separated for lightweight testing of multiple cookies 1425 */ 1426 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, 1427 dma_cookie_t last_complete, dma_cookie_t last_used) 1428 { 1429 if (last_complete <= last_used) { 1430 if ((cookie <= last_complete) || (cookie > last_used)) 1431 return DMA_COMPLETE; 1432 } else { 1433 if ((cookie <= last_complete) && (cookie > last_used)) 1434 return DMA_COMPLETE; 1435 } 1436 return DMA_IN_PROGRESS; 1437 } 1438 1439 static inline void 1440 dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue) 1441 { 1442 if (!st) 1443 return; 1444 1445 st->last = last; 1446 st->used = used; 1447 st->residue = residue; 1448 } 1449 1450 #ifdef CONFIG_DMA_ENGINE 1451 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); 1452 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); 1453 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); 1454 void dma_issue_pending_all(void); 1455 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, 1456 dma_filter_fn fn, void *fn_param, 1457 struct device_node *np); 1458 struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name); 1459 1460 struct dma_chan *dma_request_chan(struct device *dev, const char *name); 1461 struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask); 1462 1463 void dma_release_channel(struct dma_chan *chan); 1464 int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps); 1465 #else 1466 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) 1467 { 1468 return NULL; 1469 } 1470 static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) 1471 { 1472 return DMA_COMPLETE; 1473 } 1474 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) 1475 { 1476 return DMA_COMPLETE; 1477 } 1478 static inline void dma_issue_pending_all(void) 1479 { 1480 } 1481 static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, 1482 dma_filter_fn fn, 1483 void *fn_param, 1484 struct device_node *np) 1485 { 1486 return NULL; 1487 } 1488 static inline struct dma_chan *dma_request_slave_channel(struct device *dev, 1489 const char *name) 1490 { 1491 return NULL; 1492 } 1493 static inline struct dma_chan *dma_request_chan(struct device *dev, 1494 const char *name) 1495 { 1496 return ERR_PTR(-ENODEV); 1497 } 1498 static inline struct dma_chan *dma_request_chan_by_mask( 1499 const dma_cap_mask_t *mask) 1500 { 1501 return ERR_PTR(-ENODEV); 1502 } 1503 static inline void dma_release_channel(struct dma_chan *chan) 1504 { 1505 } 1506 static inline int dma_get_slave_caps(struct dma_chan *chan, 1507 struct dma_slave_caps *caps) 1508 { 1509 return -ENXIO; 1510 } 1511 #endif 1512 1513 #define dma_request_slave_channel_reason(dev, name) dma_request_chan(dev, name) 1514 1515 static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx) 1516 { 1517 struct dma_slave_caps caps; 1518 int ret; 1519 1520 ret = dma_get_slave_caps(tx->chan, &caps); 1521 if (ret) 1522 return ret; 1523 1524 if (!caps.descriptor_reuse) 1525 return -EPERM; 1526 1527 tx->flags |= DMA_CTRL_REUSE; 1528 return 0; 1529 } 1530 1531 static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx) 1532 { 1533 tx->flags &= ~DMA_CTRL_REUSE; 1534 } 1535 1536 static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx) 1537 { 1538 return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE; 1539 } 1540 1541 static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc) 1542 { 1543 /* this is supported for reusable desc, so check that */ 1544 if (!dmaengine_desc_test_reuse(desc)) 1545 return -EPERM; 1546 1547 return desc->desc_free(desc); 1548 } 1549 1550 /* --- DMA device --- */ 1551 1552 int dma_async_device_register(struct dma_device *device); 1553 int dmaenginem_async_device_register(struct dma_device *device); 1554 void dma_async_device_unregister(struct dma_device *device); 1555 int dma_async_device_channel_register(struct dma_device *device, 1556 struct dma_chan *chan); 1557 void dma_async_device_channel_unregister(struct dma_device *device, 1558 struct dma_chan *chan); 1559 void dma_run_dependencies(struct dma_async_tx_descriptor *tx); 1560 #define dma_request_channel(mask, x, y) \ 1561 __dma_request_channel(&(mask), x, y, NULL) 1562 1563 static inline struct dma_chan 1564 *dma_request_slave_channel_compat(const dma_cap_mask_t mask, 1565 dma_filter_fn fn, void *fn_param, 1566 struct device *dev, const char *name) 1567 { 1568 struct dma_chan *chan; 1569 1570 chan = dma_request_slave_channel(dev, name); 1571 if (chan) 1572 return chan; 1573 1574 if (!fn || !fn_param) 1575 return NULL; 1576 1577 return __dma_request_channel(&mask, fn, fn_param, NULL); 1578 } 1579 1580 static inline char * 1581 dmaengine_get_direction_text(enum dma_transfer_direction dir) 1582 { 1583 switch (dir) { 1584 case DMA_DEV_TO_MEM: 1585 return "DEV_TO_MEM"; 1586 case DMA_MEM_TO_DEV: 1587 return "MEM_TO_DEV"; 1588 case DMA_MEM_TO_MEM: 1589 return "MEM_TO_MEM"; 1590 case DMA_DEV_TO_DEV: 1591 return "DEV_TO_DEV"; 1592 default: 1593 return "invalid"; 1594 } 1595 } 1596 #endif /* DMAENGINE_H */ 1597