1 /* 2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 59 16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called COPYING. 20 */ 21 #ifndef DMAENGINE_H 22 #define DMAENGINE_H 23 24 #include <linux/device.h> 25 #include <linux/uio.h> 26 #include <linux/kref.h> 27 #include <linux/completion.h> 28 #include <linux/rcupdate.h> 29 #include <linux/dma-mapping.h> 30 31 /** 32 * typedef dma_cookie_t - an opaque DMA cookie 33 * 34 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code 35 */ 36 typedef s32 dma_cookie_t; 37 38 #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0) 39 40 /** 41 * enum dma_status - DMA transaction status 42 * @DMA_SUCCESS: transaction completed successfully 43 * @DMA_IN_PROGRESS: transaction not yet processed 44 * @DMA_ERROR: transaction failed 45 */ 46 enum dma_status { 47 DMA_SUCCESS, 48 DMA_IN_PROGRESS, 49 DMA_ERROR, 50 }; 51 52 /** 53 * enum dma_transaction_type - DMA transaction types/indexes 54 */ 55 enum dma_transaction_type { 56 DMA_MEMCPY, 57 DMA_XOR, 58 DMA_PQ_XOR, 59 DMA_DUAL_XOR, 60 DMA_PQ_UPDATE, 61 DMA_ZERO_SUM, 62 DMA_PQ_ZERO_SUM, 63 DMA_MEMSET, 64 DMA_MEMCPY_CRC32C, 65 DMA_INTERRUPT, 66 DMA_PRIVATE, 67 DMA_SLAVE, 68 }; 69 70 /* last transaction type for creation of the capabilities mask */ 71 #define DMA_TX_TYPE_END (DMA_SLAVE + 1) 72 73 74 /** 75 * enum dma_ctrl_flags - DMA flags to augment operation preparation, 76 * control completion, and communicate status. 77 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of 78 * this transaction 79 * @DMA_CTRL_ACK - the descriptor cannot be reused until the client 80 * acknowledges receipt, i.e. has has a chance to establish any 81 * dependency chains 82 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s) 83 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s) 84 */ 85 enum dma_ctrl_flags { 86 DMA_PREP_INTERRUPT = (1 << 0), 87 DMA_CTRL_ACK = (1 << 1), 88 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2), 89 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3), 90 }; 91 92 /** 93 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. 94 * See linux/cpumask.h 95 */ 96 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; 97 98 /** 99 * struct dma_chan_percpu - the per-CPU part of struct dma_chan 100 * @refcount: local_t used for open-coded "bigref" counting 101 * @memcpy_count: transaction counter 102 * @bytes_transferred: byte counter 103 */ 104 105 struct dma_chan_percpu { 106 /* stats */ 107 unsigned long memcpy_count; 108 unsigned long bytes_transferred; 109 }; 110 111 /** 112 * struct dma_chan - devices supply DMA channels, clients use them 113 * @device: ptr to the dma device who supplies this channel, always !%NULL 114 * @cookie: last cookie value returned to client 115 * @chan_id: channel ID for sysfs 116 * @dev: class device for sysfs 117 * @refcount: kref, used in "bigref" slow-mode 118 * @slow_ref: indicates that the DMA channel is free 119 * @rcu: the DMA channel's RCU head 120 * @device_node: used to add this to the device chan list 121 * @local: per-cpu pointer to a struct dma_chan_percpu 122 * @client-count: how many clients are using this channel 123 * @table_count: number of appearances in the mem-to-mem allocation table 124 */ 125 struct dma_chan { 126 struct dma_device *device; 127 dma_cookie_t cookie; 128 129 /* sysfs */ 130 int chan_id; 131 struct dma_chan_dev *dev; 132 133 struct list_head device_node; 134 struct dma_chan_percpu *local; 135 int client_count; 136 int table_count; 137 }; 138 139 /** 140 * struct dma_chan_dev - relate sysfs device node to backing channel device 141 * @chan - driver channel device 142 * @device - sysfs device 143 * @dev_id - parent dma_device dev_id 144 * @idr_ref - reference count to gate release of dma_device dev_id 145 */ 146 struct dma_chan_dev { 147 struct dma_chan *chan; 148 struct device device; 149 int dev_id; 150 atomic_t *idr_ref; 151 }; 152 153 static inline const char *dma_chan_name(struct dma_chan *chan) 154 { 155 return dev_name(&chan->dev->device); 156 } 157 158 void dma_chan_cleanup(struct kref *kref); 159 160 /** 161 * typedef dma_filter_fn - callback filter for dma_request_channel 162 * @chan: channel to be reviewed 163 * @filter_param: opaque parameter passed through dma_request_channel 164 * 165 * When this optional parameter is specified in a call to dma_request_channel a 166 * suitable channel is passed to this routine for further dispositioning before 167 * being returned. Where 'suitable' indicates a non-busy channel that 168 * satisfies the given capability mask. It returns 'true' to indicate that the 169 * channel is suitable. 170 */ 171 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); 172 173 typedef void (*dma_async_tx_callback)(void *dma_async_param); 174 /** 175 * struct dma_async_tx_descriptor - async transaction descriptor 176 * ---dma generic offload fields--- 177 * @cookie: tracking cookie for this transaction, set to -EBUSY if 178 * this tx is sitting on a dependency list 179 * @flags: flags to augment operation preparation, control completion, and 180 * communicate status 181 * @phys: physical address of the descriptor 182 * @tx_list: driver common field for operations that require multiple 183 * descriptors 184 * @chan: target channel for this operation 185 * @tx_submit: set the prepared descriptor(s) to be executed by the engine 186 * @callback: routine to call after this operation is complete 187 * @callback_param: general parameter to pass to the callback routine 188 * ---async_tx api specific fields--- 189 * @next: at completion submit this descriptor 190 * @parent: pointer to the next level up in the dependency chain 191 * @lock: protect the parent and next pointers 192 */ 193 struct dma_async_tx_descriptor { 194 dma_cookie_t cookie; 195 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ 196 dma_addr_t phys; 197 struct list_head tx_list; 198 struct dma_chan *chan; 199 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); 200 dma_async_tx_callback callback; 201 void *callback_param; 202 struct dma_async_tx_descriptor *next; 203 struct dma_async_tx_descriptor *parent; 204 spinlock_t lock; 205 }; 206 207 /** 208 * struct dma_device - info on the entity supplying DMA services 209 * @chancnt: how many DMA channels are supported 210 * @channels: the list of struct dma_chan 211 * @global_node: list_head for global dma_device_list 212 * @cap_mask: one or more dma_capability flags 213 * @max_xor: maximum number of xor sources, 0 if no capability 214 * @refcount: reference count 215 * @done: IO completion struct 216 * @dev_id: unique device ID 217 * @dev: struct device reference for dma mapping api 218 * @device_alloc_chan_resources: allocate resources and return the 219 * number of allocated descriptors 220 * @device_free_chan_resources: release DMA channel's resources 221 * @device_prep_dma_memcpy: prepares a memcpy operation 222 * @device_prep_dma_xor: prepares a xor operation 223 * @device_prep_dma_zero_sum: prepares a zero_sum operation 224 * @device_prep_dma_memset: prepares a memset operation 225 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation 226 * @device_prep_slave_sg: prepares a slave dma operation 227 * @device_terminate_all: terminate all pending operations 228 * @device_issue_pending: push pending transactions to hardware 229 */ 230 struct dma_device { 231 232 unsigned int chancnt; 233 struct list_head channels; 234 struct list_head global_node; 235 dma_cap_mask_t cap_mask; 236 int max_xor; 237 238 int dev_id; 239 struct device *dev; 240 241 int (*device_alloc_chan_resources)(struct dma_chan *chan); 242 void (*device_free_chan_resources)(struct dma_chan *chan); 243 244 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( 245 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 246 size_t len, unsigned long flags); 247 struct dma_async_tx_descriptor *(*device_prep_dma_xor)( 248 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, 249 unsigned int src_cnt, size_t len, unsigned long flags); 250 struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)( 251 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, 252 size_t len, u32 *result, unsigned long flags); 253 struct dma_async_tx_descriptor *(*device_prep_dma_memset)( 254 struct dma_chan *chan, dma_addr_t dest, int value, size_t len, 255 unsigned long flags); 256 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( 257 struct dma_chan *chan, unsigned long flags); 258 259 struct dma_async_tx_descriptor *(*device_prep_slave_sg)( 260 struct dma_chan *chan, struct scatterlist *sgl, 261 unsigned int sg_len, enum dma_data_direction direction, 262 unsigned long flags); 263 void (*device_terminate_all)(struct dma_chan *chan); 264 265 enum dma_status (*device_is_tx_complete)(struct dma_chan *chan, 266 dma_cookie_t cookie, dma_cookie_t *last, 267 dma_cookie_t *used); 268 void (*device_issue_pending)(struct dma_chan *chan); 269 }; 270 271 /* --- public DMA engine API --- */ 272 273 void dmaengine_get(void); 274 void dmaengine_put(void); 275 dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, 276 void *dest, void *src, size_t len); 277 dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, 278 struct page *page, unsigned int offset, void *kdata, size_t len); 279 dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, 280 struct page *dest_pg, unsigned int dest_off, struct page *src_pg, 281 unsigned int src_off, size_t len); 282 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, 283 struct dma_chan *chan); 284 285 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) 286 { 287 tx->flags |= DMA_CTRL_ACK; 288 } 289 290 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) 291 { 292 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; 293 } 294 295 #define first_dma_cap(mask) __first_dma_cap(&(mask)) 296 static inline int __first_dma_cap(const dma_cap_mask_t *srcp) 297 { 298 return min_t(int, DMA_TX_TYPE_END, 299 find_first_bit(srcp->bits, DMA_TX_TYPE_END)); 300 } 301 302 #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask)) 303 static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp) 304 { 305 return min_t(int, DMA_TX_TYPE_END, 306 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1)); 307 } 308 309 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) 310 static inline void 311 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) 312 { 313 set_bit(tx_type, dstp->bits); 314 } 315 316 #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) 317 static inline void __dma_cap_zero(dma_cap_mask_t *dstp) 318 { 319 bitmap_zero(dstp->bits, DMA_TX_TYPE_END); 320 } 321 322 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) 323 static inline int 324 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) 325 { 326 return test_bit(tx_type, srcp->bits); 327 } 328 329 #define for_each_dma_cap_mask(cap, mask) \ 330 for ((cap) = first_dma_cap(mask); \ 331 (cap) < DMA_TX_TYPE_END; \ 332 (cap) = next_dma_cap((cap), (mask))) 333 334 /** 335 * dma_async_issue_pending - flush pending transactions to HW 336 * @chan: target DMA channel 337 * 338 * This allows drivers to push copies to HW in batches, 339 * reducing MMIO writes where possible. 340 */ 341 static inline void dma_async_issue_pending(struct dma_chan *chan) 342 { 343 chan->device->device_issue_pending(chan); 344 } 345 346 #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan) 347 348 /** 349 * dma_async_is_tx_complete - poll for transaction completion 350 * @chan: DMA channel 351 * @cookie: transaction identifier to check status of 352 * @last: returns last completed cookie, can be NULL 353 * @used: returns last issued cookie, can be NULL 354 * 355 * If @last and @used are passed in, upon return they reflect the driver 356 * internal state and can be used with dma_async_is_complete() to check 357 * the status of multiple cookies without re-checking hardware state. 358 */ 359 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, 360 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) 361 { 362 return chan->device->device_is_tx_complete(chan, cookie, last, used); 363 } 364 365 #define dma_async_memcpy_complete(chan, cookie, last, used)\ 366 dma_async_is_tx_complete(chan, cookie, last, used) 367 368 /** 369 * dma_async_is_complete - test a cookie against chan state 370 * @cookie: transaction identifier to test status of 371 * @last_complete: last know completed transaction 372 * @last_used: last cookie value handed out 373 * 374 * dma_async_is_complete() is used in dma_async_memcpy_complete() 375 * the test logic is separated for lightweight testing of multiple cookies 376 */ 377 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, 378 dma_cookie_t last_complete, dma_cookie_t last_used) 379 { 380 if (last_complete <= last_used) { 381 if ((cookie <= last_complete) || (cookie > last_used)) 382 return DMA_SUCCESS; 383 } else { 384 if ((cookie <= last_complete) && (cookie > last_used)) 385 return DMA_SUCCESS; 386 } 387 return DMA_IN_PROGRESS; 388 } 389 390 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); 391 #ifdef CONFIG_DMA_ENGINE 392 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); 393 #else 394 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) 395 { 396 return DMA_SUCCESS; 397 } 398 #endif 399 400 /* --- DMA device --- */ 401 402 int dma_async_device_register(struct dma_device *device); 403 void dma_async_device_unregister(struct dma_device *device); 404 void dma_run_dependencies(struct dma_async_tx_descriptor *tx); 405 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); 406 void dma_issue_pending_all(void); 407 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) 408 struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param); 409 void dma_release_channel(struct dma_chan *chan); 410 411 /* --- Helper iov-locking functions --- */ 412 413 struct dma_page_list { 414 char __user *base_address; 415 int nr_pages; 416 struct page **pages; 417 }; 418 419 struct dma_pinned_list { 420 int nr_iovecs; 421 struct dma_page_list page_list[0]; 422 }; 423 424 struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len); 425 void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list); 426 427 dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov, 428 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len); 429 dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov, 430 struct dma_pinned_list *pinned_list, struct page *page, 431 unsigned int offset, size_t len); 432 433 #endif /* DMAENGINE_H */ 434