1 /* 2 * AMD CS5535/CS5536 definitions 3 * Copyright (C) 2006 Advanced Micro Devices, Inc. 4 * Copyright (C) 2009 Andres Salomon <[email protected]> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of version 2 of the GNU General Public License 8 * as published by the Free Software Foundation. 9 */ 10 11 #ifndef _CS5535_H 12 #define _CS5535_H 13 14 #include <asm/msr.h> 15 16 /* MSRs */ 17 #define MSR_GLIU_P2D_RO0 0x10000029 18 19 #define MSR_LX_GLD_MSR_CONFIG 0x48002001 20 #define MSR_LX_MSR_PADSEL 0x48002011 /* NOT 0x48000011; the data 21 * sheet has the wrong value */ 22 #define MSR_GLCP_SYS_RSTPLL 0x4C000014 23 #define MSR_GLCP_DOTPLL 0x4C000015 24 25 #define MSR_LBAR_SMB 0x5140000B 26 #define MSR_LBAR_GPIO 0x5140000C 27 #define MSR_LBAR_MFGPT 0x5140000D 28 #define MSR_LBAR_ACPI 0x5140000E 29 #define MSR_LBAR_PMS 0x5140000F 30 31 #define MSR_DIVIL_SOFT_RESET 0x51400017 32 33 #define MSR_PIC_YSEL_LOW 0x51400020 34 #define MSR_PIC_YSEL_HIGH 0x51400021 35 #define MSR_PIC_ZSEL_LOW 0x51400022 36 #define MSR_PIC_ZSEL_HIGH 0x51400023 37 #define MSR_PIC_IRQM_LPC 0x51400025 38 39 #define MSR_MFGPT_IRQ 0x51400028 40 #define MSR_MFGPT_NR 0x51400029 41 #define MSR_MFGPT_SETUP 0x5140002B 42 43 #define MSR_RTC_DOMA_OFFSET 0x51400055 44 #define MSR_RTC_MONA_OFFSET 0x51400056 45 #define MSR_RTC_CEN_OFFSET 0x51400057 46 47 #define MSR_LX_SPARE_MSR 0x80000011 /* DC-specific */ 48 49 #define MSR_GX_GLD_MSR_CONFIG 0xC0002001 50 #define MSR_GX_MSR_PADSEL 0xC0002011 51 52 static inline int cs5535_pic_unreqz_select_high(unsigned int group, 53 unsigned int irq) 54 { 55 uint32_t lo, hi; 56 57 rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi); 58 lo &= ~(0xF << (group * 4)); 59 lo |= (irq & 0xF) << (group * 4); 60 wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi); 61 return 0; 62 } 63 64 /* PIC registers */ 65 #define CS5536_PIC_INT_SEL1 0x4d0 66 #define CS5536_PIC_INT_SEL2 0x4d1 67 68 /* resource sizes */ 69 #define LBAR_GPIO_SIZE 0xFF 70 #define LBAR_MFGPT_SIZE 0x40 71 #define LBAR_ACPI_SIZE 0x40 72 #define LBAR_PMS_SIZE 0x80 73 74 /* 75 * PMC registers (PMS block) 76 * It is only safe to access these registers as dword accesses. 77 * See CS5536 Specification Update erratas 17 & 18 78 */ 79 #define CS5536_PM_SCLK 0x10 80 #define CS5536_PM_IN_SLPCTL 0x20 81 #define CS5536_PM_WKXD 0x34 82 #define CS5536_PM_WKD 0x30 83 #define CS5536_PM_SSC 0x54 84 85 /* 86 * PM registers (ACPI block) 87 * It is only safe to access these registers as dword accesses. 88 * See CS5536 Specification Update erratas 17 & 18 89 */ 90 #define CS5536_PM1_STS 0x00 91 #define CS5536_PM1_EN 0x02 92 #define CS5536_PM1_CNT 0x08 93 #define CS5536_PM_GPE0_STS 0x18 94 #define CS5536_PM_GPE0_EN 0x1c 95 96 /* CS5536_PM1_STS bits */ 97 #define CS5536_WAK_FLAG (1 << 15) 98 #define CS5536_RTC_FLAG (1 << 10) 99 #define CS5536_PWRBTN_FLAG (1 << 8) 100 101 /* CS5536_PM1_EN bits */ 102 #define CS5536_PM_PWRBTN (1 << 8) 103 #define CS5536_PM_RTC (1 << 10) 104 105 /* CS5536_PM_GPE0_STS bits */ 106 #define CS5536_GPIOM7_PME_FLAG (1 << 31) 107 #define CS5536_GPIOM6_PME_FLAG (1 << 30) 108 109 /* CS5536_PM_GPE0_EN bits */ 110 #define CS5536_GPIOM7_PME_EN (1 << 31) 111 #define CS5536_GPIOM6_PME_EN (1 << 30) 112 113 /* VSA2 magic values */ 114 #define VSA_VRC_INDEX 0xAC1C 115 #define VSA_VRC_DATA 0xAC1E 116 #define VSA_VR_UNLOCK 0xFC53 /* unlock virtual register */ 117 #define VSA_VR_SIGNATURE 0x0003 118 #define VSA_VR_MEM_SIZE 0x0200 119 #define AMD_VSA_SIG 0x4132 /* signature is ascii 'VSA2' */ 120 #define GSW_VSA_SIG 0x534d /* General Software signature */ 121 122 #include <linux/io.h> 123 124 static inline int cs5535_has_vsa2(void) 125 { 126 static int has_vsa2 = -1; 127 128 if (has_vsa2 == -1) { 129 uint16_t val; 130 131 /* 132 * The VSA has virtual registers that we can query for a 133 * signature. 134 */ 135 outw(VSA_VR_UNLOCK, VSA_VRC_INDEX); 136 outw(VSA_VR_SIGNATURE, VSA_VRC_INDEX); 137 138 val = inw(VSA_VRC_DATA); 139 has_vsa2 = (val == AMD_VSA_SIG || val == GSW_VSA_SIG); 140 } 141 142 return has_vsa2; 143 } 144 145 /* GPIOs */ 146 #define GPIO_OUTPUT_VAL 0x00 147 #define GPIO_OUTPUT_ENABLE 0x04 148 #define GPIO_OUTPUT_OPEN_DRAIN 0x08 149 #define GPIO_OUTPUT_INVERT 0x0C 150 #define GPIO_OUTPUT_AUX1 0x10 151 #define GPIO_OUTPUT_AUX2 0x14 152 #define GPIO_PULL_UP 0x18 153 #define GPIO_PULL_DOWN 0x1C 154 #define GPIO_INPUT_ENABLE 0x20 155 #define GPIO_INPUT_INVERT 0x24 156 #define GPIO_INPUT_FILTER 0x28 157 #define GPIO_INPUT_EVENT_COUNT 0x2C 158 #define GPIO_READ_BACK 0x30 159 #define GPIO_INPUT_AUX1 0x34 160 #define GPIO_EVENTS_ENABLE 0x38 161 #define GPIO_LOCK_ENABLE 0x3C 162 #define GPIO_POSITIVE_EDGE_EN 0x40 163 #define GPIO_NEGATIVE_EDGE_EN 0x44 164 #define GPIO_POSITIVE_EDGE_STS 0x48 165 #define GPIO_NEGATIVE_EDGE_STS 0x4C 166 167 #define GPIO_FLTR7_AMOUNT 0xD8 168 169 #define GPIO_MAP_X 0xE0 170 #define GPIO_MAP_Y 0xE4 171 #define GPIO_MAP_Z 0xE8 172 #define GPIO_MAP_W 0xEC 173 174 #define GPIO_FE7_SEL 0xF7 175 176 void cs5535_gpio_set(unsigned offset, unsigned int reg); 177 void cs5535_gpio_clear(unsigned offset, unsigned int reg); 178 int cs5535_gpio_isset(unsigned offset, unsigned int reg); 179 int cs5535_gpio_set_irq(unsigned group, unsigned irq); 180 void cs5535_gpio_setup_event(unsigned offset, int pair, int pme); 181 182 /* MFGPTs */ 183 184 #define MFGPT_MAX_TIMERS 8 185 #define MFGPT_TIMER_ANY (-1) 186 187 #define MFGPT_DOMAIN_WORKING 1 188 #define MFGPT_DOMAIN_STANDBY 2 189 #define MFGPT_DOMAIN_ANY (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY) 190 191 #define MFGPT_CMP1 0 192 #define MFGPT_CMP2 1 193 194 #define MFGPT_EVENT_IRQ 0 195 #define MFGPT_EVENT_NMI 1 196 #define MFGPT_EVENT_RESET 3 197 198 #define MFGPT_REG_CMP1 0 199 #define MFGPT_REG_CMP2 2 200 #define MFGPT_REG_COUNTER 4 201 #define MFGPT_REG_SETUP 6 202 203 #define MFGPT_SETUP_CNTEN (1 << 15) 204 #define MFGPT_SETUP_CMP2 (1 << 14) 205 #define MFGPT_SETUP_CMP1 (1 << 13) 206 #define MFGPT_SETUP_SETUP (1 << 12) 207 #define MFGPT_SETUP_STOPEN (1 << 11) 208 #define MFGPT_SETUP_EXTEN (1 << 10) 209 #define MFGPT_SETUP_REVEN (1 << 5) 210 #define MFGPT_SETUP_CLKSEL (1 << 4) 211 212 struct cs5535_mfgpt_timer; 213 214 extern uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer, 215 uint16_t reg); 216 extern void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg, 217 uint16_t value); 218 219 extern int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp, 220 int event, int enable); 221 extern int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp, 222 int *irq, int enable); 223 extern struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer, 224 int domain); 225 extern void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer); 226 227 static inline int cs5535_mfgpt_setup_irq(struct cs5535_mfgpt_timer *timer, 228 int cmp, int *irq) 229 { 230 return cs5535_mfgpt_set_irq(timer, cmp, irq, 1); 231 } 232 233 static inline int cs5535_mfgpt_release_irq(struct cs5535_mfgpt_timer *timer, 234 int cmp, int *irq) 235 { 236 return cs5535_mfgpt_set_irq(timer, cmp, irq, 0); 237 } 238 239 #endif 240