1 /* 2 * linux/include/linux/clk-provider.h 3 * 4 * Copyright (c) 2010-2011 Jeremy Kerr <[email protected]> 5 * Copyright (C) 2011-2012 Linaro Ltd <[email protected]> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #ifndef __LINUX_CLK_PROVIDER_H 12 #define __LINUX_CLK_PROVIDER_H 13 14 #include <linux/clk.h> 15 #include <linux/io.h> 16 17 #ifdef CONFIG_COMMON_CLK 18 19 /* 20 * flags used across common struct clk. these flags should only affect the 21 * top-level framework. custom flags for dealing with hardware specifics 22 * belong in struct clk_foo 23 */ 24 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 25 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 26 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 27 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 28 #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ 29 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ 30 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 31 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 32 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 33 34 struct clk_hw; 35 struct dentry; 36 37 /** 38 * struct clk_ops - Callback operations for hardware clocks; these are to 39 * be provided by the clock implementation, and will be called by drivers 40 * through the clk_* api. 41 * 42 * @prepare: Prepare the clock for enabling. This must not return until 43 * the clock is fully prepared, and it's safe to call clk_enable. 44 * This callback is intended to allow clock implementations to 45 * do any initialisation that may sleep. Called with 46 * prepare_lock held. 47 * 48 * @unprepare: Release the clock from its prepared state. This will typically 49 * undo any work done in the @prepare callback. Called with 50 * prepare_lock held. 51 * 52 * @is_prepared: Queries the hardware to determine if the clock is prepared. 53 * This function is allowed to sleep. Optional, if this op is not 54 * set then the prepare count will be used. 55 * 56 * @unprepare_unused: Unprepare the clock atomically. Only called from 57 * clk_disable_unused for prepare clocks with special needs. 58 * Called with prepare mutex held. This function may sleep. 59 * 60 * @enable: Enable the clock atomically. This must not return until the 61 * clock is generating a valid clock signal, usable by consumer 62 * devices. Called with enable_lock held. This function must not 63 * sleep. 64 * 65 * @disable: Disable the clock atomically. Called with enable_lock held. 66 * This function must not sleep. 67 * 68 * @is_enabled: Queries the hardware to determine if the clock is enabled. 69 * This function must not sleep. Optional, if this op is not 70 * set then the enable count will be used. 71 * 72 * @disable_unused: Disable the clock atomically. Only called from 73 * clk_disable_unused for gate clocks with special needs. 74 * Called with enable_lock held. This function must not 75 * sleep. 76 * 77 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The 78 * parent rate is an input parameter. It is up to the caller to 79 * ensure that the prepare_mutex is held across this call. 80 * Returns the calculated rate. Optional, but recommended - if 81 * this op is not set then clock rate will be initialized to 0. 82 * 83 * @round_rate: Given a target rate as input, returns the closest rate actually 84 * supported by the clock. The parent rate is an input/output 85 * parameter. 86 * 87 * @determine_rate: Given a target rate as input, returns the closest rate 88 * actually supported by the clock, and optionally the parent clock 89 * that should be used to provide the clock rate. 90 * 91 * @set_parent: Change the input source of this clock; for clocks with multiple 92 * possible parents specify a new parent by passing in the index 93 * as a u8 corresponding to the parent in either the .parent_names 94 * or .parents arrays. This function in affect translates an 95 * array index into the value programmed into the hardware. 96 * Returns 0 on success, -EERROR otherwise. 97 * 98 * @get_parent: Queries the hardware to determine the parent of a clock. The 99 * return value is a u8 which specifies the index corresponding to 100 * the parent clock. This index can be applied to either the 101 * .parent_names or .parents arrays. In short, this function 102 * translates the parent value read from hardware into an array 103 * index. Currently only called when the clock is initialized by 104 * __clk_init. This callback is mandatory for clocks with 105 * multiple parents. It is optional (and unnecessary) for clocks 106 * with 0 or 1 parents. 107 * 108 * @set_rate: Change the rate of this clock. The requested rate is specified 109 * by the second argument, which should typically be the return 110 * of .round_rate call. The third argument gives the parent rate 111 * which is likely helpful for most .set_rate implementation. 112 * Returns 0 on success, -EERROR otherwise. 113 * 114 * @set_rate_and_parent: Change the rate and the parent of this clock. The 115 * requested rate is specified by the second argument, which 116 * should typically be the return of .round_rate call. The 117 * third argument gives the parent rate which is likely helpful 118 * for most .set_rate_and_parent implementation. The fourth 119 * argument gives the parent index. This callback is optional (and 120 * unnecessary) for clocks with 0 or 1 parents as well as 121 * for clocks that can tolerate switching the rate and the parent 122 * separately via calls to .set_parent and .set_rate. 123 * Returns 0 on success, -EERROR otherwise. 124 * 125 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy 126 * is expressed in ppb (parts per billion). The parent accuracy is 127 * an input parameter. 128 * Returns the calculated accuracy. Optional - if this op is not 129 * set then clock accuracy will be initialized to parent accuracy 130 * or 0 (perfect clock) if clock has no parent. 131 * 132 * @init: Perform platform-specific initialization magic. 133 * This is not not used by any of the basic clock types. 134 * Please consider other ways of solving initialization problems 135 * before using this callback, as its use is discouraged. 136 * 137 * @debug_init: Set up type-specific debugfs entries for this clock. This 138 * is called once, after the debugfs directory entry for this 139 * clock has been created. The dentry pointer representing that 140 * directory is provided as an argument. Called with 141 * prepare_lock held. Returns 0 on success, -EERROR otherwise. 142 * 143 * 144 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 145 * implementations to split any work between atomic (enable) and sleepable 146 * (prepare) contexts. If enabling a clock requires code that might sleep, 147 * this must be done in clk_prepare. Clock enable code that will never be 148 * called in a sleepable context may be implemented in clk_enable. 149 * 150 * Typically, drivers will call clk_prepare when a clock may be needed later 151 * (eg. when a device is opened), and clk_enable when the clock is actually 152 * required (eg. from an interrupt). Note that clk_prepare MUST have been 153 * called before clk_enable. 154 */ 155 struct clk_ops { 156 int (*prepare)(struct clk_hw *hw); 157 void (*unprepare)(struct clk_hw *hw); 158 int (*is_prepared)(struct clk_hw *hw); 159 void (*unprepare_unused)(struct clk_hw *hw); 160 int (*enable)(struct clk_hw *hw); 161 void (*disable)(struct clk_hw *hw); 162 int (*is_enabled)(struct clk_hw *hw); 163 void (*disable_unused)(struct clk_hw *hw); 164 unsigned long (*recalc_rate)(struct clk_hw *hw, 165 unsigned long parent_rate); 166 long (*round_rate)(struct clk_hw *hw, unsigned long rate, 167 unsigned long *parent_rate); 168 long (*determine_rate)(struct clk_hw *hw, unsigned long rate, 169 unsigned long *best_parent_rate, 170 struct clk **best_parent_clk); 171 int (*set_parent)(struct clk_hw *hw, u8 index); 172 u8 (*get_parent)(struct clk_hw *hw); 173 int (*set_rate)(struct clk_hw *hw, unsigned long rate, 174 unsigned long parent_rate); 175 int (*set_rate_and_parent)(struct clk_hw *hw, 176 unsigned long rate, 177 unsigned long parent_rate, u8 index); 178 unsigned long (*recalc_accuracy)(struct clk_hw *hw, 179 unsigned long parent_accuracy); 180 void (*init)(struct clk_hw *hw); 181 int (*debug_init)(struct clk_hw *hw, struct dentry *dentry); 182 }; 183 184 /** 185 * struct clk_init_data - holds init data that's common to all clocks and is 186 * shared between the clock provider and the common clock framework. 187 * 188 * @name: clock name 189 * @ops: operations this clock supports 190 * @parent_names: array of string names for all possible parents 191 * @num_parents: number of possible parents 192 * @flags: framework-level hints and quirks 193 */ 194 struct clk_init_data { 195 const char *name; 196 const struct clk_ops *ops; 197 const char **parent_names; 198 u8 num_parents; 199 unsigned long flags; 200 }; 201 202 /** 203 * struct clk_hw - handle for traversing from a struct clk to its corresponding 204 * hardware-specific structure. struct clk_hw should be declared within struct 205 * clk_foo and then referenced by the struct clk instance that uses struct 206 * clk_foo's clk_ops 207 * 208 * @clk: pointer to the struct clk instance that points back to this struct 209 * clk_hw instance 210 * 211 * @init: pointer to struct clk_init_data that contains the init data shared 212 * with the common clock framework. 213 */ 214 struct clk_hw { 215 struct clk *clk; 216 const struct clk_init_data *init; 217 }; 218 219 /* 220 * DOC: Basic clock implementations common to many platforms 221 * 222 * Each basic clock hardware type is comprised of a structure describing the 223 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 224 * unique flags for that hardware type, a registration function and an 225 * alternative macro for static initialization 226 */ 227 228 /** 229 * struct clk_fixed_rate - fixed-rate clock 230 * @hw: handle between common and hardware-specific interfaces 231 * @fixed_rate: constant frequency of clock 232 */ 233 struct clk_fixed_rate { 234 struct clk_hw hw; 235 unsigned long fixed_rate; 236 unsigned long fixed_accuracy; 237 u8 flags; 238 }; 239 240 extern const struct clk_ops clk_fixed_rate_ops; 241 struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 242 const char *parent_name, unsigned long flags, 243 unsigned long fixed_rate); 244 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, 245 const char *name, const char *parent_name, unsigned long flags, 246 unsigned long fixed_rate, unsigned long fixed_accuracy); 247 248 void of_fixed_clk_setup(struct device_node *np); 249 250 /** 251 * struct clk_gate - gating clock 252 * 253 * @hw: handle between common and hardware-specific interfaces 254 * @reg: register controlling gate 255 * @bit_idx: single bit controlling gate 256 * @flags: hardware-specific flags 257 * @lock: register lock 258 * 259 * Clock which can gate its output. Implements .enable & .disable 260 * 261 * Flags: 262 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 263 * enable the clock. Setting this flag does the opposite: setting the bit 264 * disable the clock and clearing it enables the clock 265 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit 266 * of this register, and mask of gate bits are in higher 16-bit of this 267 * register. While setting the gate bits, higher 16-bit should also be 268 * updated to indicate changing gate bits. 269 */ 270 struct clk_gate { 271 struct clk_hw hw; 272 void __iomem *reg; 273 u8 bit_idx; 274 u8 flags; 275 spinlock_t *lock; 276 }; 277 278 #define CLK_GATE_SET_TO_DISABLE BIT(0) 279 #define CLK_GATE_HIWORD_MASK BIT(1) 280 281 extern const struct clk_ops clk_gate_ops; 282 struct clk *clk_register_gate(struct device *dev, const char *name, 283 const char *parent_name, unsigned long flags, 284 void __iomem *reg, u8 bit_idx, 285 u8 clk_gate_flags, spinlock_t *lock); 286 287 struct clk_div_table { 288 unsigned int val; 289 unsigned int div; 290 }; 291 292 /** 293 * struct clk_divider - adjustable divider clock 294 * 295 * @hw: handle between common and hardware-specific interfaces 296 * @reg: register containing the divider 297 * @shift: shift to the divider bit field 298 * @width: width of the divider bit field 299 * @table: array of value/divider pairs, last entry should have div = 0 300 * @lock: register lock 301 * 302 * Clock with an adjustable divider affecting its output frequency. Implements 303 * .recalc_rate, .set_rate and .round_rate 304 * 305 * Flags: 306 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 307 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 308 * the raw value read from the register, with the value of zero considered 309 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. 310 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 311 * the hardware register 312 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have 313 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. 314 * Some hardware implementations gracefully handle this case and allow a 315 * zero divisor by not modifying their input clock 316 * (divide by one / bypass). 317 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit 318 * of this register, and mask of divider bits are in higher 16-bit of this 319 * register. While setting the divider bits, higher 16-bit should also be 320 * updated to indicate changing divider bits. 321 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded 322 * to the closest integer instead of the up one. 323 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should 324 * not be changed by the clock framework. 325 */ 326 struct clk_divider { 327 struct clk_hw hw; 328 void __iomem *reg; 329 u8 shift; 330 u8 width; 331 u8 flags; 332 const struct clk_div_table *table; 333 spinlock_t *lock; 334 }; 335 336 #define CLK_DIVIDER_ONE_BASED BIT(0) 337 #define CLK_DIVIDER_POWER_OF_TWO BIT(1) 338 #define CLK_DIVIDER_ALLOW_ZERO BIT(2) 339 #define CLK_DIVIDER_HIWORD_MASK BIT(3) 340 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) 341 #define CLK_DIVIDER_READ_ONLY BIT(5) 342 343 extern const struct clk_ops clk_divider_ops; 344 extern const struct clk_ops clk_divider_ro_ops; 345 struct clk *clk_register_divider(struct device *dev, const char *name, 346 const char *parent_name, unsigned long flags, 347 void __iomem *reg, u8 shift, u8 width, 348 u8 clk_divider_flags, spinlock_t *lock); 349 struct clk *clk_register_divider_table(struct device *dev, const char *name, 350 const char *parent_name, unsigned long flags, 351 void __iomem *reg, u8 shift, u8 width, 352 u8 clk_divider_flags, const struct clk_div_table *table, 353 spinlock_t *lock); 354 355 /** 356 * struct clk_mux - multiplexer clock 357 * 358 * @hw: handle between common and hardware-specific interfaces 359 * @reg: register controlling multiplexer 360 * @shift: shift to multiplexer bit field 361 * @width: width of mutliplexer bit field 362 * @flags: hardware-specific flags 363 * @lock: register lock 364 * 365 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 366 * and .recalc_rate 367 * 368 * Flags: 369 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 370 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 371 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this 372 * register, and mask of mux bits are in higher 16-bit of this register. 373 * While setting the mux bits, higher 16-bit should also be updated to 374 * indicate changing mux bits. 375 */ 376 struct clk_mux { 377 struct clk_hw hw; 378 void __iomem *reg; 379 u32 *table; 380 u32 mask; 381 u8 shift; 382 u8 flags; 383 spinlock_t *lock; 384 }; 385 386 #define CLK_MUX_INDEX_ONE BIT(0) 387 #define CLK_MUX_INDEX_BIT BIT(1) 388 #define CLK_MUX_HIWORD_MASK BIT(2) 389 #define CLK_MUX_READ_ONLY BIT(3) /* mux setting cannot be changed */ 390 391 extern const struct clk_ops clk_mux_ops; 392 extern const struct clk_ops clk_mux_ro_ops; 393 394 struct clk *clk_register_mux(struct device *dev, const char *name, 395 const char **parent_names, u8 num_parents, unsigned long flags, 396 void __iomem *reg, u8 shift, u8 width, 397 u8 clk_mux_flags, spinlock_t *lock); 398 399 struct clk *clk_register_mux_table(struct device *dev, const char *name, 400 const char **parent_names, u8 num_parents, unsigned long flags, 401 void __iomem *reg, u8 shift, u32 mask, 402 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 403 404 void of_fixed_factor_clk_setup(struct device_node *node); 405 406 /** 407 * struct clk_fixed_factor - fixed multiplier and divider clock 408 * 409 * @hw: handle between common and hardware-specific interfaces 410 * @mult: multiplier 411 * @div: divider 412 * 413 * Clock with a fixed multiplier and divider. The output frequency is the 414 * parent clock rate divided by div and multiplied by mult. 415 * Implements .recalc_rate, .set_rate and .round_rate 416 */ 417 418 struct clk_fixed_factor { 419 struct clk_hw hw; 420 unsigned int mult; 421 unsigned int div; 422 }; 423 424 extern struct clk_ops clk_fixed_factor_ops; 425 struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 426 const char *parent_name, unsigned long flags, 427 unsigned int mult, unsigned int div); 428 429 /** 430 * struct clk_fractional_divider - adjustable fractional divider clock 431 * 432 * @hw: handle between common and hardware-specific interfaces 433 * @reg: register containing the divider 434 * @mshift: shift to the numerator bit field 435 * @mwidth: width of the numerator bit field 436 * @nshift: shift to the denominator bit field 437 * @nwidth: width of the denominator bit field 438 * @lock: register lock 439 * 440 * Clock with adjustable fractional divider affecting its output frequency. 441 */ 442 443 struct clk_fractional_divider { 444 struct clk_hw hw; 445 void __iomem *reg; 446 u8 mshift; 447 u32 mmask; 448 u8 nshift; 449 u32 nmask; 450 u8 flags; 451 spinlock_t *lock; 452 }; 453 454 extern const struct clk_ops clk_fractional_divider_ops; 455 struct clk *clk_register_fractional_divider(struct device *dev, 456 const char *name, const char *parent_name, unsigned long flags, 457 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, 458 u8 clk_divider_flags, spinlock_t *lock); 459 460 /*** 461 * struct clk_composite - aggregate clock of mux, divider and gate clocks 462 * 463 * @hw: handle between common and hardware-specific interfaces 464 * @mux_hw: handle between composite and hardware-specific mux clock 465 * @rate_hw: handle between composite and hardware-specific rate clock 466 * @gate_hw: handle between composite and hardware-specific gate clock 467 * @mux_ops: clock ops for mux 468 * @rate_ops: clock ops for rate 469 * @gate_ops: clock ops for gate 470 */ 471 struct clk_composite { 472 struct clk_hw hw; 473 struct clk_ops ops; 474 475 struct clk_hw *mux_hw; 476 struct clk_hw *rate_hw; 477 struct clk_hw *gate_hw; 478 479 const struct clk_ops *mux_ops; 480 const struct clk_ops *rate_ops; 481 const struct clk_ops *gate_ops; 482 }; 483 484 struct clk *clk_register_composite(struct device *dev, const char *name, 485 const char **parent_names, int num_parents, 486 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 487 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 488 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 489 unsigned long flags); 490 491 /** 492 * clk_register - allocate a new clock, register it and return an opaque cookie 493 * @dev: device that is registering this clock 494 * @hw: link to hardware-specific clock data 495 * 496 * clk_register is the primary interface for populating the clock tree with new 497 * clock nodes. It returns a pointer to the newly allocated struct clk which 498 * cannot be dereferenced by driver code but may be used in conjuction with the 499 * rest of the clock API. In the event of an error clk_register will return an 500 * error code; drivers must test for an error code after calling clk_register. 501 */ 502 struct clk *clk_register(struct device *dev, struct clk_hw *hw); 503 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); 504 505 void clk_unregister(struct clk *clk); 506 void devm_clk_unregister(struct device *dev, struct clk *clk); 507 508 /* helper functions */ 509 const char *__clk_get_name(struct clk *clk); 510 struct clk_hw *__clk_get_hw(struct clk *clk); 511 u8 __clk_get_num_parents(struct clk *clk); 512 struct clk *__clk_get_parent(struct clk *clk); 513 struct clk *clk_get_parent_by_index(struct clk *clk, u8 index); 514 unsigned int __clk_get_enable_count(struct clk *clk); 515 unsigned int __clk_get_prepare_count(struct clk *clk); 516 unsigned long __clk_get_rate(struct clk *clk); 517 unsigned long __clk_get_accuracy(struct clk *clk); 518 unsigned long __clk_get_flags(struct clk *clk); 519 bool __clk_is_prepared(struct clk *clk); 520 bool __clk_is_enabled(struct clk *clk); 521 struct clk *__clk_lookup(const char *name); 522 long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, 523 unsigned long *best_parent_rate, 524 struct clk **best_parent_p); 525 526 /* 527 * FIXME clock api without lock protection 528 */ 529 int __clk_prepare(struct clk *clk); 530 void __clk_unprepare(struct clk *clk); 531 void __clk_reparent(struct clk *clk, struct clk *new_parent); 532 unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); 533 534 struct of_device_id; 535 536 typedef void (*of_clk_init_cb_t)(struct device_node *); 537 538 struct clk_onecell_data { 539 struct clk **clks; 540 unsigned int clk_num; 541 }; 542 543 extern struct of_device_id __clk_of_table; 544 545 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) 546 547 #ifdef CONFIG_OF 548 int of_clk_add_provider(struct device_node *np, 549 struct clk *(*clk_src_get)(struct of_phandle_args *args, 550 void *data), 551 void *data); 552 void of_clk_del_provider(struct device_node *np); 553 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 554 void *data); 555 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 556 int of_clk_get_parent_count(struct device_node *np); 557 const char *of_clk_get_parent_name(struct device_node *np, int index); 558 559 void of_clk_init(const struct of_device_id *matches); 560 561 #else /* !CONFIG_OF */ 562 563 static inline int of_clk_add_provider(struct device_node *np, 564 struct clk *(*clk_src_get)(struct of_phandle_args *args, 565 void *data), 566 void *data) 567 { 568 return 0; 569 } 570 #define of_clk_del_provider(np) \ 571 { while (0); } 572 static inline struct clk *of_clk_src_simple_get( 573 struct of_phandle_args *clkspec, void *data) 574 { 575 return ERR_PTR(-ENOENT); 576 } 577 static inline struct clk *of_clk_src_onecell_get( 578 struct of_phandle_args *clkspec, void *data) 579 { 580 return ERR_PTR(-ENOENT); 581 } 582 static inline const char *of_clk_get_parent_name(struct device_node *np, 583 int index) 584 { 585 return NULL; 586 } 587 #define of_clk_init(matches) \ 588 { while (0); } 589 #endif /* CONFIG_OF */ 590 591 /* 592 * wrap access to peripherals in accessor routines 593 * for improved portability across platforms 594 */ 595 596 #if IS_ENABLED(CONFIG_PPC) 597 598 static inline u32 clk_readl(u32 __iomem *reg) 599 { 600 return ioread32be(reg); 601 } 602 603 static inline void clk_writel(u32 val, u32 __iomem *reg) 604 { 605 iowrite32be(val, reg); 606 } 607 608 #else /* platform dependent I/O accessors */ 609 610 static inline u32 clk_readl(u32 __iomem *reg) 611 { 612 return readl(reg); 613 } 614 615 static inline void clk_writel(u32 val, u32 __iomem *reg) 616 { 617 writel(val, reg); 618 } 619 620 #endif /* platform dependent I/O accessors */ 621 622 #endif /* CONFIG_COMMON_CLK */ 623 #endif /* CLK_PROVIDER_H */ 624