1 #ifndef LINUX_BCMA_DRIVER_CC_H_ 2 #define LINUX_BCMA_DRIVER_CC_H_ 3 4 #include <linux/platform_device.h> 5 #include <linux/gpio.h> 6 7 /** ChipCommon core registers. **/ 8 #define BCMA_CC_ID 0x0000 9 #define BCMA_CC_ID_ID 0x0000FFFF 10 #define BCMA_CC_ID_ID_SHIFT 0 11 #define BCMA_CC_ID_REV 0x000F0000 12 #define BCMA_CC_ID_REV_SHIFT 16 13 #define BCMA_CC_ID_PKG 0x00F00000 14 #define BCMA_CC_ID_PKG_SHIFT 20 15 #define BCMA_CC_ID_NRCORES 0x0F000000 16 #define BCMA_CC_ID_NRCORES_SHIFT 24 17 #define BCMA_CC_ID_TYPE 0xF0000000 18 #define BCMA_CC_ID_TYPE_SHIFT 28 19 #define BCMA_CC_CAP 0x0004 /* Capabilities */ 20 #define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */ 21 #define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */ 22 #define BCMA_CC_CAP_UARTCLK 0x00000018 /* UART clock select */ 23 #define BCMA_CC_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */ 24 #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */ 25 #define BCMA_CC_CAP_EXTBUS 0x000000C0 /* External buses present */ 26 #define BCMA_CC_CAP_FLASHT 0x00000700 /* Flash Type */ 27 #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */ 28 #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */ 29 #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */ 30 #define BCMA_CC_FLASHT_NAND 0x00000300 /* NAND flash */ 31 #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */ 32 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */ 33 #define BCMA_PLLTYPE_NONE 0x00000000 34 #define BCMA_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */ 35 #define BCMA_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */ 36 #define BCMA_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */ 37 #define BCMA_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */ 38 #define BCMA_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */ 39 #define BCMA_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */ 40 #define BCMA_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */ 41 #define BCMA_CC_CAP_PCTL 0x00040000 /* Power Control */ 42 #define BCMA_CC_CAP_OTPS 0x00380000 /* OTP size */ 43 #define BCMA_CC_CAP_OTPS_SHIFT 19 44 #define BCMA_CC_CAP_OTPS_BASE 5 45 #define BCMA_CC_CAP_JTAGM 0x00400000 /* JTAG master present */ 46 #define BCMA_CC_CAP_BROM 0x00800000 /* Internal boot ROM active */ 47 #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */ 48 #define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */ 49 #define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */ 50 #define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */ 51 #define BCMA_CC_CAP_NFLASH 0x80000000 /* NAND flash present (rev >= 35 or BCM4706?) */ 52 #define BCMA_CC_CORECTL 0x0008 53 #define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ 54 #define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ 55 #define BCMA_CC_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */ 56 #define BCMA_CC_BIST 0x000C 57 #define BCMA_CC_OTPS 0x0010 /* OTP status */ 58 #define BCMA_CC_OTPS_PROGFAIL 0x80000000 59 #define BCMA_CC_OTPS_PROTECT 0x00000007 60 #define BCMA_CC_OTPS_HW_PROTECT 0x00000001 61 #define BCMA_CC_OTPS_SW_PROTECT 0x00000002 62 #define BCMA_CC_OTPS_CID_PROTECT 0x00000004 63 #define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */ 64 #define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8 65 #define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */ 66 #define BCMA_CC_OTPC 0x0014 /* OTP control */ 67 #define BCMA_CC_OTPC_RECWAIT 0xFF000000 68 #define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00 69 #define BCMA_CC_OTPC_PRW_SHIFT 8 70 #define BCMA_CC_OTPC_MAXFAIL 0x00000038 71 #define BCMA_CC_OTPC_VSEL 0x00000006 72 #define BCMA_CC_OTPC_SELVL 0x00000001 73 #define BCMA_CC_OTPP 0x0018 /* OTP prog */ 74 #define BCMA_CC_OTPP_COL 0x000000FF 75 #define BCMA_CC_OTPP_ROW 0x0000FF00 76 #define BCMA_CC_OTPP_ROW_SHIFT 8 77 #define BCMA_CC_OTPP_READERR 0x10000000 78 #define BCMA_CC_OTPP_VALUE 0x20000000 79 #define BCMA_CC_OTPP_READ 0x40000000 80 #define BCMA_CC_OTPP_START 0x80000000 81 #define BCMA_CC_OTPP_BUSY 0x80000000 82 #define BCMA_CC_OTPL 0x001C /* OTP layout */ 83 #define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */ 84 #define BCMA_CC_IRQSTAT 0x0020 85 #define BCMA_CC_IRQMASK 0x0024 86 #define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */ 87 #define BCMA_CC_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */ 88 #define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */ 89 #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */ 90 #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */ 91 #define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1 92 #define BCMA_CC_CHIPST_4313_OTP_PRESENT 2 93 #define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2 94 #define BCMA_CC_CHIPST_4331_OTP_PRESENT 4 95 #define BCMA_CC_CHIPST_43228_ILP_DIV_EN 0x00000001 96 #define BCMA_CC_CHIPST_43228_OTP_PRESENT 0x00000002 97 #define BCMA_CC_CHIPST_43228_SERDES_REFCLK_PADSEL 0x00000004 98 #define BCMA_CC_CHIPST_43228_SDIO_MODE 0x00000008 99 #define BCMA_CC_CHIPST_43228_SDIO_OTP_PRESENT 0x00000010 100 #define BCMA_CC_CHIPST_43228_SDIO_RESET 0x00000020 101 #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */ 102 #define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */ 103 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */ 104 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */ 105 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */ 106 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */ 107 #define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001 108 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ 109 #define BCMA_CC_JCMD_START 0x80000000 110 #define BCMA_CC_JCMD_BUSY 0x80000000 111 #define BCMA_CC_JCMD_PAUSE 0x40000000 112 #define BCMA_CC_JCMD0_ACC_MASK 0x0000F000 113 #define BCMA_CC_JCMD0_ACC_IRDR 0x00000000 114 #define BCMA_CC_JCMD0_ACC_DR 0x00001000 115 #define BCMA_CC_JCMD0_ACC_IR 0x00002000 116 #define BCMA_CC_JCMD0_ACC_RESET 0x00003000 117 #define BCMA_CC_JCMD0_ACC_IRPDR 0x00004000 118 #define BCMA_CC_JCMD0_ACC_PDR 0x00005000 119 #define BCMA_CC_JCMD0_IRW_MASK 0x00000F00 120 #define BCMA_CC_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */ 121 #define BCMA_CC_JCMD_ACC_IRDR 0x00000000 122 #define BCMA_CC_JCMD_ACC_DR 0x00010000 123 #define BCMA_CC_JCMD_ACC_IR 0x00020000 124 #define BCMA_CC_JCMD_ACC_RESET 0x00030000 125 #define BCMA_CC_JCMD_ACC_IRPDR 0x00040000 126 #define BCMA_CC_JCMD_ACC_PDR 0x00050000 127 #define BCMA_CC_JCMD_IRW_MASK 0x00001F00 128 #define BCMA_CC_JCMD_IRW_SHIFT 8 129 #define BCMA_CC_JCMD_DRW_MASK 0x0000003F 130 #define BCMA_CC_JIR 0x0034 /* Rev >= 10 only */ 131 #define BCMA_CC_JDR 0x0038 /* Rev >= 10 only */ 132 #define BCMA_CC_JCTL 0x003C /* Rev >= 10 only */ 133 #define BCMA_CC_JCTL_FORCE_CLK 4 /* Force clock */ 134 #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */ 135 #define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */ 136 #define BCMA_CC_FLASHCTL 0x0040 137 /* Start/busy bit in flashcontrol */ 138 #define BCMA_CC_FLASHCTL_OPCODE 0x000000ff 139 #define BCMA_CC_FLASHCTL_ACTION 0x00000700 140 #define BCMA_CC_FLASHCTL_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */ 141 #define BCMA_CC_FLASHCTL_START 0x80000000 142 #define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START 143 /* Flashcontrol action + opcodes for ST flashes */ 144 #define BCMA_CC_FLASHCTL_ST_WREN 0x0006 /* Write Enable */ 145 #define BCMA_CC_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */ 146 #define BCMA_CC_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */ 147 #define BCMA_CC_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */ 148 #define BCMA_CC_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */ 149 #define BCMA_CC_FLASHCTL_ST_PP 0x0302 /* Page Program */ 150 #define BCMA_CC_FLASHCTL_ST_SE 0x02d8 /* Sector Erase */ 151 #define BCMA_CC_FLASHCTL_ST_BE 0x00c7 /* Bulk Erase */ 152 #define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */ 153 #define BCMA_CC_FLASHCTL_ST_RES 0x03ab /* Read Electronic Signature */ 154 #define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */ 155 #define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */ 156 /* Flashcontrol action + opcodes for Atmel flashes */ 157 #define BCMA_CC_FLASHCTL_AT_READ 0x07e8 158 #define BCMA_CC_FLASHCTL_AT_PAGE_READ 0x07d2 159 #define BCMA_CC_FLASHCTL_AT_STATUS 0x01d7 160 #define BCMA_CC_FLASHCTL_AT_BUF1_WRITE 0x0384 161 #define BCMA_CC_FLASHCTL_AT_BUF2_WRITE 0x0387 162 #define BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM 0x0283 163 #define BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM 0x0286 164 #define BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM 0x0288 165 #define BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM 0x0289 166 #define BCMA_CC_FLASHCTL_AT_PAGE_ERASE 0x0281 167 #define BCMA_CC_FLASHCTL_AT_BLOCK_ERASE 0x0250 168 #define BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 169 #define BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 170 #define BCMA_CC_FLASHCTL_AT_BUF1_LOAD 0x0253 171 #define BCMA_CC_FLASHCTL_AT_BUF2_LOAD 0x0255 172 #define BCMA_CC_FLASHCTL_AT_BUF1_COMPARE 0x0260 173 #define BCMA_CC_FLASHCTL_AT_BUF2_COMPARE 0x0261 174 #define BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM 0x0258 175 #define BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM 0x0259 176 #define BCMA_CC_FLASHADDR 0x0044 177 #define BCMA_CC_FLASHDATA 0x0048 178 /* Status register bits for ST flashes */ 179 #define BCMA_CC_FLASHDATA_ST_WIP 0x01 /* Write In Progress */ 180 #define BCMA_CC_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */ 181 #define BCMA_CC_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */ 182 #define BCMA_CC_FLASHDATA_ST_BP_SHIFT 2 183 #define BCMA_CC_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */ 184 /* Status register bits for Atmel flashes */ 185 #define BCMA_CC_FLASHDATA_AT_READY 0x80 186 #define BCMA_CC_FLASHDATA_AT_MISMATCH 0x40 187 #define BCMA_CC_FLASHDATA_AT_ID_MASK 0x38 188 #define BCMA_CC_FLASHDATA_AT_ID_SHIFT 3 189 #define BCMA_CC_BCAST_ADDR 0x0050 190 #define BCMA_CC_BCAST_DATA 0x0054 191 #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */ 192 #define BCMA_CC_GPIOPULLDOWN 0x005C /* Rev >= 20 only */ 193 #define BCMA_CC_GPIOIN 0x0060 194 #define BCMA_CC_GPIOOUT 0x0064 195 #define BCMA_CC_GPIOOUTEN 0x0068 196 #define BCMA_CC_GPIOCTL 0x006C 197 #define BCMA_CC_GPIOPOL 0x0070 198 #define BCMA_CC_GPIOIRQ 0x0074 199 #define BCMA_CC_WATCHDOG 0x0080 200 #define BCMA_CC_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */ 201 #define BCMA_CC_GPIOTIMER_OFFTIME 0x0000FFFF 202 #define BCMA_CC_GPIOTIMER_OFFTIME_SHIFT 0 203 #define BCMA_CC_GPIOTIMER_ONTIME 0xFFFF0000 204 #define BCMA_CC_GPIOTIMER_ONTIME_SHIFT 16 205 #define BCMA_CC_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */ 206 #define BCMA_CC_CLOCK_N 0x0090 207 #define BCMA_CC_CLOCK_SB 0x0094 208 #define BCMA_CC_CLOCK_PCI 0x0098 209 #define BCMA_CC_CLOCK_M2 0x009C 210 #define BCMA_CC_CLOCK_MIPS 0x00A0 211 #define BCMA_CC_CLKDIV 0x00A4 /* Rev >= 3 only */ 212 #define BCMA_CC_CLKDIV_SFLASH 0x0F000000 213 #define BCMA_CC_CLKDIV_SFLASH_SHIFT 24 214 #define BCMA_CC_CLKDIV_OTP 0x000F0000 215 #define BCMA_CC_CLKDIV_OTP_SHIFT 16 216 #define BCMA_CC_CLKDIV_JTAG 0x00000F00 217 #define BCMA_CC_CLKDIV_JTAG_SHIFT 8 218 #define BCMA_CC_CLKDIV_UART 0x000000FF 219 #define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */ 220 #define BCMA_CC_CAP_EXT_SECI_PRESENT 0x00000001 221 #define BCMA_CC_CAP_EXT_GSIO_PRESENT 0x00000002 222 #define BCMA_CC_CAP_EXT_GCI_PRESENT 0x00000004 223 #define BCMA_CC_CAP_EXT_SECI_PUART_PRESENT 0x00000008 /* UART present */ 224 #define BCMA_CC_CAP_EXT_AOB_PRESENT 0x00000040 225 #define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */ 226 #define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */ 227 #define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */ 228 #define BCMA_CC_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */ 229 #define BCMA_CC_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */ 230 #define BCMA_CC_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */ 231 #define BCMA_CC_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */ 232 #define BCMA_CC_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ 233 #define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */ 234 #define BCMA_CC_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */ 235 #define BCMA_CC_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */ 236 #define BCMA_CC_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */ 237 #define BCMA_CC_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ 238 #define BCMA_CC_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ 239 #define BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT 16 240 #define BCMA_CC_SYSCLKCTL 0x00C0 /* Rev >= 3 only */ 241 #define BCMA_CC_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */ 242 #define BCMA_CC_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */ 243 #define BCMA_CC_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */ 244 #define BCMA_CC_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */ 245 #define BCMA_CC_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */ 246 #define BCMA_CC_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */ 247 #define BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT 16 248 #define BCMA_CC_CLKSTSTR 0x00C4 /* Rev >= 3 only */ 249 #define BCMA_CC_EROM 0x00FC 250 #define BCMA_CC_PCMCIA_CFG 0x0100 251 #define BCMA_CC_PCMCIA_MEMWAIT 0x0104 252 #define BCMA_CC_PCMCIA_ATTRWAIT 0x0108 253 #define BCMA_CC_PCMCIA_IOWAIT 0x010C 254 #define BCMA_CC_IDE_CFG 0x0110 255 #define BCMA_CC_IDE_MEMWAIT 0x0114 256 #define BCMA_CC_IDE_ATTRWAIT 0x0118 257 #define BCMA_CC_IDE_IOWAIT 0x011C 258 #define BCMA_CC_PROG_CFG 0x0120 259 #define BCMA_CC_PROG_WAITCNT 0x0124 260 #define BCMA_CC_FLASH_CFG 0x0128 261 #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ 262 #define BCMA_CC_FLASH_WAITCNT 0x012C 263 #define BCMA_CC_SROM_CONTROL 0x0190 264 #define BCMA_CC_SROM_CONTROL_START 0x80000000 265 #define BCMA_CC_SROM_CONTROL_BUSY 0x80000000 266 #define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000 267 #define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000 268 #define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000 269 #define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000 270 #define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000 271 #define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010 272 #define BCMA_CC_SROM_CONTROL_LOCK 0x00000008 273 #define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006 274 #define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000 275 #define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002 276 #define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004 277 #define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1 278 #define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001 279 /* Block 0x140 - 0x190 registers are chipset specific */ 280 #define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */ 281 #define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff 282 #define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */ 283 #define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */ 284 #define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */ 285 #define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */ 286 #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0 287 #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */ 288 #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */ 289 #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */ 290 #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */ 291 #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */ 292 #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */ 293 #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */ 294 /* NAND flash registers for BCM4706 (corerev = 31) */ 295 #define BCMA_CC_NFLASH_CTL 0x01A0 296 #define BCMA_CC_NFLASH_CTL_ERR 0x08000000 297 #define BCMA_CC_NFLASH_CONF 0x01A4 298 #define BCMA_CC_NFLASH_COL_ADDR 0x01A8 299 #define BCMA_CC_NFLASH_ROW_ADDR 0x01AC 300 #define BCMA_CC_NFLASH_DATA 0x01B0 301 #define BCMA_CC_NFLASH_WAITCNT0 0x01B4 302 /* 0x1E0 is defined as shared BCMA_CLKCTLST */ 303 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ 304 #define BCMA_CC_UART0_DATA 0x0300 305 #define BCMA_CC_UART0_IMR 0x0304 306 #define BCMA_CC_UART0_FCR 0x0308 307 #define BCMA_CC_UART0_LCR 0x030C 308 #define BCMA_CC_UART0_MCR 0x0310 309 #define BCMA_CC_UART0_LSR 0x0314 310 #define BCMA_CC_UART0_MSR 0x0318 311 #define BCMA_CC_UART0_SCRATCH 0x031C 312 #define BCMA_CC_UART1_DATA 0x0400 313 #define BCMA_CC_UART1_IMR 0x0404 314 #define BCMA_CC_UART1_FCR 0x0408 315 #define BCMA_CC_UART1_LCR 0x040C 316 #define BCMA_CC_UART1_MCR 0x0410 317 #define BCMA_CC_UART1_LSR 0x0414 318 #define BCMA_CC_UART1_MSR 0x0418 319 #define BCMA_CC_UART1_SCRATCH 0x041C 320 /* PMU registers (rev >= 20) */ 321 #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */ 322 #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */ 323 #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16 324 #define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */ 325 #define BCMA_CC_PMU_CTL_RES_SHIFT 13 326 #define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */ 327 #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400 328 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */ 329 #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */ 330 #define BCMA_CC_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */ 331 #define BCMA_CC_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */ 332 #define BCMA_CC_PMU_CTL_XTALFREQ_SHIFT 2 333 #define BCMA_CC_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */ 334 #define BCMA_CC_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */ 335 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */ 336 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */ 337 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */ 338 #define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100 339 #define BCMA_CC_PMU_STAT_WDRESET 0x00000080 340 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */ 341 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */ 342 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */ 343 #define BCMA_CC_PMU_STAT_HAVEHT 0x00000004 /* HT available */ 344 #define BCMA_CC_PMU_STAT_RESINIT 0x00000003 /* Res init */ 345 #define BCMA_CC_PMU_RES_STAT 0x060C /* PMU res status */ 346 #define BCMA_CC_PMU_RES_PEND 0x0610 /* PMU res pending */ 347 #define BCMA_CC_PMU_TIMER 0x0614 /* PMU timer */ 348 #define BCMA_CC_PMU_MINRES_MSK 0x0618 /* PMU min res mask */ 349 #define BCMA_CC_PMU_MAXRES_MSK 0x061C /* PMU max res mask */ 350 #define BCMA_CC_PMU_RES_TABSEL 0x0620 /* PMU res table sel */ 351 #define BCMA_CC_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */ 352 #define BCMA_CC_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */ 353 #define BCMA_CC_PMU_RES_TIMER 0x062C /* PMU res timer */ 354 #define BCMA_CC_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */ 355 #define BCMA_CC_PMU_WATCHDOG 0x0634 /* PMU watchdog */ 356 #define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */ 357 #define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */ 358 #define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */ 359 #define BCMA_CC_PMU_CHIPCTL_ADDR 0x0650 360 #define BCMA_CC_PMU_CHIPCTL_DATA 0x0654 361 #define BCMA_CC_PMU_REGCTL_ADDR 0x0658 362 #define BCMA_CC_PMU_REGCTL_DATA 0x065C 363 #define BCMA_CC_PMU_PLLCTL_ADDR 0x0660 364 #define BCMA_CC_PMU_PLLCTL_DATA 0x0664 365 #define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */ 366 #define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */ 367 #define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF 368 #define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000 369 #define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31 370 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */ 371 /* NAND flash MLC controller registers (corerev >= 38) */ 372 #define BCMA_CC_NAND_REVISION 0x0C00 373 #define BCMA_CC_NAND_CMD_START 0x0C04 374 #define BCMA_CC_NAND_CMD_ADDR_X 0x0C08 375 #define BCMA_CC_NAND_CMD_ADDR 0x0C0C 376 #define BCMA_CC_NAND_CMD_END_ADDR 0x0C10 377 #define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14 378 #define BCMA_CC_NAND_CS_NAND_XOR 0x0C18 379 #define BCMA_CC_NAND_SPARE_RD0 0x0C20 380 #define BCMA_CC_NAND_SPARE_RD4 0x0C24 381 #define BCMA_CC_NAND_SPARE_RD8 0x0C28 382 #define BCMA_CC_NAND_SPARE_RD12 0x0C2C 383 #define BCMA_CC_NAND_SPARE_WR0 0x0C30 384 #define BCMA_CC_NAND_SPARE_WR4 0x0C34 385 #define BCMA_CC_NAND_SPARE_WR8 0x0C38 386 #define BCMA_CC_NAND_SPARE_WR12 0x0C3C 387 #define BCMA_CC_NAND_ACC_CONTROL 0x0C40 388 #define BCMA_CC_NAND_CONFIG 0x0C48 389 #define BCMA_CC_NAND_TIMING_1 0x0C50 390 #define BCMA_CC_NAND_TIMING_2 0x0C54 391 #define BCMA_CC_NAND_SEMAPHORE 0x0C58 392 #define BCMA_CC_NAND_DEVID 0x0C60 393 #define BCMA_CC_NAND_DEVID_X 0x0C64 394 #define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68 395 #define BCMA_CC_NAND_INTFC_STATUS 0x0C6C 396 #define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70 397 #define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74 398 #define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78 399 #define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C 400 #define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80 401 #define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84 402 #define BCMA_CC_NAND_READ_ADDR_X 0x0C90 403 #define BCMA_CC_NAND_READ_ADDR 0x0C94 404 #define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98 405 #define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C 406 #define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0 407 #define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4 408 #define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8 409 #define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC 410 #define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0 411 #define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4 412 #define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0 413 #define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0 414 #define BCMA_CC_NAND_CONFIG_CS1 0x0CD4 415 #define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8 416 #define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC 417 #define BCMA_CC_NAND_SPARE_RD16 0x0D30 418 #define BCMA_CC_NAND_SPARE_RD20 0x0D34 419 #define BCMA_CC_NAND_SPARE_RD24 0x0D38 420 #define BCMA_CC_NAND_SPARE_RD28 0x0D3C 421 #define BCMA_CC_NAND_CACHE_ADDR 0x0D40 422 #define BCMA_CC_NAND_CACHE_DATA 0x0D44 423 #define BCMA_CC_NAND_CTRL_CONFIG 0x0D48 424 #define BCMA_CC_NAND_CTRL_STATUS 0x0D4C 425 426 /* Divider allocation in 4716/47162/5356 */ 427 #define BCMA_CC_PMU5_MAINPLL_CPU 1 428 #define BCMA_CC_PMU5_MAINPLL_MEM 2 429 #define BCMA_CC_PMU5_MAINPLL_SSB 3 430 431 /* PLL usage in 4716/47162 */ 432 #define BCMA_CC_PMU4716_MAINPLL_PLL0 12 433 434 /* PLL usage in 5356/5357 */ 435 #define BCMA_CC_PMU5356_MAINPLL_PLL0 0 436 #define BCMA_CC_PMU5357_MAINPLL_PLL0 0 437 438 /* 4706 PMU */ 439 #define BCMA_CC_PMU4706_MAINPLL_PLL0 0 440 #define BCMA_CC_PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */ 441 #define BCMA_CC_PMU6_4706_PROC_P2DIV_MASK 0x000f0000 442 #define BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT 16 443 #define BCMA_CC_PMU6_4706_PROC_P1DIV_MASK 0x0000f000 444 #define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT 12 445 #define BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8 446 #define BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT 3 447 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007 448 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0 449 450 /* PMU rev 15 */ 451 #define BCMA_CC_PMU15_PLL_PLLCTL0 0 452 #define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003 453 #define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0 454 #define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC 455 #define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2 456 #define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000 457 #define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22 458 #define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000 459 #define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24 460 #define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000 461 #define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27 462 #define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000 463 #define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30 464 #define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000 465 #define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31 466 467 /* ALP clock on pre-PMU chips */ 468 #define BCMA_CC_PMU_ALP_CLOCK 20000000 469 /* HT clock for systems with PMU-enabled chipcommon */ 470 #define BCMA_CC_PMU_HT_CLOCK 80000000 471 472 /* PMU rev 5 (& 6) */ 473 #define BCMA_CC_PPL_P1P2_OFF 0 474 #define BCMA_CC_PPL_P1_MASK 0x0f000000 475 #define BCMA_CC_PPL_P1_SHIFT 24 476 #define BCMA_CC_PPL_P2_MASK 0x00f00000 477 #define BCMA_CC_PPL_P2_SHIFT 20 478 #define BCMA_CC_PPL_M14_OFF 1 479 #define BCMA_CC_PPL_MDIV_MASK 0x000000ff 480 #define BCMA_CC_PPL_MDIV_WIDTH 8 481 #define BCMA_CC_PPL_NM5_OFF 2 482 #define BCMA_CC_PPL_NDIV_MASK 0xfff00000 483 #define BCMA_CC_PPL_NDIV_SHIFT 20 484 #define BCMA_CC_PPL_FMAB_OFF 3 485 #define BCMA_CC_PPL_MRAT_MASK 0xf0000000 486 #define BCMA_CC_PPL_MRAT_SHIFT 28 487 #define BCMA_CC_PPL_ABRAT_MASK 0x08000000 488 #define BCMA_CC_PPL_ABRAT_SHIFT 27 489 #define BCMA_CC_PPL_FDIV_MASK 0x07ffffff 490 #define BCMA_CC_PPL_PLLCTL_OFF 4 491 #define BCMA_CC_PPL_PCHI_OFF 5 492 #define BCMA_CC_PPL_PCHI_MASK 0x0000003f 493 494 #define BCMA_CC_PMU_PLL_CTL0 0 495 #define BCMA_CC_PMU_PLL_CTL1 1 496 #define BCMA_CC_PMU_PLL_CTL2 2 497 #define BCMA_CC_PMU_PLL_CTL3 3 498 #define BCMA_CC_PMU_PLL_CTL4 4 499 #define BCMA_CC_PMU_PLL_CTL5 5 500 501 #define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 502 #define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT 20 503 504 #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 505 #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 506 507 #define BCMA_CCB_MII_MNG_CTL 0x0000 508 #define BCMA_CCB_MII_MNG_CMD_DATA 0x0004 509 510 /* BCM4331 ChipControl numbers. */ 511 #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */ 512 #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */ 513 #define BCMA_CHIPCTL_4331_EXT_LNA BIT(2) /* 0 disable */ 514 #define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */ 515 #define BCMA_CHIPCTL_4331_EXTPA_EN BIT(4) /* 0 ext pa disable, 1 ext pa enabled */ 516 #define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS BIT(5) /* set drive out GPIO_CLK on sprom_cs pin */ 517 #define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS BIT(6) /* use sprom_cs pin as PCIE mdio interface */ 518 #define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5 BIT(7) /* aband extpa will be at gpio2/5 and sprom_dout */ 519 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN BIT(8) /* override core control on pipe_AuxClkEnable */ 520 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */ 521 #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */ 522 #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */ 523 #define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */ 524 #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */ 525 #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */ 526 527 /* 43224 chip-specific ChipControl register bits */ 528 #define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */ 529 #define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ 530 #define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ 531 532 /* 4313 Chip specific ChipControl register bits */ 533 #define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ 534 535 /* BCM5357 ChipControl register bits */ 536 #define BCMA_CHIPCTL_5357_EXTPA BIT(14) 537 #define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15) 538 #define BCMA_CHIPCTL_5357_NFLASH BIT(16) 539 #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18) 540 #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19) 541 542 #define BCMA_RES_4314_LPLDO_PU BIT(0) 543 #define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1) 544 #define BCMA_RES_4314_PMU_BG_PU BIT(2) 545 #define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3) 546 #define BCMA_RES_4314_CBUCK_PFM_PU BIT(4) 547 #define BCMA_RES_4314_CLDO_PU BIT(5) 548 #define BCMA_RES_4314_LPLDO2_LVM BIT(6) 549 #define BCMA_RES_4314_WL_PMU_PU BIT(7) 550 #define BCMA_RES_4314_LNLDO_PU BIT(8) 551 #define BCMA_RES_4314_LDO3P3_PU BIT(9) 552 #define BCMA_RES_4314_OTP_PU BIT(10) 553 #define BCMA_RES_4314_XTAL_PU BIT(11) 554 #define BCMA_RES_4314_WL_PWRSW_PU BIT(12) 555 #define BCMA_RES_4314_LQ_AVAIL BIT(13) 556 #define BCMA_RES_4314_LOGIC_RET BIT(14) 557 #define BCMA_RES_4314_MEM_SLEEP BIT(15) 558 #define BCMA_RES_4314_MACPHY_RET BIT(16) 559 #define BCMA_RES_4314_WL_CORE_READY BIT(17) 560 #define BCMA_RES_4314_ILP_REQ BIT(18) 561 #define BCMA_RES_4314_ALP_AVAIL BIT(19) 562 #define BCMA_RES_4314_MISC_PWRSW_PU BIT(20) 563 #define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21) 564 #define BCMA_RES_4314_RX_PWRSW_PU BIT(22) 565 #define BCMA_RES_4314_RADIO_PU BIT(23) 566 #define BCMA_RES_4314_VCO_LDO_PU BIT(24) 567 #define BCMA_RES_4314_AFE_LDO_PU BIT(25) 568 #define BCMA_RES_4314_RX_LDO_PU BIT(26) 569 #define BCMA_RES_4314_TX_LDO_PU BIT(27) 570 #define BCMA_RES_4314_HT_AVAIL BIT(28) 571 #define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29) 572 573 /* Data for the PMU, if available. 574 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU) 575 */ 576 struct bcma_chipcommon_pmu { 577 struct bcma_device *core; /* Can be separated core or just ChipCommon one */ 578 u8 rev; /* PMU revision */ 579 u32 crystalfreq; /* The active crystal frequency (in kHz) */ 580 }; 581 582 #ifdef CONFIG_BCMA_PFLASH 583 struct bcma_pflash { 584 bool present; 585 }; 586 #endif 587 588 #ifdef CONFIG_BCMA_SFLASH 589 struct mtd_info; 590 591 struct bcma_sflash { 592 bool present; 593 u32 blocksize; 594 u16 numblocks; 595 u32 size; 596 }; 597 #endif 598 599 #ifdef CONFIG_BCMA_NFLASH 600 struct bcma_nflash { 601 bool present; 602 bool boot; /* This is the flash the SoC boots from */ 603 }; 604 #endif 605 606 #ifdef CONFIG_BCMA_DRIVER_MIPS 607 struct bcma_serial_port { 608 void *regs; 609 unsigned long clockspeed; 610 unsigned int irq; 611 unsigned int baud_base; 612 unsigned int reg_shift; 613 }; 614 #endif /* CONFIG_BCMA_DRIVER_MIPS */ 615 616 struct bcma_drv_cc { 617 struct bcma_device *core; 618 u32 status; 619 u32 capabilities; 620 u32 capabilities_ext; 621 u8 setup_done:1; 622 u8 early_setup_done:1; 623 /* Fast Powerup Delay constant */ 624 u16 fast_pwrup_delay; 625 struct bcma_chipcommon_pmu pmu; 626 #ifdef CONFIG_BCMA_PFLASH 627 struct bcma_pflash pflash; 628 #endif 629 #ifdef CONFIG_BCMA_SFLASH 630 struct bcma_sflash sflash; 631 #endif 632 #ifdef CONFIG_BCMA_NFLASH 633 struct bcma_nflash nflash; 634 #endif 635 636 #ifdef CONFIG_BCMA_DRIVER_MIPS 637 int nr_serial_ports; 638 struct bcma_serial_port serial_ports[4]; 639 #endif /* CONFIG_BCMA_DRIVER_MIPS */ 640 u32 ticks_per_ms; 641 struct platform_device *watchdog; 642 643 /* Lock for GPIO register access. */ 644 spinlock_t gpio_lock; 645 #ifdef CONFIG_BCMA_DRIVER_GPIO 646 struct gpio_chip gpio; 647 #endif 648 }; 649 650 struct bcma_drv_cc_b { 651 struct bcma_device *core; 652 u8 setup_done:1; 653 void __iomem *mii; 654 }; 655 656 /* Register access */ 657 #define bcma_cc_read32(cc, offset) \ 658 bcma_read32((cc)->core, offset) 659 #define bcma_cc_write32(cc, offset, val) \ 660 bcma_write32((cc)->core, offset, val) 661 662 #define bcma_cc_mask32(cc, offset, mask) \ 663 bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask)) 664 #define bcma_cc_set32(cc, offset, set) \ 665 bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) | (set)) 666 #define bcma_cc_maskset32(cc, offset, mask, set) \ 667 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set)) 668 669 /* PMU registers access */ 670 #define bcma_pmu_read32(cc, offset) \ 671 bcma_read32((cc)->pmu.core, offset) 672 #define bcma_pmu_write32(cc, offset, val) \ 673 bcma_write32((cc)->pmu.core, offset, val) 674 675 #define bcma_pmu_mask32(cc, offset, mask) \ 676 bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) & (mask)) 677 #define bcma_pmu_set32(cc, offset, set) \ 678 bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) | (set)) 679 #define bcma_pmu_maskset32(cc, offset, mask, set) \ 680 bcma_pmu_write32(cc, offset, (bcma_pmu_read32(cc, offset) & (mask)) | (set)) 681 682 extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); 683 684 extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc); 685 686 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); 687 688 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask); 689 690 /* Chipcommon GPIO pin access. */ 691 u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask); 692 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value); 693 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value); 694 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value); 695 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value); 696 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value); 697 u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value); 698 u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value); 699 700 /* PMU support */ 701 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, 702 u32 value); 703 extern void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, 704 u32 mask, u32 set); 705 extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc, 706 u32 offset, u32 mask, u32 set); 707 extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, 708 u32 offset, u32 mask, u32 set); 709 extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid); 710 711 extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc); 712 713 void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value); 714 715 #endif /* LINUX_BCMA_DRIVER_CC_H_ */ 716