1 /* 2 * linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver 3 * 4 * Copyright (C) 2005 ARM Ltd 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * pl08x information required by platform code 12 * 13 * Please credit ARM.com 14 * Documentation: ARM DDI 0196D 15 */ 16 17 #ifndef AMBA_PL08X_H 18 #define AMBA_PL08X_H 19 20 /* We need sizes of structs from this header */ 21 #include <linux/dmaengine.h> 22 #include <linux/interrupt.h> 23 24 struct pl08x_lli; 25 struct pl08x_driver_data; 26 27 /* Bitmasks for selecting AHB ports for DMA transfers */ 28 enum { 29 PL08X_AHB1 = (1 << 0), 30 PL08X_AHB2 = (1 << 1) 31 }; 32 33 /** 34 * struct pl08x_channel_data - data structure to pass info between 35 * platform and PL08x driver regarding channel configuration 36 * @bus_id: name of this device channel, not just a device name since 37 * devices may have more than one channel e.g. "foo_tx" 38 * @min_signal: the minimum DMA signal number to be muxed in for this 39 * channel (for platforms supporting muxed signals). If you have 40 * static assignments, make sure this is set to the assigned signal 41 * number, PL08x have 16 possible signals in number 0 thru 15 so 42 * when these are not enough they often get muxed (in hardware) 43 * disabling simultaneous use of the same channel for two devices. 44 * @max_signal: the maximum DMA signal number to be muxed in for 45 * the channel. Set to the same as min_signal for 46 * devices with static assignments 47 * @muxval: a number usually used to poke into some mux regiser to 48 * mux in the signal to this channel 49 * @cctl_opt: default options for the channel control register 50 * @addr: source/target address in physical memory for this DMA channel, 51 * can be the address of a FIFO register for burst requests for example. 52 * This can be left undefined if the PrimeCell API is used for configuring 53 * this. 54 * @circular_buffer: whether the buffer passed in is circular and 55 * shall simply be looped round round (like a record baby round 56 * round round round) 57 * @single: the device connected to this channel will request single DMA 58 * transfers, not bursts. (Bursts are default.) 59 * @periph_buses: the device connected to this channel is accessible via 60 * these buses (use PL08X_AHB1 | PL08X_AHB2). 61 */ 62 struct pl08x_channel_data { 63 char *bus_id; 64 int min_signal; 65 int max_signal; 66 u32 muxval; 67 u32 cctl; 68 dma_addr_t addr; 69 bool circular_buffer; 70 bool single; 71 u8 periph_buses; 72 }; 73 74 /** 75 * Struct pl08x_bus_data - information of source or destination 76 * busses for a transfer 77 * @addr: current address 78 * @maxwidth: the maximum width of a transfer on this bus 79 * @buswidth: the width of this bus in bytes: 1, 2 or 4 80 */ 81 struct pl08x_bus_data { 82 dma_addr_t addr; 83 u8 maxwidth; 84 u8 buswidth; 85 }; 86 87 /** 88 * struct pl08x_phy_chan - holder for the physical channels 89 * @id: physical index to this channel 90 * @lock: a lock to use when altering an instance of this struct 91 * @signal: the physical signal (aka channel) serving this physical channel 92 * right now 93 * @serving: the virtual channel currently being served by this physical 94 * channel 95 * @locked: channel unavailable for the system, e.g. dedicated to secure 96 * world 97 */ 98 struct pl08x_phy_chan { 99 unsigned int id; 100 void __iomem *base; 101 spinlock_t lock; 102 int signal; 103 struct pl08x_dma_chan *serving; 104 bool locked; 105 }; 106 107 /** 108 * struct pl08x_sg - structure containing data per sg 109 * @src_addr: src address of sg 110 * @dst_addr: dst address of sg 111 * @len: transfer len in bytes 112 * @node: node for txd's dsg_list 113 */ 114 struct pl08x_sg { 115 dma_addr_t src_addr; 116 dma_addr_t dst_addr; 117 size_t len; 118 struct list_head node; 119 }; 120 121 /** 122 * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor 123 * @tx: async tx descriptor 124 * @node: node for txd list for channels 125 * @dsg_list: list of children sg's 126 * @direction: direction of transfer 127 * @llis_bus: DMA memory address (physical) start for the LLIs 128 * @llis_va: virtual memory address start for the LLIs 129 * @cctl: control reg values for current txd 130 * @ccfg: config reg values for current txd 131 */ 132 struct pl08x_txd { 133 struct dma_async_tx_descriptor tx; 134 struct list_head node; 135 struct list_head dsg_list; 136 enum dma_transfer_direction direction; 137 dma_addr_t llis_bus; 138 struct pl08x_lli *llis_va; 139 /* Default cctl value for LLIs */ 140 u32 cctl; 141 /* 142 * Settings to be put into the physical channel when we 143 * trigger this txd. Other registers are in llis_va[0]. 144 */ 145 u32 ccfg; 146 }; 147 148 /** 149 * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel 150 * states 151 * @PL08X_CHAN_IDLE: the channel is idle 152 * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport 153 * channel and is running a transfer on it 154 * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport 155 * channel, but the transfer is currently paused 156 * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport 157 * channel to become available (only pertains to memcpy channels) 158 */ 159 enum pl08x_dma_chan_state { 160 PL08X_CHAN_IDLE, 161 PL08X_CHAN_RUNNING, 162 PL08X_CHAN_PAUSED, 163 PL08X_CHAN_WAITING, 164 }; 165 166 /** 167 * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel 168 * @chan: wrappped abstract channel 169 * @phychan: the physical channel utilized by this channel, if there is one 170 * @phychan_hold: if non-zero, hold on to the physical channel even if we 171 * have no pending entries 172 * @tasklet: tasklet scheduled by the IRQ to handle actual work etc 173 * @name: name of channel 174 * @cd: channel platform data 175 * @runtime_addr: address for RX/TX according to the runtime config 176 * @runtime_direction: current direction of this channel according to 177 * runtime config 178 * @pend_list: queued transactions pending on this channel 179 * @at: active transaction on this channel 180 * @lock: a lock for this channel data 181 * @host: a pointer to the host (internal use) 182 * @state: whether the channel is idle, paused, running etc 183 * @slave: whether this channel is a device (slave) or for memcpy 184 * @device_fc: Flow Controller Settings for ccfg register. Only valid for slave 185 * channels. Fill with 'true' if peripheral should be flow controller. Direction 186 * will be selected at Runtime. 187 * @waiting: a TX descriptor on this channel which is waiting for a physical 188 * channel to become available 189 */ 190 struct pl08x_dma_chan { 191 struct dma_chan chan; 192 struct pl08x_phy_chan *phychan; 193 int phychan_hold; 194 struct tasklet_struct tasklet; 195 char *name; 196 const struct pl08x_channel_data *cd; 197 dma_addr_t src_addr; 198 dma_addr_t dst_addr; 199 u32 src_cctl; 200 u32 dst_cctl; 201 enum dma_transfer_direction runtime_direction; 202 struct list_head pend_list; 203 struct pl08x_txd *at; 204 spinlock_t lock; 205 struct pl08x_driver_data *host; 206 enum pl08x_dma_chan_state state; 207 bool slave; 208 bool device_fc; 209 struct pl08x_txd *waiting; 210 }; 211 212 /** 213 * struct pl08x_platform_data - the platform configuration for the PL08x 214 * PrimeCells. 215 * @slave_channels: the channels defined for the different devices on the 216 * platform, all inclusive, including multiplexed channels. The available 217 * physical channels will be multiplexed around these signals as they are 218 * requested, just enumerate all possible channels. 219 * @get_signal: request a physical signal to be used for a DMA transfer 220 * immediately: if there is some multiplexing or similar blocking the use 221 * of the channel the transfer can be denied by returning less than zero, 222 * else it returns the allocated signal number 223 * @put_signal: indicate to the platform that this physical signal is not 224 * running any DMA transfer and multiplexing can be recycled 225 * @lli_buses: buses which LLIs can be fetched from: PL08X_AHB1 | PL08X_AHB2 226 * @mem_buses: buses which memory can be accessed from: PL08X_AHB1 | PL08X_AHB2 227 */ 228 struct pl08x_platform_data { 229 const struct pl08x_channel_data *slave_channels; 230 unsigned int num_slave_channels; 231 struct pl08x_channel_data memcpy_channel; 232 int (*get_signal)(struct pl08x_dma_chan *); 233 void (*put_signal)(struct pl08x_dma_chan *); 234 u8 lli_buses; 235 u8 mem_buses; 236 }; 237 238 #ifdef CONFIG_AMBA_PL08X 239 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id); 240 #else 241 static inline bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) 242 { 243 return false; 244 } 245 #endif 246 247 #endif /* AMBA_PL08X_H */ 248