1 /* 2 * include/linux/amba/pl022.h 3 * 4 * Copyright (C) 2008-2009 ST-Ericsson AB 5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 6 * 7 * Author: Linus Walleij <[email protected]> 8 * 9 * Initial version inspired by: 10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 11 * Initial adoption to PL022 by: 12 * Sachin Verma <[email protected]> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 */ 24 25 #ifndef _SSP_PL022_H 26 #define _SSP_PL022_H 27 28 #include <linux/device.h> 29 30 /** 31 * whether SSP is in loopback mode or not 32 */ 33 enum ssp_loopback { 34 LOOPBACK_DISABLED, 35 LOOPBACK_ENABLED 36 }; 37 38 /** 39 * enum ssp_interface - interfaces allowed for this SSP Controller 40 * @SSP_INTERFACE_MOTOROLA_SPI: Motorola Interface 41 * @SSP_INTERFACE_TI_SYNC_SERIAL: Texas Instrument Synchronous Serial 42 * interface 43 * @SSP_INTERFACE_NATIONAL_MICROWIRE: National Semiconductor Microwire 44 * interface 45 * @SSP_INTERFACE_UNIDIRECTIONAL: Unidirectional interface (STn8810 46 * &STn8815 only) 47 */ 48 enum ssp_interface { 49 SSP_INTERFACE_MOTOROLA_SPI, 50 SSP_INTERFACE_TI_SYNC_SERIAL, 51 SSP_INTERFACE_NATIONAL_MICROWIRE, 52 SSP_INTERFACE_UNIDIRECTIONAL 53 }; 54 55 /** 56 * enum ssp_hierarchy - whether SSP is configured as Master or Slave 57 */ 58 enum ssp_hierarchy { 59 SSP_MASTER, 60 SSP_SLAVE 61 }; 62 63 /** 64 * enum ssp_clock_params - clock parameters, to set SSP clock at a 65 * desired freq 66 */ 67 struct ssp_clock_params { 68 u8 cpsdvsr; /* value from 2 to 254 (even only!) */ 69 u8 scr; /* value from 0 to 255 */ 70 }; 71 72 /** 73 * enum ssp_rx_endian - endianess of Rx FIFO Data 74 */ 75 enum ssp_rx_endian { 76 SSP_RX_MSB, 77 SSP_RX_LSB 78 }; 79 80 /** 81 * enum ssp_tx_endian - endianess of Tx FIFO Data 82 */ 83 enum ssp_tx_endian { 84 SSP_TX_MSB, 85 SSP_TX_LSB 86 }; 87 88 /** 89 * enum ssp_data_size - number of bits in one data element 90 */ 91 enum ssp_data_size { 92 SSP_DATA_BITS_4 = 0x03, SSP_DATA_BITS_5, SSP_DATA_BITS_6, 93 SSP_DATA_BITS_7, SSP_DATA_BITS_8, SSP_DATA_BITS_9, 94 SSP_DATA_BITS_10, SSP_DATA_BITS_11, SSP_DATA_BITS_12, 95 SSP_DATA_BITS_13, SSP_DATA_BITS_14, SSP_DATA_BITS_15, 96 SSP_DATA_BITS_16, SSP_DATA_BITS_17, SSP_DATA_BITS_18, 97 SSP_DATA_BITS_19, SSP_DATA_BITS_20, SSP_DATA_BITS_21, 98 SSP_DATA_BITS_22, SSP_DATA_BITS_23, SSP_DATA_BITS_24, 99 SSP_DATA_BITS_25, SSP_DATA_BITS_26, SSP_DATA_BITS_27, 100 SSP_DATA_BITS_28, SSP_DATA_BITS_29, SSP_DATA_BITS_30, 101 SSP_DATA_BITS_31, SSP_DATA_BITS_32 102 }; 103 104 /** 105 * enum ssp_mode - SSP mode of operation (Communication modes) 106 */ 107 enum ssp_mode { 108 INTERRUPT_TRANSFER, 109 POLLING_TRANSFER, 110 DMA_TRANSFER 111 }; 112 113 /** 114 * enum ssp_rx_level_trig - receive FIFO watermark level which triggers 115 * IT: Interrupt fires when _N_ or more elements in RX FIFO. 116 */ 117 enum ssp_rx_level_trig { 118 SSP_RX_1_OR_MORE_ELEM, 119 SSP_RX_4_OR_MORE_ELEM, 120 SSP_RX_8_OR_MORE_ELEM, 121 SSP_RX_16_OR_MORE_ELEM, 122 SSP_RX_32_OR_MORE_ELEM 123 }; 124 125 /** 126 * Transmit FIFO watermark level which triggers (IT Interrupt fires 127 * when _N_ or more empty locations in TX FIFO) 128 */ 129 enum ssp_tx_level_trig { 130 SSP_TX_1_OR_MORE_EMPTY_LOC, 131 SSP_TX_4_OR_MORE_EMPTY_LOC, 132 SSP_TX_8_OR_MORE_EMPTY_LOC, 133 SSP_TX_16_OR_MORE_EMPTY_LOC, 134 SSP_TX_32_OR_MORE_EMPTY_LOC 135 }; 136 137 /** 138 * enum SPI Clock Phase - clock phase (Motorola SPI interface only) 139 * @SSP_CLK_FIRST_EDGE: Receive data on first edge transition (actual direction depends on polarity) 140 * @SSP_CLK_SECOND_EDGE: Receive data on second edge transition (actual direction depends on polarity) 141 */ 142 enum ssp_spi_clk_phase { 143 SSP_CLK_FIRST_EDGE, 144 SSP_CLK_SECOND_EDGE 145 }; 146 147 /** 148 * enum SPI Clock Polarity - clock polarity (Motorola SPI interface only) 149 * @SSP_CLK_POL_IDLE_LOW: Low inactive level 150 * @SSP_CLK_POL_IDLE_HIGH: High inactive level 151 */ 152 enum ssp_spi_clk_pol { 153 SSP_CLK_POL_IDLE_LOW, 154 SSP_CLK_POL_IDLE_HIGH 155 }; 156 157 /** 158 * Microwire Conrol Lengths Command size in microwire format 159 */ 160 enum ssp_microwire_ctrl_len { 161 SSP_BITS_4 = 0x03, SSP_BITS_5, SSP_BITS_6, 162 SSP_BITS_7, SSP_BITS_8, SSP_BITS_9, 163 SSP_BITS_10, SSP_BITS_11, SSP_BITS_12, 164 SSP_BITS_13, SSP_BITS_14, SSP_BITS_15, 165 SSP_BITS_16, SSP_BITS_17, SSP_BITS_18, 166 SSP_BITS_19, SSP_BITS_20, SSP_BITS_21, 167 SSP_BITS_22, SSP_BITS_23, SSP_BITS_24, 168 SSP_BITS_25, SSP_BITS_26, SSP_BITS_27, 169 SSP_BITS_28, SSP_BITS_29, SSP_BITS_30, 170 SSP_BITS_31, SSP_BITS_32 171 }; 172 173 /** 174 * enum Microwire Wait State 175 * @SSP_MWIRE_WAIT_ZERO: No wait state inserted after last command bit 176 * @SSP_MWIRE_WAIT_ONE: One wait state inserted after last command bit 177 */ 178 enum ssp_microwire_wait_state { 179 SSP_MWIRE_WAIT_ZERO, 180 SSP_MWIRE_WAIT_ONE 181 }; 182 183 /** 184 * enum Microwire - whether Full/Half Duplex 185 * @SSP_MICROWIRE_CHANNEL_FULL_DUPLEX: SSPTXD becomes bi-directional, 186 * SSPRXD not used 187 * @SSP_MICROWIRE_CHANNEL_HALF_DUPLEX: SSPTXD is an output, SSPRXD is 188 * an input. 189 */ 190 enum ssp_duplex { 191 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 192 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX 193 }; 194 195 /** 196 * CHIP select/deselect commands 197 */ 198 enum ssp_chip_select { 199 SSP_CHIP_SELECT, 200 SSP_CHIP_DESELECT 201 }; 202 203 204 /** 205 * struct pl022_ssp_master - device.platform_data for SPI controller devices. 206 * @num_chipselect: chipselects are used to distinguish individual 207 * SPI slaves, and are numbered from zero to num_chipselects - 1. 208 * each slave has a chipselect signal, but it's common that not 209 * every chipselect is connected to a slave. 210 * @enable_dma: if true enables DMA driven transfers. 211 */ 212 struct pl022_ssp_controller { 213 u16 bus_id; 214 u8 num_chipselect; 215 u8 enable_dma:1; 216 }; 217 218 /** 219 * struct ssp_config_chip - spi_board_info.controller_data for SPI 220 * slave devices, copied to spi_device.controller_data. 221 * 222 * @lbm: used for test purpose to internally connect RX and TX 223 * @iface: Interface type(Motorola, TI, Microwire, Universal) 224 * @hierarchy: sets whether interface is master or slave 225 * @slave_tx_disable: SSPTXD is disconnected (in slave mode only) 226 * @clk_freq: Tune freq parameters of SSP(when in master mode) 227 * @endian_rx: Endianess of Data in Rx FIFO 228 * @endian_tx: Endianess of Data in Tx FIFO 229 * @data_size: Width of data element(4 to 32 bits) 230 * @com_mode: communication mode: polling, Interrupt or DMA 231 * @rx_lev_trig: Rx FIFO watermark level (for IT & DMA mode) 232 * @tx_lev_trig: Tx FIFO watermark level (for IT & DMA mode) 233 * @clk_phase: Motorola SPI interface Clock phase 234 * @clk_pol: Motorola SPI interface Clock polarity 235 * @ctrl_len: Microwire interface: Control length 236 * @wait_state: Microwire interface: Wait state 237 * @duplex: Microwire interface: Full/Half duplex 238 * @cs_control: function pointer to board-specific function to 239 * assert/deassert I/O port to control HW generation of devices chip-select. 240 * @dma_xfer_type: Type of DMA xfer (Mem-to-periph or Periph-to-Periph) 241 * @dma_config: DMA configuration for SSP controller and peripheral 242 */ 243 struct pl022_config_chip { 244 struct device *dev; 245 enum ssp_loopback lbm; 246 enum ssp_interface iface; 247 enum ssp_hierarchy hierarchy; 248 bool slave_tx_disable; 249 struct ssp_clock_params clk_freq; 250 enum ssp_rx_endian endian_rx; 251 enum ssp_tx_endian endian_tx; 252 enum ssp_data_size data_size; 253 enum ssp_mode com_mode; 254 enum ssp_rx_level_trig rx_lev_trig; 255 enum ssp_tx_level_trig tx_lev_trig; 256 enum ssp_spi_clk_phase clk_phase; 257 enum ssp_spi_clk_pol clk_pol; 258 enum ssp_microwire_ctrl_len ctrl_len; 259 enum ssp_microwire_wait_state wait_state; 260 enum ssp_duplex duplex; 261 void (*cs_control) (u32 control); 262 }; 263 264 #endif /* _SSP_PL022_H */ 265