1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * An RTC driver for Allwinner A31/A23 4 * 5 * Copyright (c) 2014, Chen-Yu Tsai <[email protected]> 6 * 7 * based on rtc-sunxi.c 8 * 9 * An RTC driver for Allwinner A10/A20 10 * 11 * Copyright (c) 2013, Carlo Caione <[email protected]> 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 16 #include <linux/delay.h> 17 #include <linux/err.h> 18 #include <linux/fs.h> 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_address.h> 26 #include <linux/of_device.h> 27 #include <linux/platform_device.h> 28 #include <linux/rtc.h> 29 #include <linux/slab.h> 30 #include <linux/types.h> 31 32 /* Control register */ 33 #define SUN6I_LOSC_CTRL 0x0000 34 #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16) 35 #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15) 36 #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9) 37 #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8) 38 #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7) 39 #define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4) 40 #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0) 41 #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7) 42 43 #define SUN6I_LOSC_CLK_PRESCAL 0x0008 44 45 /* RTC */ 46 #define SUN6I_RTC_YMD 0x0010 47 #define SUN6I_RTC_HMS 0x0014 48 49 /* Alarm 0 (counter) */ 50 #define SUN6I_ALRM_COUNTER 0x0020 51 /* This holds the remaining alarm seconds on older SoCs (current value) */ 52 #define SUN6I_ALRM_COUNTER_HMS 0x0024 53 #define SUN6I_ALRM_EN 0x0028 54 #define SUN6I_ALRM_EN_CNT_EN BIT(0) 55 #define SUN6I_ALRM_IRQ_EN 0x002c 56 #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0) 57 #define SUN6I_ALRM_IRQ_STA 0x0030 58 #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0) 59 60 /* Alarm 1 (wall clock) */ 61 #define SUN6I_ALRM1_EN 0x0044 62 #define SUN6I_ALRM1_IRQ_EN 0x0048 63 #define SUN6I_ALRM1_IRQ_STA 0x004c 64 #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0) 65 66 /* Alarm config */ 67 #define SUN6I_ALARM_CONFIG 0x0050 68 #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0) 69 70 #define SUN6I_LOSC_OUT_GATING 0x0060 71 #define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0 72 73 /* 74 * Get date values 75 */ 76 #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f) 77 #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8) 78 #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16) 79 #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22) 80 81 /* 82 * Get time values 83 */ 84 #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f) 85 #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8) 86 #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16) 87 88 /* 89 * Set date values 90 */ 91 #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f) 92 #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00) 93 #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000) 94 #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000) 95 96 /* 97 * Set time values 98 */ 99 #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f) 100 #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00) 101 #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000) 102 103 /* 104 * The year parameter passed to the driver is usually an offset relative to 105 * the year 1900. This macro is used to convert this offset to another one 106 * relative to the minimum year allowed by the hardware. 107 * 108 * The year range is 1970 - 2033. This range is selected to match Allwinner's 109 * driver, even though it is somewhat limited. 110 */ 111 #define SUN6I_YEAR_MIN 1970 112 #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900) 113 114 #define SECS_PER_DAY (24 * 3600ULL) 115 116 /* 117 * There are other differences between models, including: 118 * 119 * - number of GPIO pins that can be configured to hold a certain level 120 * - crypto-key related registers (H5, H6) 121 * - boot process related (super standby, secondary processor entry address) 122 * registers (R40, H6) 123 * - SYS power domain controls (R40) 124 * - DCXO controls (H6) 125 * - RC oscillator calibration (H6) 126 * 127 * These functions are not covered by this driver. 128 */ 129 struct sun6i_rtc_clk_data { 130 unsigned long rc_osc_rate; 131 unsigned int fixed_prescaler : 16; 132 unsigned int has_prescaler : 1; 133 unsigned int has_out_clk : 1; 134 unsigned int export_iosc : 1; 135 unsigned int has_losc_en : 1; 136 unsigned int has_auto_swt : 1; 137 }; 138 139 #define RTC_LINEAR_DAY BIT(0) 140 141 struct sun6i_rtc_dev { 142 struct rtc_device *rtc; 143 const struct sun6i_rtc_clk_data *data; 144 void __iomem *base; 145 int irq; 146 time64_t alarm; 147 unsigned long flags; 148 149 struct clk_hw hw; 150 struct clk_hw *int_osc; 151 struct clk *losc; 152 struct clk *ext_losc; 153 154 spinlock_t lock; 155 }; 156 157 static struct sun6i_rtc_dev *sun6i_rtc; 158 159 static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw, 160 unsigned long parent_rate) 161 { 162 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 163 u32 val = 0; 164 165 val = readl(rtc->base + SUN6I_LOSC_CTRL); 166 if (val & SUN6I_LOSC_CTRL_EXT_OSC) 167 return parent_rate; 168 169 if (rtc->data->fixed_prescaler) 170 parent_rate /= rtc->data->fixed_prescaler; 171 172 if (rtc->data->has_prescaler) { 173 val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL); 174 val &= GENMASK(4, 0); 175 } 176 177 return parent_rate / (val + 1); 178 } 179 180 static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw) 181 { 182 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 183 184 return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC; 185 } 186 187 static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index) 188 { 189 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 190 unsigned long flags; 191 u32 val; 192 193 if (index > 1) 194 return -EINVAL; 195 196 spin_lock_irqsave(&rtc->lock, flags); 197 val = readl(rtc->base + SUN6I_LOSC_CTRL); 198 val &= ~SUN6I_LOSC_CTRL_EXT_OSC; 199 val |= SUN6I_LOSC_CTRL_KEY; 200 val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0; 201 if (rtc->data->has_losc_en) { 202 val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN; 203 val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0; 204 } 205 writel(val, rtc->base + SUN6I_LOSC_CTRL); 206 spin_unlock_irqrestore(&rtc->lock, flags); 207 208 return 0; 209 } 210 211 static const struct clk_ops sun6i_rtc_osc_ops = { 212 .recalc_rate = sun6i_rtc_osc_recalc_rate, 213 214 .get_parent = sun6i_rtc_osc_get_parent, 215 .set_parent = sun6i_rtc_osc_set_parent, 216 }; 217 218 static void __init sun6i_rtc_clk_init(struct device_node *node, 219 const struct sun6i_rtc_clk_data *data) 220 { 221 struct clk_hw_onecell_data *clk_data; 222 struct sun6i_rtc_dev *rtc; 223 struct clk_init_data init = { 224 .ops = &sun6i_rtc_osc_ops, 225 .name = "losc", 226 }; 227 const char *iosc_name = "rtc-int-osc"; 228 const char *clkout_name = "osc32k-out"; 229 const char *parents[2]; 230 u32 reg; 231 232 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); 233 if (!rtc) 234 return; 235 236 rtc->data = data; 237 clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL); 238 if (!clk_data) { 239 kfree(rtc); 240 return; 241 } 242 243 spin_lock_init(&rtc->lock); 244 245 rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node)); 246 if (IS_ERR(rtc->base)) { 247 pr_crit("Can't map RTC registers"); 248 goto err; 249 } 250 251 reg = SUN6I_LOSC_CTRL_KEY; 252 if (rtc->data->has_auto_swt) { 253 /* Bypass auto-switch to int osc, on ext losc failure */ 254 reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS; 255 writel(reg, rtc->base + SUN6I_LOSC_CTRL); 256 } 257 258 /* Switch to the external, more precise, oscillator, if present */ 259 if (of_get_property(node, "clocks", NULL)) { 260 reg |= SUN6I_LOSC_CTRL_EXT_OSC; 261 if (rtc->data->has_losc_en) 262 reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; 263 } 264 writel(reg, rtc->base + SUN6I_LOSC_CTRL); 265 266 /* Yes, I know, this is ugly. */ 267 sun6i_rtc = rtc; 268 269 /* Only read IOSC name from device tree if it is exported */ 270 if (rtc->data->export_iosc) 271 of_property_read_string_index(node, "clock-output-names", 2, 272 &iosc_name); 273 274 rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL, 275 iosc_name, 276 NULL, 0, 277 rtc->data->rc_osc_rate, 278 300000000); 279 if (IS_ERR(rtc->int_osc)) { 280 pr_crit("Couldn't register the internal oscillator\n"); 281 goto err; 282 } 283 284 parents[0] = clk_hw_get_name(rtc->int_osc); 285 /* If there is no external oscillator, this will be NULL and ... */ 286 parents[1] = of_clk_get_parent_name(node, 0); 287 288 rtc->hw.init = &init; 289 290 init.parent_names = parents; 291 /* ... number of clock parents will be 1. */ 292 init.num_parents = of_clk_get_parent_count(node) + 1; 293 of_property_read_string_index(node, "clock-output-names", 0, 294 &init.name); 295 296 rtc->losc = clk_register(NULL, &rtc->hw); 297 if (IS_ERR(rtc->losc)) { 298 pr_crit("Couldn't register the LOSC clock\n"); 299 goto err_register; 300 } 301 302 of_property_read_string_index(node, "clock-output-names", 1, 303 &clkout_name); 304 rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name, 305 0, rtc->base + SUN6I_LOSC_OUT_GATING, 306 SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0, 307 &rtc->lock); 308 if (IS_ERR(rtc->ext_losc)) { 309 pr_crit("Couldn't register the LOSC external gate\n"); 310 goto err_register; 311 } 312 313 clk_data->num = 2; 314 clk_data->hws[0] = &rtc->hw; 315 clk_data->hws[1] = __clk_get_hw(rtc->ext_losc); 316 if (rtc->data->export_iosc) { 317 clk_data->hws[2] = rtc->int_osc; 318 clk_data->num = 3; 319 } 320 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 321 return; 322 323 err_register: 324 clk_hw_unregister_fixed_rate(rtc->int_osc); 325 err: 326 kfree(clk_data); 327 } 328 329 static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = { 330 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ 331 .has_prescaler = 1, 332 }; 333 334 static void __init sun6i_a31_rtc_clk_init(struct device_node *node) 335 { 336 sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data); 337 } 338 CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc", 339 sun6i_a31_rtc_clk_init); 340 341 static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = { 342 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ 343 .has_prescaler = 1, 344 .has_out_clk = 1, 345 }; 346 347 static void __init sun8i_a23_rtc_clk_init(struct device_node *node) 348 { 349 sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data); 350 } 351 CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc", 352 sun8i_a23_rtc_clk_init); 353 354 static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = { 355 .rc_osc_rate = 16000000, 356 .fixed_prescaler = 32, 357 .has_prescaler = 1, 358 .has_out_clk = 1, 359 .export_iosc = 1, 360 }; 361 362 static void __init sun8i_h3_rtc_clk_init(struct device_node *node) 363 { 364 sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data); 365 } 366 CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc", 367 sun8i_h3_rtc_clk_init); 368 /* As far as we are concerned, clocks for H5 are the same as H3 */ 369 CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc", 370 sun8i_h3_rtc_clk_init); 371 372 static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = { 373 .rc_osc_rate = 16000000, 374 .fixed_prescaler = 32, 375 .has_prescaler = 1, 376 .has_out_clk = 1, 377 .export_iosc = 1, 378 .has_losc_en = 1, 379 .has_auto_swt = 1, 380 }; 381 382 static void __init sun50i_h6_rtc_clk_init(struct device_node *node) 383 { 384 sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data); 385 } 386 CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc", 387 sun50i_h6_rtc_clk_init); 388 389 /* 390 * The R40 user manual is self-conflicting on whether the prescaler is 391 * fixed or configurable. The clock diagram shows it as fixed, but there 392 * is also a configurable divider in the RTC block. 393 */ 394 static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = { 395 .rc_osc_rate = 16000000, 396 .fixed_prescaler = 512, 397 }; 398 static void __init sun8i_r40_rtc_clk_init(struct device_node *node) 399 { 400 sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data); 401 } 402 CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc", 403 sun8i_r40_rtc_clk_init); 404 405 static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = { 406 .rc_osc_rate = 32000, 407 .has_out_clk = 1, 408 }; 409 410 static void __init sun8i_v3_rtc_clk_init(struct device_node *node) 411 { 412 sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data); 413 } 414 CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc", 415 sun8i_v3_rtc_clk_init); 416 417 static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id) 418 { 419 struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id; 420 irqreturn_t ret = IRQ_NONE; 421 u32 val; 422 423 spin_lock(&chip->lock); 424 val = readl(chip->base + SUN6I_ALRM_IRQ_STA); 425 426 if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) { 427 val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND; 428 writel(val, chip->base + SUN6I_ALRM_IRQ_STA); 429 430 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF); 431 432 ret = IRQ_HANDLED; 433 } 434 spin_unlock(&chip->lock); 435 436 return ret; 437 } 438 439 static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip) 440 { 441 u32 alrm_val = 0; 442 u32 alrm_irq_val = 0; 443 u32 alrm_wake_val = 0; 444 unsigned long flags; 445 446 if (to) { 447 alrm_val = SUN6I_ALRM_EN_CNT_EN; 448 alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN; 449 alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP; 450 } else { 451 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, 452 chip->base + SUN6I_ALRM_IRQ_STA); 453 } 454 455 spin_lock_irqsave(&chip->lock, flags); 456 writel(alrm_val, chip->base + SUN6I_ALRM_EN); 457 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); 458 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); 459 spin_unlock_irqrestore(&chip->lock, flags); 460 } 461 462 static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) 463 { 464 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 465 u32 date, time; 466 467 /* 468 * read again in case it changes 469 */ 470 do { 471 date = readl(chip->base + SUN6I_RTC_YMD); 472 time = readl(chip->base + SUN6I_RTC_HMS); 473 } while ((date != readl(chip->base + SUN6I_RTC_YMD)) || 474 (time != readl(chip->base + SUN6I_RTC_HMS))); 475 476 if (chip->flags & RTC_LINEAR_DAY) { 477 /* 478 * Newer chips store a linear day number, the manual 479 * does not mandate any epoch base. The BSP driver uses 480 * the UNIX epoch, let's just copy that, as it's the 481 * easiest anyway. 482 */ 483 rtc_time64_to_tm((date & 0xffff) * SECS_PER_DAY, rtc_tm); 484 } else { 485 rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date); 486 rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date) - 1; 487 rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date); 488 489 /* 490 * switch from (data_year->min)-relative offset to 491 * a (1900)-relative one 492 */ 493 rtc_tm->tm_year += SUN6I_YEAR_OFF; 494 } 495 496 rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time); 497 rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time); 498 rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time); 499 500 return 0; 501 } 502 503 static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm) 504 { 505 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 506 unsigned long flags; 507 u32 alrm_st; 508 u32 alrm_en; 509 510 spin_lock_irqsave(&chip->lock, flags); 511 alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN); 512 alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA); 513 spin_unlock_irqrestore(&chip->lock, flags); 514 515 wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN); 516 wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN); 517 rtc_time64_to_tm(chip->alarm, &wkalrm->time); 518 519 return 0; 520 } 521 522 static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) 523 { 524 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 525 struct rtc_time *alrm_tm = &wkalrm->time; 526 struct rtc_time tm_now; 527 time64_t time_set; 528 u32 counter_val, counter_val_hms; 529 int ret; 530 531 time_set = rtc_tm_to_time64(alrm_tm); 532 533 if (chip->flags & RTC_LINEAR_DAY) { 534 /* 535 * The alarm registers hold the actual alarm time, encoded 536 * in the same way (linear day + HMS) as the current time. 537 */ 538 counter_val_hms = SUN6I_TIME_SET_SEC_VALUE(alrm_tm->tm_sec) | 539 SUN6I_TIME_SET_MIN_VALUE(alrm_tm->tm_min) | 540 SUN6I_TIME_SET_HOUR_VALUE(alrm_tm->tm_hour); 541 /* The division will cut off the H:M:S part of alrm_tm. */ 542 counter_val = div_u64(rtc_tm_to_time64(alrm_tm), SECS_PER_DAY); 543 } else { 544 /* The alarm register holds the number of seconds left. */ 545 time64_t time_now; 546 547 ret = sun6i_rtc_gettime(dev, &tm_now); 548 if (ret < 0) { 549 dev_err(dev, "Error in getting time\n"); 550 return -EINVAL; 551 } 552 553 time_now = rtc_tm_to_time64(&tm_now); 554 if (time_set <= time_now) { 555 dev_err(dev, "Date to set in the past\n"); 556 return -EINVAL; 557 } 558 if ((time_set - time_now) > U32_MAX) { 559 dev_err(dev, "Date too far in the future\n"); 560 return -EINVAL; 561 } 562 563 counter_val = time_set - time_now; 564 } 565 566 sun6i_rtc_setaie(0, chip); 567 writel(0, chip->base + SUN6I_ALRM_COUNTER); 568 if (chip->flags & RTC_LINEAR_DAY) 569 writel(0, chip->base + SUN6I_ALRM_COUNTER_HMS); 570 usleep_range(100, 300); 571 572 writel(counter_val, chip->base + SUN6I_ALRM_COUNTER); 573 if (chip->flags & RTC_LINEAR_DAY) 574 writel(counter_val_hms, chip->base + SUN6I_ALRM_COUNTER_HMS); 575 chip->alarm = time_set; 576 577 sun6i_rtc_setaie(wkalrm->enabled, chip); 578 579 return 0; 580 } 581 582 static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset, 583 unsigned int mask, unsigned int ms_timeout) 584 { 585 const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout); 586 u32 reg; 587 588 do { 589 reg = readl(chip->base + offset); 590 reg &= mask; 591 592 if (!reg) 593 return 0; 594 595 } while (time_before(jiffies, timeout)); 596 597 return -ETIMEDOUT; 598 } 599 600 static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm) 601 { 602 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 603 u32 date = 0; 604 u32 time = 0; 605 606 time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) | 607 SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) | 608 SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour); 609 610 if (chip->flags & RTC_LINEAR_DAY) { 611 /* The division will cut off the H:M:S part of rtc_tm. */ 612 date = div_u64(rtc_tm_to_time64(rtc_tm), SECS_PER_DAY); 613 } else { 614 rtc_tm->tm_year -= SUN6I_YEAR_OFF; 615 rtc_tm->tm_mon += 1; 616 617 date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) | 618 SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) | 619 SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year); 620 621 if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN)) 622 date |= SUN6I_LEAP_SET_VALUE(1); 623 } 624 625 /* Check whether registers are writable */ 626 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 627 SUN6I_LOSC_CTRL_ACC_MASK, 50)) { 628 dev_err(dev, "rtc is still busy.\n"); 629 return -EBUSY; 630 } 631 632 writel(time, chip->base + SUN6I_RTC_HMS); 633 634 /* 635 * After writing the RTC HH-MM-SS register, the 636 * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not 637 * be cleared until the real writing operation is finished 638 */ 639 640 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 641 SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) { 642 dev_err(dev, "Failed to set rtc time.\n"); 643 return -ETIMEDOUT; 644 } 645 646 writel(date, chip->base + SUN6I_RTC_YMD); 647 648 /* 649 * After writing the RTC YY-MM-DD register, the 650 * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not 651 * be cleared until the real writing operation is finished 652 */ 653 654 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 655 SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) { 656 dev_err(dev, "Failed to set rtc time.\n"); 657 return -ETIMEDOUT; 658 } 659 660 return 0; 661 } 662 663 static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 664 { 665 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 666 667 if (!enabled) 668 sun6i_rtc_setaie(enabled, chip); 669 670 return 0; 671 } 672 673 static const struct rtc_class_ops sun6i_rtc_ops = { 674 .read_time = sun6i_rtc_gettime, 675 .set_time = sun6i_rtc_settime, 676 .read_alarm = sun6i_rtc_getalarm, 677 .set_alarm = sun6i_rtc_setalarm, 678 .alarm_irq_enable = sun6i_rtc_alarm_irq_enable 679 }; 680 681 #ifdef CONFIG_PM_SLEEP 682 /* Enable IRQ wake on suspend, to wake up from RTC. */ 683 static int sun6i_rtc_suspend(struct device *dev) 684 { 685 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 686 687 if (device_may_wakeup(dev)) 688 enable_irq_wake(chip->irq); 689 690 return 0; 691 } 692 693 /* Disable IRQ wake on resume. */ 694 static int sun6i_rtc_resume(struct device *dev) 695 { 696 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 697 698 if (device_may_wakeup(dev)) 699 disable_irq_wake(chip->irq); 700 701 return 0; 702 } 703 #endif 704 705 static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops, 706 sun6i_rtc_suspend, sun6i_rtc_resume); 707 708 static void sun6i_rtc_bus_clk_cleanup(void *data) 709 { 710 struct clk *bus_clk = data; 711 712 clk_disable_unprepare(bus_clk); 713 } 714 715 static int sun6i_rtc_probe(struct platform_device *pdev) 716 { 717 struct sun6i_rtc_dev *chip = sun6i_rtc; 718 struct device *dev = &pdev->dev; 719 struct clk *bus_clk; 720 int ret; 721 722 bus_clk = devm_clk_get_optional(dev, "bus"); 723 if (IS_ERR(bus_clk)) 724 return PTR_ERR(bus_clk); 725 726 if (bus_clk) { 727 ret = clk_prepare_enable(bus_clk); 728 if (ret) 729 return ret; 730 731 ret = devm_add_action_or_reset(dev, sun6i_rtc_bus_clk_cleanup, 732 bus_clk); 733 if (ret) 734 return ret; 735 } 736 737 if (!chip) { 738 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 739 if (!chip) 740 return -ENOMEM; 741 742 spin_lock_init(&chip->lock); 743 744 chip->base = devm_platform_ioremap_resource(pdev, 0); 745 if (IS_ERR(chip->base)) 746 return PTR_ERR(chip->base); 747 } 748 749 platform_set_drvdata(pdev, chip); 750 751 chip->flags = (unsigned long)of_device_get_match_data(&pdev->dev); 752 753 chip->irq = platform_get_irq(pdev, 0); 754 if (chip->irq < 0) 755 return chip->irq; 756 757 ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq, 758 0, dev_name(&pdev->dev), chip); 759 if (ret) { 760 dev_err(&pdev->dev, "Could not request IRQ\n"); 761 return ret; 762 } 763 764 /* clear the alarm counter value */ 765 writel(0, chip->base + SUN6I_ALRM_COUNTER); 766 767 /* disable counter alarm */ 768 writel(0, chip->base + SUN6I_ALRM_EN); 769 770 /* disable counter alarm interrupt */ 771 writel(0, chip->base + SUN6I_ALRM_IRQ_EN); 772 773 /* disable week alarm */ 774 writel(0, chip->base + SUN6I_ALRM1_EN); 775 776 /* disable week alarm interrupt */ 777 writel(0, chip->base + SUN6I_ALRM1_IRQ_EN); 778 779 /* clear counter alarm pending interrupts */ 780 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, 781 chip->base + SUN6I_ALRM_IRQ_STA); 782 783 /* clear week alarm pending interrupts */ 784 writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND, 785 chip->base + SUN6I_ALRM1_IRQ_STA); 786 787 /* disable alarm wakeup */ 788 writel(0, chip->base + SUN6I_ALARM_CONFIG); 789 790 clk_prepare_enable(chip->losc); 791 792 device_init_wakeup(&pdev->dev, 1); 793 794 chip->rtc = devm_rtc_allocate_device(&pdev->dev); 795 if (IS_ERR(chip->rtc)) 796 return PTR_ERR(chip->rtc); 797 798 chip->rtc->ops = &sun6i_rtc_ops; 799 if (chip->flags & RTC_LINEAR_DAY) 800 chip->rtc->range_max = (65536 * SECS_PER_DAY) - 1; 801 else 802 chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */ 803 804 ret = devm_rtc_register_device(chip->rtc); 805 if (ret) 806 return ret; 807 808 dev_info(&pdev->dev, "RTC enabled\n"); 809 810 return 0; 811 } 812 813 /* 814 * As far as RTC functionality goes, all models are the same. The 815 * datasheets claim that different models have different number of 816 * registers available for non-volatile storage, but experiments show 817 * that all SoCs have 16 registers available for this purpose. 818 */ 819 static const struct of_device_id sun6i_rtc_dt_ids[] = { 820 { .compatible = "allwinner,sun6i-a31-rtc" }, 821 { .compatible = "allwinner,sun8i-a23-rtc" }, 822 { .compatible = "allwinner,sun8i-h3-rtc" }, 823 { .compatible = "allwinner,sun8i-r40-rtc" }, 824 { .compatible = "allwinner,sun8i-v3-rtc" }, 825 { .compatible = "allwinner,sun50i-h5-rtc" }, 826 { .compatible = "allwinner,sun50i-h6-rtc" }, 827 { /* sentinel */ }, 828 }; 829 MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); 830 831 static struct platform_driver sun6i_rtc_driver = { 832 .probe = sun6i_rtc_probe, 833 .driver = { 834 .name = "sun6i-rtc", 835 .of_match_table = sun6i_rtc_dt_ids, 836 .pm = &sun6i_rtc_pm_ops, 837 }, 838 }; 839 builtin_platform_driver(sun6i_rtc_driver); 840